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Commit 5c6dc6c9a9a5f253f3928a97ca020712177884e7

Authored by Laurentiu Tudor
Committed by Prabhakar Kushwaha
1 parent aef654a2ed
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

armv8: ls1088a: add icid setup for platform devices 

Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec. The ICID macros for SEC needed to be adapted because
the format of the registers is different.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Showing 6 changed files with 89 additions and 10 deletions Side-by-side Diff

arch/arm/cpu/armv8/fsl-layerscape/Makefile
Diff comments   View file @ 5c6dc6c
... ... @@ -47,6 +47,7 @@
47 47  
48 48 ifneq ($(CONFIG_ARCH_LS1088A),)
49 49 obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
  50 +obj-y += icid.o ls1088_ids.o
50 51 endif
51 52  
52 53 ifneq ($(CONFIG_ARCH_LS1028A),)
arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
Diff comments   View file @ 5c6dc6c
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2019 NXP
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <asm/arch-fsl-layerscape/immap_lsch3.h>
  8 +#include <asm/arch-fsl-layerscape/fsl_icid.h>
  9 +#include <asm/arch-fsl-layerscape/fsl_portals.h>
  10 +
  11 +struct icid_id_table icid_tbl[] = {
  12 + SET_SDHC_ICID(FSL_SDMMC_STREAM_ID),
  13 + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
  14 + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
  15 + SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
  16 + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
  17 + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
  18 + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
  19 + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
  20 + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
  21 + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
  22 + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
  23 + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
  24 + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
  25 + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
  26 + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
  27 + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
  28 +};
  29 +
  30 +int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
arch/arm/cpu/armv8/fsl-layerscape/soc.c
Diff comments   View file @ 5c6dc6c
... ... @@ -340,6 +340,10 @@
340 340 if (fsl_check_boot_mode_secure() == 1)
341 341 bypass_smmu();
342 342 #endif
  343 +
  344 +#ifdef CONFIG_ARCH_LS1088A
  345 + set_icids();
  346 +#endif
343 347 }
344 348  
345 349 /* Get VDD in the unit mV from voltage ID */
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
Diff comments   View file @ 5c6dc6c
... ... @@ -40,6 +40,14 @@
40 40 .le = _le \
41 41 }
42 42  
  43 +#ifdef CONFIG_SYS_FSL_SEC_LE
  44 +#define SEC_IS_LE true
  45 +#elif defined(CONFIG_SYS_FSL_SEC_BE)
  46 +#define SEC_IS_LE false
  47 +#endif
  48 +
  49 +#ifdef CONFIG_FSL_LSCH2
  50 +
43 51 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
44 52 #define SCFG_IS_LE true
45 53 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
... ... @@ -100,11 +108,7 @@
100 108 #define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
101 109 { .port_id = (_port_id), .icid = (streamid) }
102 110  
103   -#ifdef CONFIG_SYS_FSL_SEC_LE
104   -#define SEC_IS_LE true
105   -#elif defined(CONFIG_SYS_FSL_SEC_BE)
106   -#define SEC_IS_LE false
107   -#endif
  111 +#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
108 112  
109 113 #define SET_SEC_QI_ICID(streamid) \
110 114 SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
... ... @@ -112,6 +116,38 @@
112 116 CONFIG_SYS_FSL_SEC_ADDR, \
113 117 CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
114 118  
  119 +extern struct fman_icid_id_table fman_icid_tbl[];
  120 +extern int fman_icid_tbl_sz;
  121 +
  122 +#else /* CONFIG_FSL_LSCH2 */
  123 +
  124 +#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
  125 +#define GUR_IS_LE true
  126 +#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
  127 +#define GUR_IS_LE false
  128 +#endif
  129 +
  130 +#define SET_GUR_ICID(compat, streamid, name, compataddr) \
  131 + SET_ICID_ENTRY(compat, streamid, streamid, \
  132 + offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
  133 + compataddr, GUR_IS_LE)
  134 +
  135 +#define SET_USB_ICID(usb_num, compat, streamid) \
  136 + SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
  137 + CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
  138 +
  139 +#define SET_SATA_ICID(sata_num, compat, streamid) \
  140 + SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
  141 + AHCI_BASE_ADDR##sata_num)
  142 +
  143 +#define SET_SDHC_ICID(streamid) \
  144 + SET_GUR_ICID("fsl,esdhc", streamid, sdmm1_amqr,\
  145 + CONFIG_SYS_FSL_ESDHC_ADDR)
  146 +
  147 +#define SEC_ICID_REG_VAL(streamid) (streamid)
  148 +
  149 +#endif /* CONFIG_FSL_LSCH2 */
  150 +
115 151 #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
116 152 SET_ICID_ENTRY( \
117 153 (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \
118 154  
119 155  
120 156  
121 157  
... ... @@ -120,25 +156,23 @@
120 156 ? NULL \
121 157 : "fsl,sec-v4.0-job-ring"), \
122 158 streamid, \
123   - (((streamid) << 16) | (streamid)), \
  159 + SEC_ICID_REG_VAL(streamid), \
124 160 offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
125 161 CONFIG_SYS_FSL_SEC_ADDR, \
126 162 FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
127 163  
128 164 #define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
129   - SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
  165 + SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
130 166 offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
131 167 CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
132 168  
133 169 #define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
134   - SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
  170 + SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
135 171 offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
136 172 CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
137 173  
138 174 extern struct icid_id_table icid_tbl[];
139   -extern struct fman_icid_id_table fman_icid_tbl[];
140 175 extern int icid_tbl_sz;
141   -extern int fman_icid_tbl_sz;
142 176  
143 177 #endif
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
Diff comments   View file @ 5c6dc6c
... ... @@ -98,5 +98,11 @@
98 98 #define FSL_DPAA2_STREAM_ID_START 23
99 99 #define FSL_DPAA2_STREAM_ID_END 63
100 100  
  101 +#define FSL_SEC_STREAM_ID 64
  102 +#define FSL_SEC_JR1_STREAM_ID 65
  103 +#define FSL_SEC_JR2_STREAM_ID 66
  104 +#define FSL_SEC_JR3_STREAM_ID 67
  105 +#define FSL_SEC_JR4_STREAM_ID 68
  106 +
101 107 #endif
board/freescale/ls1088a/ls1088a.c
Diff comments   View file @ 5c6dc6c
... ... @@ -21,6 +21,7 @@
21 21 #include <hwconfig.h>
22 22 #include <asm/arch/fsl_serdes.h>
23 23 #include <asm/arch/soc.h>
  24 +#include <asm/arch-fsl-layerscape/fsl_icid.h>
24 25  
25 26 #include "../common/qixis.h"
26 27 #include "ls1088a_qixis.h"
... ... @@ -968,6 +969,9 @@
968 969 #ifdef CONFIG_FSL_MC_ENET
969 970 fdt_fixup_board_enet(blob);
970 971 #endif
  972 +
  973 + fdt_fixup_icid(blob);
  974 +
971 975 if (is_pb_board())
972 976 fixup_ls1088ardb_pb_banner(blob);
973 977