ARM: keystone2: add K2E SoC hardware definitions

This patch adds hardware definitions specific to Keystone II K2E device. It has a lot common definitions with k2hk SoC, so move them to common hardware.h. This is preparation patch for adding K2E SoC support. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

ARM: keystone2: add K2E SoC hardware definitions
This patch adds hardware definitions specific to Keystone II K2E device. It has a lot common definitions with k2hk SoC, so move them to common hardware.h. This is preparation patch for adding K2E SoC support. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Hao Zhang · Tom Rini
1 parent b1babef856
Showing 3 changed files with 105 additions and 44 deletions Side-by-side Diff
arch/arm/include/asm/arch-keystone/hardware-k2e.h
arch/arm/include/asm/arch-keystone/hardware-k2hk.h
arch/arm/include/asm/arch-keystone/hardware.h
+/*
+ * K2E: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2E_H
+#define __ASM_ARCH_HARDWARE_K2E_H
+
+/* PA SS Registers */
+#define KS2_PASS_BASE			0x24000000
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_MOD_RST		0
+#define KS2_LPSC_USB_1			1
+#define KS2_LPSC_USB			2
+#define KS2_LPSC_EMIF25_SPI		3
+#define KS2_LPSC_TSIP			4
+#define KS2_LPSC_DEBUGSS_TRC		5
+#define KS2_LPSC_TETB_TRC		6
+#define KS2_LPSC_PKTPROC		7
+#define KS2_LPSC_PA			KS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII			8
+#define KS2_LPSC_CPGMAC			KS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO			9
+#define KS2_LPSC_PCIE			10
+#define KS2_LPSC_VUSR0			12
+#define KS2_LPSC_CHIP_SRSS		13
+#define KS2_LPSC_MSMC			14
+#define KS2_LPSC_EMIF4F_DDR3		23
+#define KS2_LPSC_PCIE_1			27
+#define KS2_LPSC_XGE			50
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM	-1	/* not defined in K2E */
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM	-1	/* not defined in K2E */
+
+/* Number of DSP cores */
+#define KS2_NUM_DSPS			1
+
+#endif
@@ -10,46 +10,16 @@
 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
 #define __ASM_ARCH_HARDWARE_K2HK_H
  
-#define KS2_PLL_CNTRL_BASE		0x02310000
-#define KS2_CLOCK_BASE			KS2_PLL_CNTRL_BASE
-#define KS2_RSTCTRL			(KS2_PLL_CNTRL_BASE + 0xe8)
-#define KS2_RSTCTRL_KEY			0x5a69
-#define KS2_RSTCTRL_MASK		0xffff0000
-#define KS2_RSTCTRL_SWRST		0xfffe0000
-
-#define KS2_DEVICE_STATE_CTRL_BASE	0x02620000
-#define KS2_JTAG_ID_REG			(KS2_DEVICE_STATE_CTRL_BASE + 0x18)
-#define KS2_DEVSTAT			(KS2_DEVICE_STATE_CTRL_BASE + 0x20)
-
 #define KS2_MISC_CTRL			(KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
  
 #define KS2_ARM_PLL_EN			BIT(13)
  
-#define KS2_SPI0_BASE			0x21000400
-#define KS2_SPI1_BASE			0x21000600
-#define KS2_SPI2_BASE			0x21000800
-#define KS2_SPI_BASE			KS2_SPI0_BASE
-
-/* Chip configuration unlock codes and registers */
-#define KS2_KICK0			(KS2_DEVICE_STATE_CTRL_BASE + 0x38)
-#define KS2_KICK1			(KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
-#define KS2_KICK0_MAGIC			0x83e70b13
-#define KS2_KICK1_MAGIC			0x95a4f1e0
-
 /* PA SS Registers */
 #define KS2_PASS_BASE			0x02000000
  
 /* PLL control registers */
-#define KS2_MAINPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x350)
-#define KS2_MAINPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x354)
-#define KS2_PASSPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x358)
-#define KS2_PASSPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
-#define KS2_DDR3APLLCTL0		(KS2_DEVICE_STATE_CTRL_BASE + 0x360)
-#define KS2_DDR3APLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x364)
 #define KS2_DDR3BPLLCTL0		(KS2_DEVICE_STATE_CTRL_BASE + 0x368)
 #define KS2_DDR3BPLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
-#define KS2_ARMPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x370)
-#define KS2_ARMPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x374)
  
 /* Power and Sleep Controller (PSC) Domains */
 #define KS2_LPSC_MOD			0
  
@@ -106,24 +76,10 @@
 #define KS2_LPSC_XGE			50
 #define KS2_LPSC_ARM_SREFLEX		51
  
-/* DDR3A definitions */
-#define KS2_DDR3A_EMIF_CTRL_BASE	0x21010000
-#define KS2_DDR3A_EMIF_DATA_BASE	0x80000000
-#define KS2_DDR3A_DDRPHYC		0x02329000
 /* DDR3B definitions */
 #define KS2_DDR3B_EMIF_CTRL_BASE	0x21020000
 #define KS2_DDR3B_EMIF_DATA_BASE	0x60000000
 #define KS2_DDR3B_DDRPHYC		0x02328000
-
-/* Queue manager */
-#define KS2_QM_MANAGER_BASE		0x02a02000
-#define KS2_QM_DESC_SETUP_BASE		0x02a03000
-#define KS2_QM_MANAGER_QUEUES_BASEi	0x02a80000
-#define KS2_QM_MANAGER_Q_PROXY_BASE	0x02ac0000
-#define KS2_QM_QUEUE_STATUS_BASE	0x02a40000
-
-/* MSMC control */
-#define KS2_MSMC_CTRL_BASE		0x0bc00000
  
 /* Number of DSP cores */
 #define KS2_NUM_DSPS			8
@@ -69,6 +69,11 @@
 #define NOSRA_MASK                      0x08000000
 #define ECC_MASK                        0x00000001
  
+/* DDR3 definitions */
+#define KS2_DDR3A_EMIF_CTRL_BASE	0x21010000
+#define KS2_DDR3A_EMIF_DATA_BASE	0x80000000
+#define KS2_DDR3A_DDRPHYC		0x02329000
+
 #define KS2_DDR3_MIDR_OFFSET            0x00
 #define KS2_DDR3_STATUS_OFFSET          0x04
 #define KS2_DDR3_SDCFG_OFFSET           0x08
  
@@ -85,12 +90,46 @@
 #define KS2_UART0_BASE                	0x02530c00
 #define KS2_UART1_BASE                	0x02531000
  
+/* Boot Config */
+#define KS2_DEVICE_STATE_CTRL_BASE	0x02620000
+#define KS2_JTAG_ID_REG			(KS2_DEVICE_STATE_CTRL_BASE + 0x18)
+#define KS2_DEVSTAT			(KS2_DEVICE_STATE_CTRL_BASE + 0x20)
+
 /* PSC */
 #define KS2_PSC_BASE			0x02350000
 #define KS2_LPSC_GEM_0			15
 #define KS2_LPSC_TETRIS			52
 #define KS2_TETRIS_PWR_DOMAIN		31
  
+/* Chip configuration unlock codes and registers */
+#define KS2_KICK0			(KS2_DEVICE_STATE_CTRL_BASE + 0x38)
+#define KS2_KICK1			(KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
+#define KS2_KICK0_MAGIC			0x83e70b13
+#define KS2_KICK1_MAGIC			0x95a4f1e0
+
+/* PLL control registers */
+#define KS2_MAINPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x350)
+#define KS2_MAINPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x354)
+#define KS2_PASSPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x358)
+#define KS2_PASSPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
+#define KS2_DDR3APLLCTL0		(KS2_DEVICE_STATE_CTRL_BASE + 0x360)
+#define KS2_DDR3APLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x364)
+#define KS2_ARMPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x370)
+#define KS2_ARMPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+
+#define KS2_PLL_CNTRL_BASE		0x02310000
+#define KS2_CLOCK_BASE			KS2_PLL_CNTRL_BASE
+#define KS2_RSTCTRL			(KS2_PLL_CNTRL_BASE + 0xe8)
+#define KS2_RSTCTRL_KEY			0x5a69
+#define KS2_RSTCTRL_MASK		0xffff0000
+#define KS2_RSTCTRL_SWRST		0xfffe0000
+
+/* SPI */
+#define KS2_SPI0_BASE			0x21000400
+#define KS2_SPI1_BASE			0x21000600
+#define KS2_SPI2_BASE			0x21000800
+#define KS2_SPI_BASE			KS2_SPI0_BASE
+
 /* AEMIF */
 #define KS2_AEMIF_CNTRL_BASE       	0x21000a00
 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE   KS2_AEMIF_CNTRL_BASE
  
@@ -98,10 +137,24 @@
 /* Flag from ks2_debug options to check if DSPs need to stay ON */
 #define DBG_LEAVE_DSPS_ON		0x1
  
+/* Queue manager */
+#define KS2_QM_MANAGER_BASE		0x02a02000
+#define KS2_QM_DESC_SETUP_BASE		0x02a03000
+#define KS2_QM_MANAGER_QUEUES_BASEi	0x02a80000
+#define KS2_QM_MANAGER_Q_PROXY_BASE	0x02ac0000
+#define KS2_QM_QUEUE_STATUS_BASE	0x02a40000
+
+/* MSMC control */
+#define KS2_MSMC_CTRL_BASE		0x0bc00000
+
 #ifdef CONFIG_SOC_K2HK
 #include <asm/arch/hardware-k2hk.h>
 #endif
  
+#ifdef CONFIG_SOC_K2E
+#include <asm/arch/hardware-k2e.h>
+#endif
+
 #ifndef __ASSEMBLY__
 static inline int cpu_is_k2hk(void)
 {
@@ -109,6 +162,14 @@
 	unsigned int part_no	= (jtag_id >> 12) & 0xffff;
  
 	return (part_no == 0xb981) ? 1 : 0;
+}
+
+static inline int cpu_is_k2e(void)
+{
+	unsigned int jtag_id    = __raw_readl(KS2_JTAG_ID_REG);
+	unsigned int part_no    = (jtag_id >> 12) & 0xffff;
+
+	return (part_no == 0xb9a6) ? 1 : 0;
 }
  
 static inline int cpu_revision(void)
	1	+/*
	2	+ * K2E: SoC definitions
	3	+ *
	4	+ * (C) Copyright 2012-2014
	5	+ * Texas Instruments Incorporated, <www.ti.com>
	6	+ *
	7	+ * SPDX-License-Identifier: GPL-2.0+
	8	+ */
	9	+
	10	+#ifndef __ASM_ARCH_HARDWARE_K2E_H
	11	+#define __ASM_ARCH_HARDWARE_K2E_H
	12	+
	13	+/* PA SS Registers */
	14	+#define KS2_PASS_BASE 0x24000000
	15	+
	16	+/* Power and Sleep Controller (PSC) Domains */
	17	+#define KS2_LPSC_MOD_RST 0
	18	+#define KS2_LPSC_USB_1 1
	19	+#define KS2_LPSC_USB 2
	20	+#define KS2_LPSC_EMIF25_SPI 3
	21	+#define KS2_LPSC_TSIP 4
	22	+#define KS2_LPSC_DEBUGSS_TRC 5
	23	+#define KS2_LPSC_TETB_TRC 6
	24	+#define KS2_LPSC_PKTPROC 7
	25	+#define KS2_LPSC_PA KS2_LPSC_PKTPROC
	26	+#define KS2_LPSC_SGMII 8
	27	+#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
	28	+#define KS2_LPSC_CRYPTO 9
	29	+#define KS2_LPSC_PCIE 10
	30	+#define KS2_LPSC_VUSR0 12
	31	+#define KS2_LPSC_CHIP_SRSS 13
	32	+#define KS2_LPSC_MSMC 14
	33	+#define KS2_LPSC_EMIF4F_DDR3 23
	34	+#define KS2_LPSC_PCIE_1 27
	35	+#define KS2_LPSC_XGE 50
	36	+
	37	+/* Chip Interrupt Controller */
	38	+#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
	39	+#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
	40	+
	41	+/* Number of DSP cores */
	42	+#define KS2_NUM_DSPS 1
	43	+
	44	+#endif
...	...	@@ -10,46 +10,16 @@
10	10	#ifndef __ASM_ARCH_HARDWARE_K2HK_H
11	11	#define __ASM_ARCH_HARDWARE_K2HK_H
12	12
13		-#define KS2_PLL_CNTRL_BASE 0x02310000
14		-#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
15		-#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
16		-#define KS2_RSTCTRL_KEY 0x5a69
17		-#define KS2_RSTCTRL_MASK 0xffff0000
18		-#define KS2_RSTCTRL_SWRST 0xfffe0000
19		-
20		-#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
21		-#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
22		-#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
23		-
24	13	#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
25	14
26	15	#define KS2_ARM_PLL_EN BIT(13)
27	16
28		-#define KS2_SPI0_BASE 0x21000400
29		-#define KS2_SPI1_BASE 0x21000600
30		-#define KS2_SPI2_BASE 0x21000800
31		-#define KS2_SPI_BASE KS2_SPI0_BASE
32		-
33		-/* Chip configuration unlock codes and registers */
34		-#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
35		-#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
36		-#define KS2_KICK0_MAGIC 0x83e70b13
37		-#define KS2_KICK1_MAGIC 0x95a4f1e0
38		-
39	17	/* PA SS Registers */
40	18	#define KS2_PASS_BASE 0x02000000
41	19
42	20	/* PLL control registers */
43		-#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
44		-#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
45		-#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
46		-#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
47		-#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
48		-#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
49	21	#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
50	22	#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
51		-#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
52		-#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
53	23
54	24	/* Power and Sleep Controller (PSC) Domains */
55	25	#define KS2_LPSC_MOD 0
56	26
...	...	@@ -106,24 +76,10 @@
106	76	#define KS2_LPSC_XGE 50
107	77	#define KS2_LPSC_ARM_SREFLEX 51
108	78
109		-/* DDR3A definitions */
110		-#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
111		-#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
112		-#define KS2_DDR3A_DDRPHYC 0x02329000
113	79	/* DDR3B definitions */
114	80	#define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000
115	81	#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
116	82	#define KS2_DDR3B_DDRPHYC 0x02328000
117		-
118		-/* Queue manager */
119		-#define KS2_QM_MANAGER_BASE 0x02a02000
120		-#define KS2_QM_DESC_SETUP_BASE 0x02a03000
121		-#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000
122		-#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
123		-#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
124		-
125		-/* MSMC control */
126		-#define KS2_MSMC_CTRL_BASE 0x0bc00000
127	83
128	84	/* Number of DSP cores */
129	85	#define KS2_NUM_DSPS 8
...	...	@@ -69,6 +69,11 @@
69	69	#define NOSRA_MASK 0x08000000
70	70	#define ECC_MASK 0x00000001
71	71
	72	+/* DDR3 definitions */
	73	+#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
	74	+#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
	75	+#define KS2_DDR3A_DDRPHYC 0x02329000
	76	+
72	77	#define KS2_DDR3_MIDR_OFFSET 0x00
73	78	#define KS2_DDR3_STATUS_OFFSET 0x04
74	79	#define KS2_DDR3_SDCFG_OFFSET 0x08
75	80
...	...	@@ -85,12 +90,46 @@
85	90	#define KS2_UART0_BASE 0x02530c00
86	91	#define KS2_UART1_BASE 0x02531000
87	92
	93	+/* Boot Config */
	94	+#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
	95	+#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
	96	+#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
	97	+
88	98	/* PSC */
89	99	#define KS2_PSC_BASE 0x02350000
90	100	#define KS2_LPSC_GEM_0 15
91	101	#define KS2_LPSC_TETRIS 52
92	102	#define KS2_TETRIS_PWR_DOMAIN 31
93	103
	104	+/* Chip configuration unlock codes and registers */
	105	+#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
	106	+#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
	107	+#define KS2_KICK0_MAGIC 0x83e70b13
	108	+#define KS2_KICK1_MAGIC 0x95a4f1e0
	109	+
	110	+/* PLL control registers */
	111	+#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
	112	+#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
	113	+#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
	114	+#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
	115	+#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
	116	+#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
	117	+#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
	118	+#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
	119	+
	120	+#define KS2_PLL_CNTRL_BASE 0x02310000
	121	+#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
	122	+#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
	123	+#define KS2_RSTCTRL_KEY 0x5a69
	124	+#define KS2_RSTCTRL_MASK 0xffff0000
	125	+#define KS2_RSTCTRL_SWRST 0xfffe0000
	126	+
	127	+/* SPI */
	128	+#define KS2_SPI0_BASE 0x21000400
	129	+#define KS2_SPI1_BASE 0x21000600
	130	+#define KS2_SPI2_BASE 0x21000800
	131	+#define KS2_SPI_BASE KS2_SPI0_BASE
	132	+
94	133	/* AEMIF */
95	134	#define KS2_AEMIF_CNTRL_BASE 0x21000a00
96	135	#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
97	136
...	...	@@ -98,10 +137,24 @@
98	137	/* Flag from ks2_debug options to check if DSPs need to stay ON */
99	138	#define DBG_LEAVE_DSPS_ON 0x1
100	139
	140	+/* Queue manager */
	141	+#define KS2_QM_MANAGER_BASE 0x02a02000
	142	+#define KS2_QM_DESC_SETUP_BASE 0x02a03000
	143	+#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000
	144	+#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
	145	+#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
	146	+
	147	+/* MSMC control */
	148	+#define KS2_MSMC_CTRL_BASE 0x0bc00000
	149	+
101	150	#ifdef CONFIG_SOC_K2HK
102	151	#include <asm/arch/hardware-k2hk.h>
103	152	#endif
104	153
	154	+#ifdef CONFIG_SOC_K2E
	155	+#include <asm/arch/hardware-k2e.h>
	156	+#endif
	157	+
105	158	#ifndef __ASSEMBLY__
106	159	static inline int cpu_is_k2hk(void)
107	160	{
...	...	@@ -109,6 +162,14 @@
109	162	unsigned int part_no = (jtag_id >> 12) & 0xffff;
110	163
111	164	return (part_no == 0xb981) ? 1 : 0;
	165	+}
	166	+
	167	+static inline int cpu_is_k2e(void)
	168	+{
	169	+ unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
	170	+ unsigned int part_no = (jtag_id >> 12) & 0xffff;
	171	+
	172	+ return (part_no == 0xb9a6) ? 1 : 0;
112	173	}
113	174
114	175	static inline int cpu_revision(void)