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Commit 5cec5a30f01392d0cc4827e09540170951685ba4

Authored by Lokesh Vutla
1 parent c74bed1b2f
Exists in v2015.07-smarct4x and in 3 other branches ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc

ARM: DRA72-evm: Add mux data 

All the mux configurations needs to be done as part of the IODelay
sequence to avoid glitch.
Adding all the mux configuration for DRA72-evm.
MANUAL/VIRTUAL mode settings will be added once the data is available.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Showing 2 changed files with 164 additions and 143 deletions Side-by-side Diff

board/ti/dra7xx/evm.c
Diff comments   View file @ 5cec5a3
... ... @@ -86,8 +86,8 @@
86 86 void recalibrate_iodelay(void)
87 87 {
88 88 if (is_dra72x()) {
89   - __recalibrate_iodelay(core_padconf_array_essential,
90   - ARRAY_SIZE(core_padconf_array_essential),
  89 + __recalibrate_iodelay(dra72x_core_padconf_array,
  90 + ARRAY_SIZE(dra72x_core_padconf_array),
91 91 iodelay_cfg_array,
92 92 ARRAY_SIZE(iodelay_cfg_array));
93 93 } else {
board/ti/dra7xx/mux_data.h
Diff comments   View file @ 5cec5a3
... ... @@ -12,134 +12,168 @@
12 12  
13 13 #include <asm/arch/mux_dra7xx.h>
14 14  
15   -const struct pad_conf_entry core_padconf_array_essential[] = {
16   - {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
17   - {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
18   - {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
19   - {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
20   - {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
21   - {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
22   - {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
23   - {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
24   -#if defined(CONFIG_NOR)
25   - /* NOR only pin-mux */
26   - {GPMC_A0 , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */
27   - {GPMC_A1 , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */
28   - {GPMC_A2 , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */
29   - {GPMC_A3 , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */
30   - {GPMC_A4 , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */
31   - {GPMC_A5 , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */
32   - {GPMC_A6 , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */
33   - {GPMC_A7 , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */
34   - {GPMC_A8 , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */
35   - {GPMC_A9 , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */
36   - {GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */
37   - {GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */
38   - {GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */
39   - {GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */
40   - {GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */
41   - {GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */
42   - {GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */
43   - {GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */
44   - {GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */
45   - {GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */
46   - {GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */
47   - {GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */
48   - {GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */
49   - {GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */
50   - {GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */
51   - {GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */
52   - {GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */
53   -#else
54   - /* eMMC pinmux */
55   - {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
56   - {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
57   - {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
58   - {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
59   - {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
60   - {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
61   - {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
62   - {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
63   - {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
64   - {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
65   -#endif
66   -#if (CONFIG_CONS_INDEX == 1)
67   - {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
68   - {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
69   - {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */
70   - {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
71   -#elif (CONFIG_CONS_INDEX == 3)
72   - {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
73   - {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
74   -#endif
75   - {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
76   - {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
77   - {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
78   - {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
79   - {RGMII0_TXC, (PIN_OUTPUT | MANUAL_MODE | M0) },
80   - {RGMII0_TXCTL, (PIN_OUTPUT | MANUAL_MODE | M0) },
81   - {RGMII0_TXD3, (PIN_OUTPUT | MANUAL_MODE | M0) },
82   - {RGMII0_TXD2, (PIN_OUTPUT | MANUAL_MODE | M0) },
83   - {RGMII0_TXD1, (PIN_OUTPUT | MANUAL_MODE | M0) },
84   - {RGMII0_TXD0, (PIN_OUTPUT | MANUAL_MODE | M0) },
85   - {RGMII0_RXC, (PIN_INPUT | MANUAL_MODE | M0) },
86   - {RGMII0_RXCTL, (PIN_INPUT | MANUAL_MODE | M0) },
87   - {RGMII0_RXD3, (PIN_INPUT | MANUAL_MODE | M0) },
88   - {RGMII0_RXD2, (PIN_INPUT | MANUAL_MODE | M0) },
89   - {RGMII0_RXD1, (PIN_INPUT | MANUAL_MODE | M0) },
90   - {RGMII0_RXD0, (PIN_INPUT | MANUAL_MODE | M0) },
91   - {VIN2A_D12, (PIN_OUTPUT | MANUAL_MODE | M3) },
92   - {VIN2A_D13, (PIN_OUTPUT | MANUAL_MODE | M3) },
93   - {VIN2A_D14, (PIN_OUTPUT | MANUAL_MODE | M3) },
94   - {VIN2A_D15, (PIN_OUTPUT | MANUAL_MODE | M3) },
95   - {VIN2A_D16, (PIN_OUTPUT | MANUAL_MODE | M3) },
96   - {VIN2A_D17, (PIN_OUTPUT | MANUAL_MODE | M3) },
97   - {VIN2A_D18, (PIN_INPUT | MANUAL_MODE | M3)},
98   - {VIN2A_D19, (PIN_INPUT | MANUAL_MODE | M3)},
99   - {VIN2A_D20, (PIN_INPUT | MANUAL_MODE | M3)},
100   - {VIN2A_D21, (PIN_INPUT | MANUAL_MODE | M3)},
101   - {VIN2A_D22, (PIN_INPUT | MANUAL_MODE | M3)},
102   - {VIN2A_D23, (PIN_INPUT | MANUAL_MODE | M3)},
103   -#if defined(CONFIG_NAND) || defined(CONFIG_NOR)
104   - /* NAND / NOR pin-mux */
105   - {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */
106   - {GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */
107   - {GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */
108   - {GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */
109   - {GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */
110   - {GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */
111   - {GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */
112   - {GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */
113   - {GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */
114   - {GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */
115   - {GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */
116   - {GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */
117   - {GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */
118   - {GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */
119   - {GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */
120   - {GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */
121   - {GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */
122   - {GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */
123   - {GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */
124   - {GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */
125   - {GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */
126   - {GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */
127   - /* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
128   -#else
129   - /* QSPI pin-mux */
130   - {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
131   - {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
132   - {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
133   - {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
134   - {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
135   - {GPMC_A18, (M1)}, /* QSPI1_SCLK */
136   - {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
137   - {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
138   - {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
139   - {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
140   -#endif /* CONFIG_NAND || CONFIG_NOR */
141   - {USB2_DRVVBUS, (M0 | IEN | FSC) },
142   - {SPI1_CS1, (PEN | IDIS | M14) },
  15 +const struct pad_conf_entry dra72x_core_padconf_array[] = {
  16 + {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
  17 + {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
  18 + {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
  19 + {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
  20 + {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
  21 + {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
  22 + {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
  23 + {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
  24 + {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
  25 + {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
  26 + {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
  27 + {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
  28 + {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
  29 + {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
  30 + {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
  31 + {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
  32 + {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
  33 + {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
  34 + {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
  35 + {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
  36 + {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
  37 + {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
  38 + {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
  39 + {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
  40 + {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
  41 + {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
  42 + {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
  43 + {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */
  44 + {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.qspi1_rtclk */
  45 + {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a14.qspi1_d3 */
  46 + {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.qspi1_d2 */
  47 + {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.qspi1_d0 */
  48 + {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.qspi1_d1 */
  49 + {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a18.qspi1_sclk */
  50 + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
  51 + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
  52 + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
  53 + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
  54 + {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
  55 + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
  56 + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
  57 + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
  58 + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
  59 + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
  60 + {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.qspi1_cs0 */
  61 + {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
  62 + {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.vin2a_clk0 */
  63 + {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_hsync0.vin2a_hsync0 */
  64 + {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_vsync0.vin2a_vsync0 */
  65 + {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.vin2a_d0 */
  66 + {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.vin2a_d1 */
  67 + {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.vin2a_d2 */
  68 + {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.vin2a_d3 */
  69 + {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.vin2a_d4 */
  70 + {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.vin2a_d5 */
  71 + {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.vin2a_d6 */
  72 + {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.vin2a_d7 */
  73 + {VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.vin2a_d8 */
  74 + {VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.vin2a_d9 */
  75 + {VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.vin2a_d10 */
  76 + {VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.vin2a_d11 */
  77 + {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
  78 + {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
  79 + {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */
  80 + {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
  81 + {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
  82 + {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
  83 + {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
  84 + {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
  85 + {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
  86 + {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
  87 + {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
  88 + {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
  89 + {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
  90 + {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
  91 + {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
  92 + {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
  93 + {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
  94 + {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
  95 + {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
  96 + {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
  97 + {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
  98 + {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
  99 + {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
  100 + {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
  101 + {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
  102 + {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
  103 + {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
  104 + {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
  105 + {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
  106 + {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
  107 + {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_txc.rgmii0_txc */
  108 + {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_txctl.rgmii0_txctl */
  109 + {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_txd3.rgmii0_txd3 */
  110 + {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_txd2.rgmii0_txd2 */
  111 + {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_txd1.rgmii0_txd1 */
  112 + {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_txd0.rgmii0_txd0 */
  113 + {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxc.rgmii0_rxc */
  114 + {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxctl.rgmii0_rxctl */
  115 + {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd3.rgmii0_rxd3 */
  116 + {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd2.rgmii0_rxd2 */
  117 + {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd1.rgmii0_rxd1 */
  118 + {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd0.rgmii0_rxd0 */
  119 + {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
  120 + {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
  121 + {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
  122 + {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
  123 + {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
  124 + {XREF_CLK1, (M5 | PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */
  125 + {XREF_CLK2, (M5 | PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */
  126 + {MCASP1_AXR0, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr0.i2c5_sda */
  127 + {MCASP1_AXR1, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.i2c5_scl */
  128 + {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
  129 + {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
  130 + {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
  131 + {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
  132 + {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
  133 + {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
  134 + {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.mcasp7_axr0 */
  135 + {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
  136 + {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.mcasp7_aclkx */
  137 + {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.mcasp7_fsx */
  138 + {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
  139 + {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
  140 + {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
  141 + {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
  142 + {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr1.mcasp3_axr1 */
  143 + {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
  144 + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
  145 + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
  146 + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
  147 + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
  148 + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
  149 + {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */
  150 + {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
  151 + {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
  152 + {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
  153 + {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
  154 + {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
  155 + {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
  156 + {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
  157 + {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
  158 + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
  159 + {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
  160 + {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
  161 + {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
  162 + {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
  163 + {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
  164 + {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
  165 + {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
  166 + {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
  167 + {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
  168 + {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
  169 + {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */
  170 + {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
  171 + {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
  172 + {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
  173 + {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
  174 + {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
  175 + {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
  176 + {WAKEUP3, (M1 | PIN_INPUT_PULLUP)}, /* Wakeup3.sys_nirq1 */
143 177 };
144 178  
145 179 const struct pad_conf_entry early_padconf[] = {
... ... @@ -168,19 +202,6 @@
168 202 {0x764, 1740, 240}, /* RGMMI0_TXD1_OUT */
169 203 {0x770, 1680, 380}, /* RGMMI0_TXD2_OUT */
170 204 {0x77C, 1740, 440}, /* RGMMI0_TXD3_OUT */
171   - /* These values are for using RGMII1 configuration on VIN2a_x pins. */
172   - {0xAB0, 596, 0}, /* CFG_VIN2A_D18_IN */
173   - {0xABC, 314, 980}, /* CFG_VIN2A_D19_IN */
174   - {0xAD4, 241, 1536}, /* CFG_VIN2A_D20_IN */
175   - {0xAE0, 103, 1689}, /* CFG_VIN2A_D21_IN */
176   - {0xAEC, 161, 1563}, /* CFG_VIN2A_D22_IN */
177   - {0xAF8, 0, 1613}, /* CFG_VIN2A_D23_IN */
178   - {0xA70, 0, 200}, /* CFG_VIN2A_D12_OUT */
179   - {0xA7C, 1560, 140}, /* CFG_VIN2A_D13_OUT */
180   - {0xA88, 1700, 0}, /* CFG_VIN2A_D14_OUT */
181   - {0xA94, 1260, 0}, /* CFG_VIN2A_D15_OUT */
182   - {0xAA0, 1400, 0}, /* CFG_VIN2A_D16_OUT */
183   - {0xAAC, 1290, 0}, /* CFG_VIN2A_D17_OUT */
184 205 };
185 206 #endif
186 207