Commit 5d41deb939b2b190d9ba071f9674984cb0924f61
Committed by
Lokesh Vutla
Lokesh Vutla
1 parent
5edb75ad45
Exists in
v2015.07-smarct4x
and in
3 other branches
ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2
Enabled clocks for the second dwc3 controller and second USB PHY present in DRA7. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Showing 4 changed files with 23 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/omap5/hw_data.c
| ... | ... | @@ -463,7 +463,10 @@ |
| 463 | 463 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) |
| 464 | 464 | (*prcm)->cm_l3init_ocp2scp1_clkctrl, |
| 465 | 465 | (*prcm)->cm_l3init_usb_otg_ss1_clkctrl, |
| 466 | +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) | |
| 467 | + (*prcm)->cm_l3init_usb_otg_ss2_clkctrl, | |
| 466 | 468 | #endif |
| 469 | +#endif | |
| 467 | 470 | 0 |
| 468 | 471 | }; |
| 469 | 472 | |
| ... | ... | @@ -503,6 +506,19 @@ |
| 503 | 506 | /* Enable 32 KHz clock for dwc3 */ |
| 504 | 507 | setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, |
| 505 | 508 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); |
| 509 | +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) | |
| 510 | + /* Enable 960 MHz clock for dwc3 */ | |
| 511 | + setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, | |
| 512 | + OPTFCLKEN_REFCLK960M); | |
| 513 | + | |
| 514 | + /* Enable 32 KHz clock for dwc3 */ | |
| 515 | + setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, | |
| 516 | + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); | |
| 517 | + | |
| 518 | + /* Enable 60 MHz clock for USB2PHY2 */ | |
| 519 | + setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, | |
| 520 | + L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); | |
| 521 | +#endif | |
| 506 | 522 | #endif |
| 507 | 523 | |
| 508 | 524 | /* Set the correct clock dividers for mmc */ |
arch/arm/cpu/armv7/omap5/prcm-regs.c
| ... | ... | @@ -809,6 +809,7 @@ |
| 809 | 809 | .cm_clkmode_dpll_gmac = 0x4a0052a8, |
| 810 | 810 | .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, |
| 811 | 811 | .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, |
| 812 | + .cm_coreaon_l3init_60m_gfclk_clkctrl = 0x4a0086c0, | |
| 812 | 813 | |
| 813 | 814 | /* cm1.mpu */ |
| 814 | 815 | .cm_mpu_mpu_clkctrl = 0x4a005320, |
| ... | ... | @@ -919,6 +920,7 @@ |
| 919 | 920 | .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, |
| 920 | 921 | .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, |
| 921 | 922 | .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0093f0, |
| 923 | + .cm_l3init_usb_otg_ss2_clkctrl = 0x4a009340, | |
| 922 | 924 | |
| 923 | 925 | /* cm2.l4per */ |
| 924 | 926 | .cm_l4per_clkstctrl = 0x4a009700, |
arch/arm/include/asm/arch-omap5/clock.h
| ... | ... | @@ -172,6 +172,9 @@ |
| 172 | 172 | /* CM_COREAON_USB_PHY_CORE_CLKCTRL */ |
| 173 | 173 | #define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) |
| 174 | 174 | |
| 175 | +/* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */ | |
| 176 | +#define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK (1 << 8) | |
| 177 | + | |
| 175 | 178 | /* CM_L3INIT_USB_OTG_SS_CLKCTRL */ |
| 176 | 179 | #define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0) |
| 177 | 180 | #define OPTFCLKEN_REFCLK960M (1 << 8) |
arch/arm/include/asm/omap_common.h
| ... | ... | @@ -145,6 +145,7 @@ |
| 145 | 145 | u32 cm_ssc_modfreqdiv_dpll_unipro; |
| 146 | 146 | u32 cm_coreaon_usb_phy1_core_clkctrl; |
| 147 | 147 | u32 cm_coreaon_usb_phy2_core_clkctrl; |
| 148 | + u32 cm_coreaon_l3init_60m_gfclk_clkctrl; | |
| 148 | 149 | |
| 149 | 150 | /* cm2.core */ |
| 150 | 151 | u32 cm_coreaon_bandgap_clkctrl; |
| ... | ... | @@ -231,6 +232,7 @@ |
| 231 | 232 | u32 cm_l3init_ocp2scp1_clkctrl; |
| 232 | 233 | u32 cm_l3init_ocp2scp3_clkctrl; |
| 233 | 234 | u32 cm_l3init_usb_otg_ss1_clkctrl; |
| 235 | + u32 cm_l3init_usb_otg_ss2_clkctrl; | |
| 234 | 236 | |
| 235 | 237 | u32 prm_irqstatus_mpu_2; |
| 236 | 238 |