spi: spi-mxc: implement clk control for ECSPI to fix SPI_MODE_3

SPI_MODE_3 requires clk high when inactive. The SCLK_CTL field of the config reg was not configured in case of CPOL. Fix configuration so that SPI_MODE_3 which uses CPOL configures the clk line to be high in inactive state. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

spi: spi-mxc: implement clk control for ECSPI to fix SPI_MODE_3
SPI_MODE_3 requires clk high when inactive. The SCLK_CTL field of the config reg was not configured in case of CPOL. Fix configuration so that SPI_MODE_3 which uses CPOL configures the clk line to be high in inactive state. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Markus Niebel · Jagannadha Sutradharudu Teki
1 parent d7cbcc762e
Showing 1 changed file with 7 additions and 2 deletions Side-by-side Diff
drivers/spi/mxc_spi.c
@@ -115,7 +115,8 @@
 {
 	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
 	s32 reg_ctrl, reg_config;
-	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, pre_div = 0, post_div = 0;
+	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
+	u32 pre_div = 0, post_div = 0;
 	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
  
 	if (max_hz == 0) {
  
@@ -164,8 +165,10 @@
 	if (mode & SPI_CS_HIGH)
 		ss_pol = 1;
  
-	if (mode & SPI_CPOL)
+	if (mode & SPI_CPOL) {
 		sclkpol = 1;
+		sclkctl = 1;
+	}
  
 	if (mode & SPI_CPHA)
 		sclkpha = 1;
@@ -180,6 +183,8 @@
 		(ss_pol << (cs + MXC_CSPICON_SSPOL));
 	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
 		(sclkpol << (cs + MXC_CSPICON_POL));
+	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
+		(sclkctl << (cs + MXC_CSPICON_CTL));
 	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
 		(sclkpha << (cs + MXC_CSPICON_PHA));
...	...	@@ -115,7 +115,8 @@
115	115	{
116	116	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
117	117	s32 reg_ctrl, reg_config;
118		- u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, pre_div = 0, post_div = 0;
	118	+ u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
	119	+ u32 pre_div = 0, post_div = 0;
119	120	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
120	121
121	122	if (max_hz == 0) {
122	123
...	...	@@ -164,8 +165,10 @@
164	165	if (mode & SPI_CS_HIGH)
165	166	ss_pol = 1;
166	167
167		- if (mode & SPI_CPOL)
	168	+ if (mode & SPI_CPOL) {
168	169	sclkpol = 1;
	170	+ sclkctl = 1;
	171	+ }
169	172
170	173	if (mode & SPI_CPHA)
171	174	sclkpha = 1;
...	...	@@ -180,6 +183,8 @@
180	183	(ss_pol << (cs + MXC_CSPICON_SSPOL));
181	184	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) \|
182	185	(sclkpol << (cs + MXC_CSPICON_POL));
	186	+ reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) \|
	187	+ (sclkctl << (cs + MXC_CSPICON_CTL));
183	188	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) \|
184	189	(sclkpha << (cs + MXC_CSPICON_PHA));
185	190