powerpc: p1022ds: add TPL for p1022ds nand boot

TPL is introduced in the patch "NAND: TPL : introduce the TPL based on the SPL", here enable TPL for p1022ds nand boot. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>

powerpc: p1022ds: add TPL for p1022ds nand boot
TPL is introduced in the patch "NAND: TPL : introduce the TPL based on the SPL", here enable TPL for p1022ds nand boot. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
Ying Zhang · York Sun
1 parent 3aa29de0b0
Showing 5 changed files with 103 additions and 71 deletions Side-by-side Diff
board/freescale/p1022ds/spl.c
board/freescale/p1022ds/spl_minimal.c
drivers/mtd/nand/Makefile
drivers/mtd/nand/fsl_elbc_spl.c
include/configs/P1022DS.h
@@ -100,22 +100,38 @@
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+#ifndef CONFIG_SPL_NAND_BOOT
 	env_init();
+#endif
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_initialize(bd);
 #endif
 	/* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+#else
 	env_relocate();
+#endif
  
 	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  
 	gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("Tertiary program loader running in sram...");
+#else
 	puts("Second program loader running in sram...\n");
+#endif
  
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
 #elif defined(CONFIG_SPL_SPI_BOOT)
 	spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
 #endif
 }
@@ -12,51 +12,6 @@
 #include <asm/fsl_ddr_sdram.h>
  
  
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-void sdram_init(void)
-{
-	volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
-
-	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
-	__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
-#endif
-	__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
-
-	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
-	__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
-	__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
-
-	__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
-	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
-
-	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
-	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-	__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
-
-	/* Set, but do not enable the memory */
-	__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN,
-			&ddr->sdram_cfg);
-
-	in_be32(&ddr->sdram_cfg);
-	udelay(500);
-
-	/* Let the controller go */
-	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-	in_be32(&ddr->sdram_cfg);
-
-	set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
-}
-
 const static u32 sysclk_tbl[] = {
 	66666000, 7499900, 83332500, 8999900,
 	99999000, 11111000, 12499800, 13333200
@@ -68,6 +23,10 @@
 	u32 plat_ratio, sys_clk, bus_clk;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
 	/* for FPGA */
 	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
@@ -83,9 +42,6 @@
  
 	puts("\nNAND boot... ");
  
-	/* Initialize the DDR3 */
-	sdram_init();
-
 	/* copy code to RAM and jump to it - this should not return */
 	/* NOTE - code has to be copied out of NAND buffer before
 	 * other blocks can be read.
@@ -96,6 +52,7 @@
  
 void board_init_r(gd_t *gd, ulong dest_addr)
 {
+	puts("\nSecond program loader running in sram...");
 	nand_boot();
 }
  
@@ -23,6 +23,7 @@
 COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
 COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
 COBJS-$(CONFIG_SPL_NAND_BASE) += nand_base.o
+COBJS-$(CONFIG_SPL_NAND_INIT) += nand.o
  
 else # not spl
  
@@ -34,7 +34,11 @@
 	}
 }
  
+#ifdef CONFIG_TPL_BUILD
+int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
+#else
 static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
+#endif
 {
 	fsl_lbc_t *regs = LBC_BASE_ADDR;
 	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
@@ -114,6 +118,15 @@
 }
  
 /*
+ * Defines a static function nand_load_image() here, because non-static makes
+ * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
+ */
+#ifndef CONFIG_TPL_BUILD
+#define nand_spl_load_image(offs, uboot_size, vdst) \
+	nand_load_image(offs, uboot_size, vdst)
+#endif
+
+/*
  * The main entry for NAND booting. It's necessary that SDRAM is already
  * configured and available since this code loads the main U-Boot image
  * from NAND into SDRAM and starts it from there.
  
  
@@ -124,17 +137,17 @@
 	/*
 	 * Load U-Boot image from NAND into RAM
 	 */
-	nand_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-			CONFIG_SYS_NAND_U_BOOT_SIZE,
-			(void *)CONFIG_SYS_NAND_U_BOOT_DST);
+	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+			    CONFIG_SYS_NAND_U_BOOT_SIZE,
+			    (void *)CONFIG_SYS_NAND_U_BOOT_DST);
  
 #ifdef CONFIG_NAND_ENV_DST
-	nand_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			(void *)CONFIG_NAND_ENV_DST);
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (void *)CONFIG_NAND_ENV_DST);
  
 #ifdef CONFIG_ENV_OFFSET_REDUND
-	nand_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
-			(void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+	nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+			    (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
 #endif
 #endif
  
@@ -78,23 +78,44 @@
  
 #ifdef CONFIG_NAND
 #define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-
-#define CONFIG_SYS_TEXT_BASE           0x00201000
-#define CONFIG_SPL_TEXT_BASE           0xfffff000
-#define CONFIG_SPL_MAX_SIZE            4096
-#define CONFIG_SPL_RELOC_TEXT_BASE     0x00100000
-#define CONFIG_SPL_RELOC_STACK         0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE    ((512 << 10) + CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_DST     (0x00200000 - CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START   0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS    0
-#define CONFIG_SYS_LDSCRIPT            "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_TEXT_BASE		0xff800000
+#define CONFIG_SPL_MAX_SIZE		4096
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
 #endif
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_TPL_PAD_TO		0x20000
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
  
 /* High Level Configuration Options */
 #define CONFIG_BOOKE			/* BOOKE */
  
@@ -267,11 +288,11 @@
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
  
-#define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND			1
-#define CONFIG_SYS_NAND_BLOCK_SIZE    (256 * 1024)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * 1024)
 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
  
 /* NAND flash config */
  
@@ -348,8 +369,27 @@
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(96 << 10)
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 #endif
 #endif
+#endif
  
 /*
  * Serial Port
  
@@ -596,9 +636,14 @@
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_SYS_MMC_ENV_DEV	0
 #elif defined(CONFIG_NAND)
-#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	(1024 * 1024)
 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
 #elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
...	...	@@ -100,22 +100,38 @@
100	100	get_clocks();
101	101	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
102	102	CONFIG_SPL_RELOC_MALLOC_SIZE);
	103	+#ifndef CONFIG_SPL_NAND_BOOT
103	104	env_init();
	105	+#endif
104	106	#ifdef CONFIG_SPL_MMC_BOOT
105	107	mmc_initialize(bd);
106	108	#endif
107	109	/* relocate environment function pointers etc. */
	110	+#ifdef CONFIG_SPL_NAND_BOOT
	111	+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	112	+ (uchar *)CONFIG_ENV_ADDR);
	113	+
	114	+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
	115	+ gd->env_valid = 1;
	116	+#else
108	117	env_relocate();
	118	+#endif
109	119
110	120	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
111	121
112	122	gd->ram_size = initdram(0);
	123	+#ifdef CONFIG_SPL_NAND_BOOT
	124	+ puts("Tertiary program loader running in sram...");
	125	+#else
113	126	puts("Second program loader running in sram...\n");
	127	+#endif
114	128
115	129	#ifdef CONFIG_SPL_MMC_BOOT
116	130	mmc_boot();
117	131	#elif defined(CONFIG_SPL_SPI_BOOT)
118	132	spi_boot();
	133	+#elif defined(CONFIG_SPL_NAND_BOOT)
	134	+ nand_boot();
119	135	#endif
120	136	}
...	...	@@ -12,51 +12,6 @@
12	12	#include <asm/fsl_ddr_sdram.h>
13	13
14	14
15		-/*
16		- * Fixed sdram init -- doesn't use serial presence detect.
17		- */
18		-void sdram_init(void)
19		-{
20		- volatile ccsr_ddr_t ddr = (ccsr_ddr_t )CONFIG_SYS_MPC8xxx_DDR_ADDR;
21		-
22		- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
23		- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
24		-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
25		- __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
26		- __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
27		-#endif
28		- __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
29		- __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
30		- __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
31		- __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
32		-
33		- __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
34		- __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
35		- __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
36		-
37		- __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
38		- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
39		- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
40		-
41		- __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
42		- __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
43		- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
44		- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
45		-
46		- /* Set, but do not enable the memory */
47		- __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN,
48		- &ddr->sdram_cfg);
49		-
50		- in_be32(&ddr->sdram_cfg);
51		- udelay(500);
52		-
53		- /* Let the controller go */
54		- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) \| SDRAM_CFG_MEM_EN);
55		- in_be32(&ddr->sdram_cfg);
56		-
57		- set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
58		-}
59		-
60	15	const static u32 sysclk_tbl[] = {
61	16	66666000, 7499900, 83332500, 8999900,
62	17	99999000, 11111000, 12499800, 13333200
...	...	@@ -68,6 +23,10 @@
68	23	u32 plat_ratio, sys_clk, bus_clk;
69	24	ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
70	25
	26	+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
	27	+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
	28	+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
	29	+#endif
71	30	/* for FPGA */
72	31	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
73	32	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
...	...	@@ -83,9 +42,6 @@
83	42
84	43	puts("\nNAND boot... ");
85	44
86		- /* Initialize the DDR3 */
87		- sdram_init();
88		-
89	45	/* copy code to RAM and jump to it - this should not return */
90	46	/* NOTE - code has to be copied out of NAND buffer before
91	47	* other blocks can be read.
...	...	@@ -96,6 +52,7 @@
96	52
97	53	void board_init_r(gd_t *gd, ulong dest_addr)
98	54	{
	55	+ puts("\nSecond program loader running in sram...");
99	56	nand_boot();
100	57	}
101	58
...	...	@@ -23,6 +23,7 @@
23	23	COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
24	24	COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
25	25	COBJS-$(CONFIG_SPL_NAND_BASE) += nand_base.o
	26	+COBJS-$(CONFIG_SPL_NAND_INIT) += nand.o
26	27
27	28	else # not spl
28	29
...	...	@@ -34,7 +34,11 @@
34	34	}
35	35	}
36	36
	37	+#ifdef CONFIG_TPL_BUILD
	38	+int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
	39	+#else
37	40	static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
	41	+#endif
38	42	{
39	43	fsl_lbc_t *regs = LBC_BASE_ADDR;
40	44	uchar buf = (uchar )CONFIG_SYS_NAND_BASE;
...	...	@@ -114,6 +118,15 @@
114	118	}
115	119
116	120	/*
	121	+ * Defines a static function nand_load_image() here, because non-static makes
	122	+ * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
	123	+ */
	124	+#ifndef CONFIG_TPL_BUILD
	125	+#define nand_spl_load_image(offs, uboot_size, vdst) \
	126	+ nand_load_image(offs, uboot_size, vdst)
	127	+#endif
	128	+
	129	+/*
117	130	* The main entry for NAND booting. It's necessary that SDRAM is already
118	131	* configured and available since this code loads the main U-Boot image
119	132	* from NAND into SDRAM and starts it from there.
120	133
121	134
...	...	@@ -124,17 +137,17 @@
124	137	/*
125	138	* Load U-Boot image from NAND into RAM
126	139	*/
127		- nand_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
128		- CONFIG_SYS_NAND_U_BOOT_SIZE,
129		- (void *)CONFIG_SYS_NAND_U_BOOT_DST);
	140	+ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
	141	+ CONFIG_SYS_NAND_U_BOOT_SIZE,
	142	+ (void *)CONFIG_SYS_NAND_U_BOOT_DST);
130	143
131	144	#ifdef CONFIG_NAND_ENV_DST
132		- nand_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
133		- (void *)CONFIG_NAND_ENV_DST);
	145	+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	146	+ (void *)CONFIG_NAND_ENV_DST);
134	147
135	148	#ifdef CONFIG_ENV_OFFSET_REDUND
136		- nand_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
137		- (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
	149	+ nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
	150	+ (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
138	151	#endif
139	152	#endif
140	153
...	...	@@ -78,23 +78,44 @@
78	78
79	79	#ifdef CONFIG_NAND
80	80	#define CONFIG_SPL
	81	+#define CONFIG_TPL
	82	+#ifdef CONFIG_TPL_BUILD
	83	+#define CONFIG_SPL_NAND_BOOT
	84	+#define CONFIG_SPL_FLUSH_IMAGE
	85	+#define CONFIG_SPL_ENV_SUPPORT
	86	+#define CONFIG_SPL_NAND_INIT
	87	+#define CONFIG_SPL_SERIAL_SUPPORT
	88	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	89	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	90	+#define CONFIG_SPL_I2C_SUPPORT
	91	+#define CONFIG_SPL_NAND_SUPPORT
	92	+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	93	+#define CONFIG_SPL_COMMON_INIT_DDR
	94	+#define CONFIG_SPL_MAX_SIZE (128 << 10)
	95	+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
	96	+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	97	+#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
	98	+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
	99	+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
	100	+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
	101	+#elif defined(CONFIG_SPL_BUILD)
81	102	#define CONFIG_SPL_INIT_MINIMAL
82	103	#define CONFIG_SPL_SERIAL_SUPPORT
83	104	#define CONFIG_SPL_NAND_SUPPORT
84	105	#define CONFIG_SPL_FLUSH_IMAGE
85		-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
86		-
87		-#define CONFIG_SYS_TEXT_BASE 0x00201000
88		-#define CONFIG_SPL_TEXT_BASE 0xfffff000
89		-#define CONFIG_SPL_MAX_SIZE 4096
90		-#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
91		-#define CONFIG_SPL_RELOC_STACK 0x00100000
92		-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE)
93		-#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
94		-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
95		-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
96		-#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
	106	+#define CONFIG_SPL_TEXT_BASE 0xff800000
	107	+#define CONFIG_SPL_MAX_SIZE 4096
	108	+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
	109	+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
	110	+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
	111	+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
97	112	#endif
	113	+#define CONFIG_SPL_PAD_TO 0x20000
	114	+#define CONFIG_TPL_PAD_TO 0x20000
	115	+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	116	+#define CONFIG_SYS_TEXT_BASE 0x11001000
	117	+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
	118	+#endif
98	119
99	120	/* High Level Configuration Options */
100	121	#define CONFIG_BOOKE /* BOOKE */
101	122
...	...	@@ -267,11 +288,11 @@
267	288	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
268	289	#endif
269	290
270		-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
	291	+#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
271	292	#define CONFIG_SYS_MAX_NAND_DEVICE 1
272	293	#define CONFIG_MTD_NAND_VERIFY_WRITE
273	294	#define CONFIG_CMD_NAND 1
274		-#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
	295	+#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
275	296	#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
276	297
277	298	/* NAND flash config */
278	299
...	...	@@ -348,8 +369,27 @@
348	369	#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
349	370	#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
350	371	#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
	372	+#elif defined(CONFIG_NAND)
	373	+#ifdef CONFIG_TPL_BUILD
	374	+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
	375	+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	376	+#define CONFIG_SYS_L2_SIZE (256 << 10)
	377	+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	378	+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
	379	+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
	380	+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
	381	+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
	382	+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
	383	+#else
	384	+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
	385	+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	386	+#define CONFIG_SYS_L2_SIZE (256 << 10)
	387	+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	388	+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
	389	+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
351	390	#endif
352	391	#endif
	392	+#endif
353	393
354	394	/*
355	395	* Serial Port
356	396
...	...	@@ -596,9 +636,14 @@
596	636	#define CONFIG_ENV_SIZE 0x2000
597	637	#define CONFIG_SYS_MMC_ENV_DEV 0
598	638	#elif defined(CONFIG_NAND)
599		-#define CONFIG_ENV_IS_IN_NAND
	639	+#ifdef CONFIG_TPL_BUILD
	640	+#define CONFIG_ENV_SIZE 0x2000
	641	+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
	642	+#else
600	643	#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
601		-#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
	644	+#endif
	645	+#define CONFIG_ENV_IS_IN_NAND
	646	+#define CONFIG_ENV_OFFSET (1024 * 1024)
602	647	#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
603	648	#elif defined(CONFIG_SYS_RAMBOOT)
604	649	#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */