boards: ls1088a: Add support of I2C driver model

DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C API when DM_I2C is used.When DM_I2C_COMPAT is not enabled for compilation, a compilation error will be generated. This patch solves the problem that the i2c-related api of the ls1088a platform does not support dm. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

boards: ls1088a: Add support of I2C driver model
DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C API when DM_I2C is used.When DM_I2C_COMPAT is not enabled for compilation, a compilation error will be generated. This patch solves the problem that the i2c-related api of the ls1088a platform does not support dm. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Chuanhua Han · Prabhakar Kushwaha
1 parent 292370df1c
Showing 3 changed files with 151 additions and 2 deletions Side-by-side Diff
board/freescale/ls1088a/ls1088a.c
include/configs/ls1088a_common.h
include/configs/ls1088ardb.h
@@ -374,7 +374,15 @@
 {
 	int ret;
  
+#ifndef CONFIG_DM_I2C
 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
 	if (ret) {
 		puts("PCA: failed to select proper channel\n");
 		return ret;
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
@@ -393,38 +401,89 @@
  
 	/* Access to Control/Shared register */
 	reg = 0x0;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
+#else
+	struct udevice *dev;
  
+	i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
+	dm_i2c_write(dev, 0xff, &reg, 1);
+#endif
+
 	/* Read device revision and ID */
+#ifndef CONFIG_DM_I2C
 	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 1, &reg, 1);
+#endif
 	debug("Retimer version id = 0x%x\n", reg);
  
 	/* Enable Broadcast. All writes target all channel register sets */
 	reg = 0x0c;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0xff, &reg, 1);
+#endif
  
 	/* Reset Channel Registers */
+#ifndef CONFIG_DM_I2C
 	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 0, &reg, 1);
+#endif
 	reg |= 0x4;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0, &reg, 1);
+#endif
  
 	/* Set data rate as 10.3125 Gbps */
 	reg = 0x90;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x60, &reg, 1);
+#endif
 	reg = 0xb3;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x61, &reg, 1);
+#endif
 	reg = 0x90;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x62, &reg, 1);
+#endif
 	reg = 0xb3;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x63, &reg, 1);
+#endif
 	reg = 0xcd;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x64, &reg, 1);
+#endif
  
 	/* Select VCO Divider to full rate (000) */
+#ifndef CONFIG_DM_I2C
 	i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 0x2F, &reg, 1);
+#endif
 	reg &= 0x0f;
 	reg |= 0x70;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x2F, &reg, 1);
+#endif
  
 #ifdef	CONFIG_TARGET_LS1088AQDS
 	/* Retimer is connected to I2C1_CH5 */
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
@@ -432,39 +491,89 @@
  
 	/* Access to Control/Shared register */
 	reg = 0x0;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
+#else
+	i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
+	dm_i2c_write(dev, 0xff, &reg, 1);
+#endif
  
 	/* Read device revision and ID */
+#ifndef CONFIG_DM_I2C
 	i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 1, &reg, 1);
+#endif
 	debug("Retimer version id = 0x%x\n", reg);
  
 	/* Enable Broadcast. All writes target all channel register sets */
 	reg = 0x0c;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0xff, &reg, 1);
+#endif
  
 	/* Reset Channel Registers */
+#ifndef CONFIG_DM_I2C
 	i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 0, &reg, 1);
+#endif
 	reg |= 0x4;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0, &reg, 1);
+#endif
  
 	/* Set data rate as 10.3125 Gbps */
 	reg = 0x90;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x60, &reg, 1);
+#endif
 	reg = 0xb3;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x61, &reg, 1);
+#endif
 	reg = 0x90;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x62, &reg, 1);
+#endif
 	reg = 0xb3;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x63, &reg, 1);
+#endif
 	reg = 0xcd;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x64, &reg, 1);
+#endif
  
 	/* Select VCO Divider to full rate (000) */
+#ifndef CONFIG_DM_I2C
 	i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 0x2F, &reg, 1);
+#endif
 	reg &= 0x0f;
 	reg |= 0x70;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x2F, &reg, 1);
 #endif
+
+#endif
 	/*return the default channel*/
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 }
  
  
  
@@ -500,16 +609,30 @@
 	u8 chan = PWM_CHANNEL0;
  
 	/* Select the PAGE 0 using PMBus commands PAGE for VDD */
+#ifndef CONFIG_DM_I2C
 	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 			PMBUS_CMD_PAGE, 1, &chan, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
+				   &chan, 1);
+#endif
+
 	if (ret) {
 		printf("VID: failed to select VDD Page 0\n");
 		return ret;
 	}
  
 	/* Read the output voltage using PMBus command READ_VOUT */
+#ifndef CONFIG_DM_I2C
 	ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
 		       PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
+#else
+	dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
+#endif
 	if (ret) {
 		printf("VID: failed to read the volatge\n");
 		return ret;
  
@@ -525,8 +648,17 @@
 			svdd & 0xFF, (svdd & 0xFF00) >> 8};
  
 	/* Write the desired voltage code to the SVDD regulator */
+#ifndef CONFIG_DM_I2C
 	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 			PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
+				   (void *)&buff, 5);
+#endif
 	if (ret) {
 		printf("VID: I2C failed to write to the volatge regulator\n");
 		return -1;
  
@@ -557,8 +689,18 @@
 	printf("SVDD changing of RDB\n");
  
 	/* Read the BRDCFG54 via CLPD */
+#ifndef CONFIG_DM_I2C
 	ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
 		       QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
+				  (void *)&brdcfg4, 1);
+#endif
+
 	if (ret) {
 		printf("VID: I2C failed to read the CPLD BRDCFG4\n");
 		return -1;
  
@@ -567,8 +709,14 @@
 	brdcfg4 = brdcfg4 | 0x08;
  
 	/* Write to the BRDCFG4 */
+#ifndef CONFIG_DM_I2C
 	ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
 			QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
+#else
+	ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
+			   (void *)&brdcfg4, 1);
+#endif
+
 	if (ret) {
 		debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
 		return -1;
@@ -67,7 +67,10 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
  
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
+#endif
+
  
 /* Serial Port */
 #define CONFIG_SYS_NS16550_SERIAL
@@ -269,9 +269,7 @@
 * RTC configuration
 */
 #define RTC
-#define CONFIG_RTC_PCF8563 1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
-#define CONFIG_CMD_DATE
 #endif
  
 /* EEPROM */
...	...	@@ -374,7 +374,15 @@
374	374	{
375	375	int ret;
376	376
	377	+#ifndef CONFIG_DM_I2C
377	378	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
	379	+#else
	380	+ struct udevice *dev;
	381	+
	382	+ ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
	383	+ if (!ret)
	384	+ ret = dm_i2c_write(dev, 0, &ch, 1);
	385	+#endif
378	386	if (ret) {
379	387	puts("PCA: failed to select proper channel\n");
380	388	return ret;
381	389
382	390
383	391
384	392
385	393
386	394
387	395
388	396
389	397
390	398
391	399
392	400
393	401
394	402
395	403
396	404
397	405
398	406
399	407
400	408
401	409
402	410
403	411
404	412
...	...	@@ -393,38 +401,89 @@
393	401
394	402	/* Access to Control/Shared register */
395	403	reg = 0x0;
	404	+#ifndef CONFIG_DM_I2C
396	405	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
	406	+#else
	407	+ struct udevice *dev;
397	408
	409	+ i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
	410	+ dm_i2c_write(dev, 0xff, &reg, 1);
	411	+#endif
	412	+
398	413	/* Read device revision and ID */
	414	+#ifndef CONFIG_DM_I2C
399	415	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
	416	+#else
	417	+ dm_i2c_read(dev, 1, &reg, 1);
	418	+#endif
400	419	debug("Retimer version id = 0x%x\n", reg);
401	420
402	421	/* Enable Broadcast. All writes target all channel register sets */
403	422	reg = 0x0c;
	423	+#ifndef CONFIG_DM_I2C
404	424	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
	425	+#else
	426	+ dm_i2c_write(dev, 0xff, &reg, 1);
	427	+#endif
405	428
406	429	/* Reset Channel Registers */
	430	+#ifndef CONFIG_DM_I2C
407	431	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
	432	+#else
	433	+ dm_i2c_read(dev, 0, &reg, 1);
	434	+#endif
408	435	reg \|= 0x4;
	436	+#ifndef CONFIG_DM_I2C
409	437	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
	438	+#else
	439	+ dm_i2c_write(dev, 0, &reg, 1);
	440	+#endif
410	441
411	442	/* Set data rate as 10.3125 Gbps */
412	443	reg = 0x90;
	444	+#ifndef CONFIG_DM_I2C
413	445	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
	446	+#else
	447	+ dm_i2c_write(dev, 0x60, &reg, 1);
	448	+#endif
414	449	reg = 0xb3;
	450	+#ifndef CONFIG_DM_I2C
415	451	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
	452	+#else
	453	+ dm_i2c_write(dev, 0x61, &reg, 1);
	454	+#endif
416	455	reg = 0x90;
	456	+#ifndef CONFIG_DM_I2C
417	457	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
	458	+#else
	459	+ dm_i2c_write(dev, 0x62, &reg, 1);
	460	+#endif
418	461	reg = 0xb3;
	462	+#ifndef CONFIG_DM_I2C
419	463	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
	464	+#else
	465	+ dm_i2c_write(dev, 0x63, &reg, 1);
	466	+#endif
420	467	reg = 0xcd;
	468	+#ifndef CONFIG_DM_I2C
421	469	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
	470	+#else
	471	+ dm_i2c_write(dev, 0x64, &reg, 1);
	472	+#endif
422	473
423	474	/* Select VCO Divider to full rate (000) */
	475	+#ifndef CONFIG_DM_I2C
424	476	i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
	477	+#else
	478	+ dm_i2c_read(dev, 0x2F, &reg, 1);
	479	+#endif
425	480	reg &= 0x0f;
426	481	reg \|= 0x70;
	482	+#ifndef CONFIG_DM_I2C
427	483	i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
	484	+#else
	485	+ dm_i2c_write(dev, 0x2F, &reg, 1);
	486	+#endif
428	487
429	488	#ifdef CONFIG_TARGET_LS1088AQDS
430	489	/* Retimer is connected to I2C1_CH5 */
431	490
432	491
433	492
434	493
435	494
436	495
437	496
438	497
439	498
440	499
441	500
442	501
443	502
444	503
445	504
446	505
447	506
448	507
449	508
450	509
451	510
452	511
453	512
454	513
...	...	@@ -432,39 +491,89 @@
432	491
433	492	/* Access to Control/Shared register */
434	493	reg = 0x0;
	494	+#ifndef CONFIG_DM_I2C
435	495	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
	496	+#else
	497	+ i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
	498	+ dm_i2c_write(dev, 0xff, &reg, 1);
	499	+#endif
436	500
437	501	/* Read device revision and ID */
	502	+#ifndef CONFIG_DM_I2C
438	503	i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
	504	+#else
	505	+ dm_i2c_read(dev, 1, &reg, 1);
	506	+#endif
439	507	debug("Retimer version id = 0x%x\n", reg);
440	508
441	509	/* Enable Broadcast. All writes target all channel register sets */
442	510	reg = 0x0c;
	511	+#ifndef CONFIG_DM_I2C
443	512	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
	513	+#else
	514	+ dm_i2c_write(dev, 0xff, &reg, 1);
	515	+#endif
444	516
445	517	/* Reset Channel Registers */
	518	+#ifndef CONFIG_DM_I2C
446	519	i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
	520	+#else
	521	+ dm_i2c_read(dev, 0, &reg, 1);
	522	+#endif
447	523	reg \|= 0x4;
	524	+#ifndef CONFIG_DM_I2C
448	525	i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
	526	+#else
	527	+ dm_i2c_write(dev, 0, &reg, 1);
	528	+#endif
449	529
450	530	/* Set data rate as 10.3125 Gbps */
451	531	reg = 0x90;
	532	+#ifndef CONFIG_DM_I2C
452	533	i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
	534	+#else
	535	+ dm_i2c_write(dev, 0x60, &reg, 1);
	536	+#endif
453	537	reg = 0xb3;
	538	+#ifndef CONFIG_DM_I2C
454	539	i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
	540	+#else
	541	+ dm_i2c_write(dev, 0x61, &reg, 1);
	542	+#endif
455	543	reg = 0x90;
	544	+#ifndef CONFIG_DM_I2C
456	545	i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
	546	+#else
	547	+ dm_i2c_write(dev, 0x62, &reg, 1);
	548	+#endif
457	549	reg = 0xb3;
	550	+#ifndef CONFIG_DM_I2C
458	551	i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
	552	+#else
	553	+ dm_i2c_write(dev, 0x63, &reg, 1);
	554	+#endif
459	555	reg = 0xcd;
	556	+#ifndef CONFIG_DM_I2C
460	557	i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
	558	+#else
	559	+ dm_i2c_write(dev, 0x64, &reg, 1);
	560	+#endif
461	561
462	562	/* Select VCO Divider to full rate (000) */
	563	+#ifndef CONFIG_DM_I2C
463	564	i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
	565	+#else
	566	+ dm_i2c_read(dev, 0x2F, &reg, 1);
	567	+#endif
464	568	reg &= 0x0f;
465	569	reg \|= 0x70;
	570	+#ifndef CONFIG_DM_I2C
466	571	i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
	572	+#else
	573	+ dm_i2c_write(dev, 0x2F, &reg, 1);
467	574	#endif
	575	+
	576	+#endif
468	577	/return the default channel/
469	578	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
470	579	}
471	580
472	581
473	582
...	...	@@ -500,16 +609,30 @@
500	609	u8 chan = PWM_CHANNEL0;
501	610
502	611	/* Select the PAGE 0 using PMBus commands PAGE for VDD */
	612	+#ifndef CONFIG_DM_I2C
503	613	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
504	614	PMBUS_CMD_PAGE, 1, &chan, 1);
	615	+#else
	616	+ struct udevice *dev;
	617	+
	618	+ ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
	619	+ if (!ret)
	620	+ ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
	621	+ &chan, 1);
	622	+#endif
	623	+
505	624	if (ret) {
506	625	printf("VID: failed to select VDD Page 0\n");
507	626	return ret;
508	627	}
509	628
510	629	/* Read the output voltage using PMBus command READ_VOUT */
	630	+#ifndef CONFIG_DM_I2C
511	631	ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
512	632	PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
	633	+#else
	634	+ dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
	635	+#endif
513	636	if (ret) {
514	637	printf("VID: failed to read the volatge\n");
515	638	return ret;
516	639
...	...	@@ -525,8 +648,17 @@
525	648	svdd & 0xFF, (svdd & 0xFF00) >> 8};
526	649
527	650	/* Write the desired voltage code to the SVDD regulator */
	651	+#ifndef CONFIG_DM_I2C
528	652	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
529	653	PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
	654	+#else
	655	+ struct udevice *dev;
	656	+
	657	+ ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
	658	+ if (!ret)
	659	+ ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
	660	+ (void *)&buff, 5);
	661	+#endif
530	662	if (ret) {
531	663	printf("VID: I2C failed to write to the volatge regulator\n");
532	664	return -1;
533	665
...	...	@@ -557,8 +689,18 @@
557	689	printf("SVDD changing of RDB\n");
558	690
559	691	/* Read the BRDCFG54 via CLPD */
	692	+#ifndef CONFIG_DM_I2C
560	693	ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
561	694	QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
	695	+#else
	696	+ struct udevice *dev;
	697	+
	698	+ ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
	699	+ if (!ret)
	700	+ ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
	701	+ (void *)&brdcfg4, 1);
	702	+#endif
	703	+
562	704	if (ret) {
563	705	printf("VID: I2C failed to read the CPLD BRDCFG4\n");
564	706	return -1;
565	707
...	...	@@ -567,8 +709,14 @@
567	709	brdcfg4 = brdcfg4 \| 0x08;
568	710
569	711	/* Write to the BRDCFG4 */
	712	+#ifndef CONFIG_DM_I2C
570	713	ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
571	714	QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
	715	+#else
	716	+ ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
	717	+ (void *)&brdcfg4, 1);
	718	+#endif
	719	+
572	720	if (ret) {
573	721	debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
574	722	return -1;
...	...	@@ -67,7 +67,10 @@
67	67	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
68	68
69	69	/* I2C */
	70	+#ifndef CONFIG_DM_I2C
70	71	#define CONFIG_SYS_I2C
	72	+#endif
	73	+
71	74
72	75	/* Serial Port */
73	76	#define CONFIG_SYS_NS16550_SERIAL
...	...	@@ -269,9 +269,7 @@
269	269	* RTC configuration
270	270	*/
271	271	#define RTC
272		-#define CONFIG_RTC_PCF8563 1
273	272	#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
274		-#define CONFIG_CMD_DATE
275	273	#endif
276	274
277	275	/* EEPROM */