Eric Lee / smarc-uboot

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Commit 5e0de0e216b8fb27634afb11c60a2fa24c23349e

Authored by Andre Schwarz
Committed by Grant Likely
1 parent 348753d416
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

mpc5xxx: Add MVBC_P board support 

The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

Showing 14 changed files with 1132 additions and 1 deletions Side-by-side Diff

... ... @@ -426,7 +426,7 @@
426 426  
427 427 N: Andre Schwarz
428 428 E: andre.schwarz@matrix-vision.de
429   -D: Support for Matrix Vision boards (MVBLM7)
  429 +D: Support for Matrix Vision boards (MVBLM7/MVBC_P)
430 430  
431 431 N: Robert Schwebel
432 432 E: r.schwebel@pengutronix.de
... ... @@ -372,6 +372,7 @@
372 372  
373 373 Andre Schwarz <andre.schwarz@matrix-vision.de>
374 374  
  375 + mvbc_p MPC5200
375 376 mvblm7 MPC8343
376 377  
377 378 Timur Tabi <timur@freescale.com>
... ... @@ -48,6 +48,7 @@
48 48 mecp5200 \
49 49 motionpro \
50 50 munices \
  51 + MVBC_P \
51 52 o2dnt \
52 53 pf5200 \
53 54 PM520 \
... ... @@ -745,6 +745,13 @@
745 745 motionpro_config: unconfig
746 746 @$(MKCONFIG) motionpro ppc mpc5xxx motionpro
747 747  
  748 +MVBC_P_config: unconfig
  749 + @mkdir -p $(obj)include
  750 + @mkdir -p $(obj)board/mvbc_p
  751 + @ >$(obj)include/config.h
  752 + @[ -z "$(findstring MVBC_P,$@)" ] || \
  753 + { echo "#define CONFIG_MVBC_P" >>$(obj)include/config.h; }
  754 + @$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p matrix_vision
748 755  
749 756 #########################################################################
750 757 ## MPC512x Systems
board/matrix_vision/mvbc_p/Makefile
Diff comments   View file @ 5e0de0e
  1 +#
  2 +# (C) Copyright 2003
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# (C) Copyright 2004-2008
  6 +# Matrix-Vision GmbH, info@matrix-vision.de
  7 +#
  8 +# See file CREDITS for list of people who contributed to this
  9 +# project.
  10 +#
  11 +# This program is free software; you can redistribute it and/or
  12 +# modify it under the terms of the GNU General Public License as
  13 +# published by the Free Software Foundation; either version 2 of
  14 +# the License, or (at your option) any later version.
  15 +#
  16 +# This program is distributed in the hope that it will be useful,
  17 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 +# GNU General Public License for more details.
  20 +#
  21 +# You should have received a copy of the GNU General Public License
  22 +# along with this program; if not, write to the Free Software
  23 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 +# MA 02111-1307 USA
  25 +#
  26 +
  27 +include $(TOPDIR)/config.mk
  28 +
  29 +LIB = $(obj)lib$(BOARD).a
  30 +
  31 +COBJS := $(BOARD).o fpga.o
  32 +
  33 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  34 +OBJS := $(addprefix $(obj),$(COBJS))
  35 +SOBJS := $(addprefix $(obj),$(SOBJS))
  36 +
  37 +$(LIB): $(obj).depend $(OBJS)
  38 + $(AR) $(ARFLAGS) $@ $(OBJS)
  39 +
  40 +clean:
  41 + rm -f $(SOBJS) $(OBJS)
  42 +
  43 +distclean: clean
  44 + rm -f $(LIB) core *.bak $(obj).depend
  45 +
  46 +#########################################################################
  47 +
  48 +include $(SRCTREE)/rules.mk
  49 +
  50 +sinclude $(obj).depend
board/matrix_vision/mvbc_p/config.mk
Diff comments   View file @ 5e0de0e
  1 +#
  2 +# (C) Copyright 2003
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
  25 +
  26 +ifndef TEXT_BASE
  27 +TEXT_BASE = 0xFF800000
  28 +endif
  29 +
  30 +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
board/matrix_vision/mvbc_p/fpga.c
Diff comments   View file @ 5e0de0e
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  4 + * Keith Outwater, keith_outwater@mvis.com.
  5 + *
  6 + * (C) Copyright 2008
  7 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
  8 + *
  9 + * See file CREDITS for list of people who contributed to this
  10 + * project.
  11 + *
  12 + * This program is free software; you can redistribute it and/or
  13 + * modify it under the terms of the GNU General Public License as
  14 + * published by the Free Software Foundation; either version 2 of
  15 + * the License, or (at your option) any later version.
  16 + *
  17 + * This program is distributed in the hope that it will be useful,
  18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20 + * GNU General Public License for more details.
  21 + *
  22 + * You should have received a copy of the GNU General Public License
  23 + * along with this program; if not, write to the Free Software
  24 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25 + * MA 02111-1307 USA
  26 + *
  27 + */
  28 +
  29 +#include <common.h>
  30 +#include <ACEX1K.h>
  31 +#include <command.h>
  32 +#include "fpga.h"
  33 +#include "mvbc_p.h"
  34 +
  35 +#ifdef FPGA_DEBUG
  36 +#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
  37 +#else
  38 +#define fpga_debug(fmt, args...)
  39 +#endif
  40 +
  41 +Altera_CYC2_Passive_Serial_fns altera_fns = {
  42 + fpga_null_fn,
  43 + fpga_config_fn,
  44 + fpga_status_fn,
  45 + fpga_done_fn,
  46 + fpga_wr_fn,
  47 + fpga_null_fn,
  48 + fpga_null_fn,
  49 + 0
  50 +};
  51 +
  52 +Altera_desc cyclone2 = {
  53 + Altera_CYC2,
  54 + passive_serial,
  55 + Altera_EP2C8_SIZE,
  56 + (void *) &altera_fns,
  57 + NULL,
  58 + 0
  59 +};
  60 +
  61 +DECLARE_GLOBAL_DATA_PTR;
  62 +
  63 +int mvbc_p_init_fpga(void)
  64 +{
  65 + fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n",
  66 + gd->reloc_off);
  67 + fpga_init(gd->reloc_off);
  68 + fpga_add(fpga_altera, &cyclone2);
  69 + fpga_config_fn(0, 1, 0);
  70 + udelay(60);
  71 +
  72 + return 1;
  73 +}
  74 +
  75 +int fpga_null_fn(int cookie)
  76 +{
  77 + return 0;
  78 +}
  79 +
  80 +int fpga_config_fn(int assert, int flush, int cookie)
  81 +{
  82 + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
  83 + u32 dvo = gpio->simple_dvo;
  84 +
  85 + fpga_debug("SET config : %s\n", assert ? "low" : "high");
  86 + if (assert)
  87 + dvo |= FPGA_CONFIG;
  88 + else
  89 + dvo &= ~FPGA_CONFIG;
  90 +
  91 + if (flush)
  92 + gpio->simple_dvo = dvo;
  93 +
  94 + return assert;
  95 +}
  96 +
  97 +int fpga_done_fn(int cookie)
  98 +{
  99 + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
  100 + int result = 0;
  101 +
  102 + udelay(10);
  103 + fpga_debug("CONF_DONE check ... ");
  104 + if (gpio->simple_ival & FPGA_CONF_DONE) {
  105 + fpga_debug("high\n");
  106 + result = 1;
  107 + } else
  108 + fpga_debug("low\n");
  109 +
  110 + return result;
  111 +}
  112 +
  113 +int fpga_status_fn(int cookie)
  114 +{
  115 + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
  116 + int result = 0;
  117 +
  118 + fpga_debug("STATUS check ... ");
  119 + if (gpio->sint_ival & FPGA_STATUS) {
  120 + fpga_debug("high\n");
  121 + result = 1;
  122 + } else
  123 + fpga_debug("low\n");
  124 +
  125 + return result;
  126 +}
  127 +
  128 +int fpga_clk_fn(int assert_clk, int flush, int cookie)
  129 +{
  130 + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
  131 + u32 dvo = gpio->simple_dvo;
  132 +
  133 + fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
  134 + if (assert_clk)
  135 + dvo |= FPGA_CCLK;
  136 + else
  137 + dvo &= ~FPGA_CCLK;
  138 +
  139 + if (flush)
  140 + gpio->simple_dvo = dvo;
  141 +
  142 + return assert_clk;
  143 +}
  144 +
  145 +static inline int _write_fpga(u8 val)
  146 +{
  147 + int i;
  148 + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
  149 + u32 dvo = gpio->simple_dvo;
  150 +
  151 + for (i=0; i<8; i++) {
  152 + dvo &= ~FPGA_CCLK;
  153 + gpio->simple_dvo = dvo;
  154 + dvo &= ~FPGA_DIN;
  155 + if (val & 1)
  156 + dvo |= FPGA_DIN;
  157 + gpio->simple_dvo = dvo;
  158 + dvo |= FPGA_CCLK;
  159 + gpio->simple_dvo = dvo;
  160 + val >>= 1;
  161 + }
  162 +
  163 + return 0;
  164 +}
  165 +
  166 +int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
  167 +{
  168 + unsigned char *data = (unsigned char *) buf;
  169 + int i;
  170 +
  171 + fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
  172 + for (i = 0; i < len; i++)
  173 + _write_fpga(data[i]);
  174 + fpga_debug("\n");
  175 +
  176 + return FPGA_SUCCESS;
  177 +}
board/matrix_vision/mvbc_p/fpga.h
Diff comments   View file @ 5e0de0e
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  4 + * Keith Outwater, keith_outwater@mvis.com.
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + *
  24 + */
  25 +
  26 +extern int mvbc_p_init_fpga(void);
  27 +
  28 +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
  29 +extern int fpga_status_fn(int cookie);
  30 +extern int fpga_config_fn(int assert, int flush, int cookie);
  31 +extern int fpga_done_fn(int cookie);
  32 +extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
  33 +extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
  34 +extern int fpga_null_fn(int cookie);
board/matrix_vision/mvbc_p/mvbc_p.c
Diff comments   View file @ 5e0de0e
  1 +/*
  2 + * (C) Copyright 2003
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * (C) Copyright 2004
  6 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
  7 + *
  8 + * (C) Copyright 2005-2007
  9 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
  10 + *
  11 + * See file CREDITS for list of people who contributed to this
  12 + * project.
  13 + *
  14 + * This program is free software; you can redistribute it and/or
  15 + * modify it under the terms of the GNU General Public License as
  16 + * published by the Free Software Foundation; either version 2 of
  17 + * the License, or (at your option) any later version.
  18 + *
  19 + * This program is distributed in the hope that it will be useful,
  20 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22 + * GNU General Public License for more details.
  23 + *
  24 + * You should have received a copy of the GNU General Public License
  25 + * along with this program; if not, write to the Free Software
  26 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27 + * MA 02111-1307 USA
  28 + */
  29 +
  30 +#include <common.h>
  31 +#include <mpc5xxx.h>
  32 +#include <malloc.h>
  33 +#include <pci.h>
  34 +#include <i2c.h>
  35 +#include <environment.h>
  36 +#include <fdt_support.h>
  37 +#include <asm/io.h>
  38 +#include "fpga.h"
  39 +#include "mvbc_p.h"
  40 +
  41 +#define SDRAM_MODE 0x00CD0000
  42 +#define SDRAM_CONTROL 0x504F0000
  43 +#define SDRAM_CONFIG1 0xD2322800
  44 +#define SDRAM_CONFIG2 0x8AD70000
  45 +
  46 +DECLARE_GLOBAL_DATA_PTR;
  47 +
  48 +static void sdram_start (int hi_addr)
  49 +{
  50 + long hi_bit = hi_addr ? 0x01000000 : 0;
  51 +
  52 + /* unlock mode register */
  53 + out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
  54 +
  55 + /* precharge all banks */
  56 + out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
  57 +
  58 + /* precharge all banks */
  59 + out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
  60 +
  61 + /* auto refresh */
  62 + out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
  63 +
  64 + /* set mode register */
  65 + out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
  66 +
  67 + /* normal operation */
  68 + out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
  69 +}
  70 +
  71 +phys_addr_t initdram (int board_type)
  72 +{
  73 + ulong dramsize = 0;
  74 + ulong test1,
  75 + test2;
  76 +
  77 + /* setup SDRAM chip selects */
  78 + out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
  79 +
  80 + /* setup config registers */
  81 + out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
  82 + out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
  83 +
  84 + /* find RAM size using SDRAM CS0 only */
  85 + sdram_start(0);
  86 + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
  87 + sdram_start(1);
  88 + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
  89 + if (test1 > test2) {
  90 + sdram_start(0);
  91 + dramsize = test1;
  92 + } else
  93 + dramsize = test2;
  94 +
  95 + if (dramsize < (1 << 20))
  96 + dramsize = 0;
  97 +
  98 + if (dramsize > 0)
  99 + out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
  100 + __builtin_ffs(dramsize >> 20) - 1);
  101 + else
  102 + out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
  103 +
  104 + return dramsize;
  105 +}
  106 +
  107 +void mvbc_init_gpio(void)
  108 +{
  109 + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
  110 +
  111 + printf("Ports : 0x%08x\n", gpio->port_config);
  112 + printf("PORCFG: 0x%08x\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
  113 +
  114 + out_be32(&gpio->simple_ddr, SIMPLE_DDR);
  115 + out_be32(&gpio->simple_dvo, SIMPLE_DVO);
  116 + out_be32(&gpio->simple_ode, SIMPLE_ODE);
  117 + out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
  118 +
  119 + out_be32((u32*)&gpio->sint_ode, SINT_ODE);
  120 + out_be32((u32*)&gpio->sint_ddr, SINT_DDR);
  121 + out_be32((u32*)&gpio->sint_dvo, SINT_DVO);
  122 + out_be32((u32*)&gpio->sint_inten, SINT_INTEN);
  123 + out_be32((u32*)&gpio->sint_itype, SINT_ITYPE);
  124 + out_be32((u32*)&gpio->sint_gpioe, SINT_GPIOEN);
  125 +
  126 + out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
  127 + out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
  128 + out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
  129 + out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
  130 +
  131 + printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
  132 + printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe);
  133 +}
  134 +
  135 +void reset_environment(void)
  136 +{
  137 + char *s, sernr[64];
  138 +
  139 + printf("\n*** RESET ENVIRONMENT ***\n");
  140 + memset(sernr, 0, sizeof(sernr));
  141 + s = getenv("serial#");
  142 + if (s) {
  143 + printf("found serial# : %s\n", s);
  144 + strncpy(sernr, s, 64);
  145 + }
  146 + gd->env_valid = 0;
  147 + env_relocate();
  148 + if (s)
  149 + setenv("serial#", sernr);
  150 +}
  151 +
  152 +int misc_init_r(void)
  153 +{
  154 + char *s = getenv("reset_env");
  155 +
  156 + if (!s) {
  157 + if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
  158 + return 0;
  159 + udelay(50000);
  160 + if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
  161 + return 0;
  162 + udelay(50000);
  163 + if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
  164 + return 0;
  165 + }
  166 + printf(" === FACTORY RESET ===\n");
  167 + reset_environment();
  168 + saveenv();
  169 +
  170 + return -1;
  171 +}
  172 +
  173 +int checkboard(void)
  174 +{
  175 + mvbc_init_gpio();
  176 + printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
  177 +
  178 + return 0;
  179 +}
  180 +
  181 +void flash_preinit(void)
  182 +{
  183 + /*
  184 + * Now, when we are in RAM, enable flash write
  185 + * access for detection process.
  186 + * Note that CS_BOOT cannot be cleared when
  187 + * executing in flash.
  188 + */
  189 + clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
  190 +}
  191 +
  192 +void flash_afterinit(ulong size)
  193 +{
  194 + out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CFG_BOOTCS_START |
  195 + size));
  196 + out_be32((u32*)MPC5XXX_CS0_START, START_REG(CFG_BOOTCS_START |
  197 + size));
  198 + out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CFG_BOOTCS_START | size,
  199 + size));
  200 + out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CFG_BOOTCS_START | size,
  201 + size));
  202 +}
  203 +
  204 +void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
  205 +{
  206 + unsigned char line = 0xff;
  207 + u32 base;
  208 +
  209 + if (PCI_BUS(dev) == 0) {
  210 + switch (PCI_DEV (dev)) {
  211 + case 0xa: /* FPGA */
  212 + line = 3;
  213 + pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
  214 + printf("found FPA - enable arbitration\n");
  215 + writel(0x03, (u32*)(base + 0x80c0));
  216 + writel(0xf0, (u32*)(base + 0x8080));
  217 + break;
  218 + case 0xb: /* LAN */
  219 + line = 2;
  220 + break;
  221 + case 0x1a:
  222 + break;
  223 + default:
  224 + printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
  225 + break;
  226 + }
  227 + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
  228 + }
  229 +}
  230 +
  231 +struct pci_controller hose = {
  232 + fixup_irq:pci_mvbc_fixup_irq
  233 +};
  234 +
  235 +int mvbc_p_load_fpga(void)
  236 +{
  237 + size_t data_size = 0;
  238 + void *fpga_data = NULL;
  239 + char *datastr = getenv("fpgadata");
  240 + char *sizestr = getenv("fpgadatasize");
  241 +
  242 + if (datastr)
  243 + fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
  244 + if (sizestr)
  245 + data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
  246 +
  247 + return fpga_load(0, fpga_data, data_size);
  248 +}
  249 +
  250 +extern void pci_mpc5xxx_init(struct pci_controller *);
  251 +
  252 +void pci_init_board(void)
  253 +{
  254 + char *s;
  255 + int load_fpga = 1;
  256 +
  257 + mvbc_p_init_fpga();
  258 + s = getenv("skip_fpga");
  259 + if (s) {
  260 + printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
  261 + load_fpga = 0;
  262 + }
  263 + if (load_fpga) {
  264 + printf("loading FPGA ... ");
  265 + mvbc_p_load_fpga();
  266 + printf("done\n");
  267 + }
  268 + pci_mpc5xxx_init(&hose);
  269 +}
  270 +
  271 +u8 *dhcp_vendorex_prep(u8 *e)
  272 +{
  273 + char *ptr;
  274 +
  275 + /* DHCP vendor-class-identifier = 60 */
  276 + if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
  277 + *e++ = 60;
  278 + *e++ = strlen(ptr);
  279 + while (*ptr)
  280 + *e++ = *ptr++;
  281 + }
  282 + /* DHCP_CLIENT_IDENTIFIER = 61 */
  283 + if ((ptr = getenv("dhcp_client_id"))) {
  284 + *e++ = 61;
  285 + *e++ = strlen(ptr);
  286 + while (*ptr)
  287 + *e++ = *ptr++;
  288 + }
  289 +
  290 + return e;
  291 +}
  292 +
  293 +u8 *dhcp_vendorex_proc (u8 *popt)
  294 +{
  295 + return NULL;
  296 +}
  297 +
  298 +void show_boot_progress(int val)
  299 +{
  300 + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
  301 +
  302 + switch(val) {
  303 + case 0: /* FPGA ok */
  304 + setbits_be32(&gpio->simple_dvo, 0x80);
  305 + break;
  306 + case 1:
  307 + setbits_be32(&gpio->simple_dvo, 0x40);
  308 + break;
  309 + case 12:
  310 + setbits_be32(&gpio->simple_dvo, 0x20);
  311 + break;
  312 + case 15:
  313 + setbits_be32(&gpio->simple_dvo, 0x10);
  314 + break;
  315 + default:
  316 + break;
  317 + }
  318 +
  319 +}
  320 +
  321 +void ft_board_setup(void *blob, bd_t *bd)
  322 +{
  323 + ft_cpu_setup(blob, bd);
  324 + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
  325 +}
board/matrix_vision/mvbc_p/mvbc_p.h
Diff comments   View file @ 5e0de0e
  1 +#ifndef __MVBC_H__
  2 +#define __MVBC_H__
  3 +
  4 +#define LED_G0 MPC5XXX_GPIO_SIMPLE_PSC2_0
  5 +#define LED_G1 MPC5XXX_GPIO_SIMPLE_PSC2_1
  6 +#define LED_Y MPC5XXX_GPIO_SIMPLE_PSC2_2
  7 +#define LED_R MPC5XXX_GPIO_SIMPLE_PSC2_3
  8 +#define ARB_X_EN MPC5XXX_GPIO_WKUP_PSC2_4
  9 +
  10 +#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0
  11 +#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1
  12 +#define FPGA_CONF_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2
  13 +#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3
  14 +#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4
  15 +
  16 +#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0
  17 +#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1
  18 +#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2
  19 +#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3
  20 +#define FACT_RST MPC5XXX_GPIO_WKUP_6
  21 +#define FLASH_RBY MPC5XXX_GPIO_WKUP_7
  22 +
  23 +#define SIMPLE_DDR (LED_G0 | LED_G1 | LED_Y | LED_R | \
  24 + FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI)
  25 +#define SIMPLE_DVO (FPGA_CONFIG)
  26 +#define SIMPLE_ODE (FPGA_CONFIG)
  27 +#define SIMPLE_GPIOEN (LED_G0 | LED_G1 | LED_Y | LED_R | \
  28 + FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\
  29 + WD_WDI | COP_PRESENT)
  30 +
  31 +#define SINT_ODE 0
  32 +#define SINT_DDR 0
  33 +#define SINT_DVO 0
  34 +#define SINT_INTEN 0
  35 +#define SINT_ITYPE 0
  36 +#define SINT_GPIOEN (FPGA_STATUS)
  37 +
  38 +#define WKUP_ODE (MAN_RST)
  39 +#define WKUP_DIR (ARB_X_EN|MAN_RST|WD_TS)
  40 +#define WKUP_DO (ARB_X_EN|MAN_RST|WD_TS)
  41 +#define WKUP_EN (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY)
  42 +
  43 +#endif
board/matrix_vision/mvbc_p/mvbc_p_autoscript
Diff comments   View file @ 5e0de0e
  1 +echo
  2 +echo "==== running autoscript ===="
  3 +echo
  4 +setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
  5 +setenv ramkernel setenv kernel_boot \${loadaddr}
  6 +setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
  7 +setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
  8 +setenv bootfromflash run flashkernel cpird ramparam addcons e1000para bootdtb
  9 +setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
  10 +setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
  11 +setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
  12 +setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
  13 +if test ${console} = yes;
  14 +then
  15 +setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baudrate}N8
  16 +else
  17 +setenv addcons setenv bootargs \${bootargs} console=tty0
  18 +fi
  19 +setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=1500 e1000.SmartPowerDownEnable=1
  20 +setenv set_static_ip setenv ipaddr \${static_ipaddr}
  21 +setenv set_static_nm setenv netmask \${static_netmask}
  22 +setenv set_static_gw setenv gatewayip \${static_gateway}
  23 +setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
  24 +setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
  25 +if test ${autoscr_boot} != no;
  26 +then
  27 + if test ${netboot} = yes;
  28 + then
  29 + bootp
  30 + if test $? = 0;
  31 + then
  32 + echo "=== bootp succeeded -> netboot ==="
  33 + run set_ip
  34 + run getdtb rundtb bootfromnet ramparam addcons e1000para bootdtb
  35 + else
  36 + echo "=== netboot failed ==="
  37 + fi
  38 + fi
  39 + run set_static_ip set_static_nm set_static_gw set_ip
  40 + echo "=== bootfromflash ==="
  41 + run cpdtb rundtb bootfromflash
  42 +else
  43 + echo "=== boot stopped with autoscr_boot no ==="
  44 +fi
  1 +Matrix Vision mvBlueCOUGAR-P (mvBC-P)
  2 +-------------------------------------
  3 +
  4 +1. Board Description
  5 +
  6 + The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera
  7 + with main focus on GigEVision protocol in combination with local image
  8 + preprocessing.
  9 +
  10 + Power Supply is either VDC 48V or Pover over Ethernet (PoE).
  11 +
  12 +2 System Components
  13 +
  14 +2.1 CPU
  15 + Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
  16 + 64MB SDRAM @ 133MHz.
  17 + 8 MByte Nor Flash on local bus.
  18 + 1 serial ports. Console running on ttyS0 @ 115200 8N1.
  19 +
  20 +2.2 PCI
  21 + PCI clock fixed at 66MHz. Arbitration inside FPGA.
  22 + Intel GD82541ER network MAC/PHY and FPGA connected.
  23 +
  24 +2.3 FPGA
  25 + Altera Cyclone-II EP2C8 with PCI DMA engine.
  26 + Connects to Matrix Vision specific CCD/CMOS sensor interface.
  27 + Utilizes 64MB Nand Flash.
  28 +
  29 +2.3.1 I/O @ FPGA
  30 + 2 Outputs : photo coupler
  31 + 2 Inputs : photo coupler
  32 +
  33 +2.4 I2C
  34 + LM75 @ 0x90 for temperature monitoring.
  35 + EEPROM @ 0xA0 for vendor specifics.
  36 + image sensor interface (slave adresses depend on sensor)
  37 +
  38 +3 Flash layout.
  39 +
  40 + reset vector is 0x00000100, i.e. "LOWBOOT".
  41 +
  42 + FF800000 u-boot
  43 + FF840000 u-boot script image
  44 + FF850000 redundant u-boot script image
  45 + FF860000 FPGA raw bit file
  46 + FF8A0000 tbd.
  47 + FF900000 root FS
  48 + FFC00000 kernel
  49 + FFFC0000 device tree blob
  50 + FFFD0000 redundant device tree blob
  51 + FFFE0000 environment
  52 + FFFF0000 redundant environment
  53 +
  54 + mtd partitions are propagated to linux kernel via device tree blob.
  55 +
  56 +4 Booting
  57 +
  58 + On startup the bootscript @ FF840000 is executed. This script can be
  59 + exchanged easily. Default boot mode is "boot from flash", i.e. system
  60 + works stand-alone.
  61 +
  62 + This behaviour depends on some environment variables :
  63 +
  64 + "netboot" : yes ->try dhcp/bootp and boot from network.
  65 + A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
  66 + DHCP server configuration, e.g. to provide different images to
  67 + different devices.
  68 +
  69 + During netboot the system tries to get 3 image files:
  70 + 1. Kernel - name + data is given during BOOTP.
  71 + 2. Initrd - name is stored in "initrd_name"
  72 + 3. device tree blob - name is stored in "dtb_name"
  73 + Fallback files are the flash versions.
include/configs/MVBC_P.h
Diff comments   View file @ 5e0de0e
  1 +/*
  2 + * (C) Copyright 2003-2004
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * (C) Copyright 2004-2008
  6 + * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +#ifndef __CONFIG_H
  28 +#define __CONFIG_H
  29 +
  30 +#include <version.h>
  31 +
  32 +#define CONFIG_MPC5xxx 1
  33 +#define CONFIG_MPC5200 1
  34 +
  35 +#define CFG_MPC5XXX_CLKIN 33000000
  36 +
  37 +#define BOOTFLAG_COLD 0x01
  38 +#define BOOTFLAG_WARM 0x02
  39 +
  40 +#define CONFIG_MISC_INIT_R 1
  41 +
  42 +#define CFG_CACHELINE_SIZE 32
  43 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  44 +#define CFG_CACHELINE_SHIFT 5
  45 +#endif
  46 +
  47 +#define CONFIG_PSC_CONSOLE 1
  48 +#define CONFIG_BAUDRATE 115200
  49 +#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
  50 +
  51 +#define CONFIG_PCI 1
  52 +#define CONFIG_PCI_PNP 1
  53 +#undef CONFIG_PCI_SCAN_SHOW
  54 +#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  55 +
  56 +#define CONFIG_PCI_MEM_BUS 0x40000000
  57 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
  58 +#define CONFIG_PCI_MEM_SIZE 0x10000000
  59 +
  60 +#define CONFIG_PCI_IO_BUS 0x50000000
  61 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
  62 +#define CONFIG_PCI_IO_SIZE 0x01000000
  63 +
  64 +#define CFG_XLB_PIPELINING 1
  65 +#define CONFIG_HIGH_BATS 1
  66 +
  67 +#define MV_CI mvBlueCOUGAR-P
  68 +#define MV_VCI mvBlueCOUGAR-P
  69 +#define MV_FPGA_DATA 0xff860000
  70 +#define MV_FPGA_SIZE 0x0003c886
  71 +#define MV_KERNEL_ADDR 0xffc00000
  72 +#define MV_INITRD_ADDR 0xff900000
  73 +#define MV_INITRD_LENGTH 0x00300000
  74 +#define MV_SCRATCH_ADDR 0x00000000
  75 +#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
  76 +#define MV_AUTOSCR_ADDR 0xff840000
  77 +#define MV_AUTOSCR_ADDR2 0xff850000
  78 +#define MV_DTB_ADDR 0xfffc0000
  79 +
  80 +#define CONFIG_SHOW_BOOT_PROGRESS 1
  81 +
  82 +#define MV_KERNEL_ADDR_RAM 0x00100000
  83 +#define MV_DTB_ADDR_RAM 0x00600000
  84 +#define MV_INITRD_ADDR_RAM 0x01000000
  85 +
  86 +/* pass open firmware flat tree */
  87 +#define CONFIG_OF_LIBFDT 1
  88 +#define CONFIG_OF_BOARD_SETUP 1
  89 +
  90 +#define OF_CPU "PowerPC,5200@0"
  91 +#define OF_SOC "soc5200@f0000000"
  92 +#define OF_TBCLK (bd->bi_busfreq / 4)
  93 +#define MV_DTB_NAME mvbc-p.dtb
  94 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1
  95 +
  96 +/*
  97 + * Supported commands
  98 + */
  99 +#include <config_cmd_default.h>
  100 +
  101 +#define CONFIG_CMD_CACHE
  102 +#define CONFIG_CMD_NET
  103 +#define CONFIG_CMD_PING
  104 +#define CONFIG_CMD_DHCP
  105 +#define CONFIG_CMD_SDRAM
  106 +#define CONFIG_CMD_PCI
  107 +#define CONFIG_CMD_FPGA
  108 +
  109 +#undef CONFIG_WATCHDOG
  110 +
  111 +#define CONFIG_BOOTP_VENDOREX
  112 +#define CONFIG_BOOTP_SUBNETMASK
  113 +#define CONFIG_BOOTP_GATEWAY
  114 +#define CONFIG_BOOTP_DNS
  115 +#define CONFIG_BOOTP_DNS2
  116 +#define CONFIG_BOOTP_HOSTNAME
  117 +#define CONFIG_BOOTP_BOOTFILESIZE
  118 +#define CONFIG_BOOTP_BOOTPATH
  119 +#define CONFIG_BOOTP_NTPSERVER
  120 +#define CONFIG_BOOTP_RANDOM_DELAY
  121 +#define CONFIG_BOOTP_SEND_HOSTNAME
  122 +
  123 +/*
  124 + * Autoboot
  125 + */
  126 +#define CONFIG_BOOTDELAY 2
  127 +#define CONFIG_AUTOBOOT_KEYED
  128 +#define CONFIG_AUTOBOOT_STOP_STR "s"
  129 +#define CONFIG_ZERO_BOOTDELAY_CHECK
  130 +#define CONFIG_RESET_TO_RETRY 1000
  131 +
  132 +#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \
  133 + then autoscr ${autoscr_addr}; \
  134 + else autoscr ${autoscr_addr2}; \
  135 + fi;"
  136 +
  137 +#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
  138 +#define CONFIG_ENV_OVERWRITE
  139 +
  140 +#define XMK_STR(x) #x
  141 +#define MK_STR(x) XMK_STR(x)
  142 +
  143 +#define CONFIG_EXTRA_ENV_SETTINGS \
  144 + "console_nr=0\0" \
  145 + "console=yes\0" \
  146 + "stdin=serial\0" \
  147 + "stdout=serial\0" \
  148 + "stderr=serial\0" \
  149 + "fpga=0\0" \
  150 + "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
  151 + "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
  152 + "autoscr_addr=" MK_STR(MV_AUTOSCR_ADDR) "\0" \
  153 + "autoscr_addr2=" MK_STR(MV_AUTOSCR_ADDR2) "\0" \
  154 + "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
  155 + "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
  156 + "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
  157 + "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
  158 + "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
  159 + "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
  160 + "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
  161 + "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
  162 + "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
  163 + "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
  164 + "mv_version=" U_BOOT_VERSION "\0" \
  165 + "dhcp_client_id=" MK_STR(MV_CI) "\0" \
  166 + "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
  167 + "netretry=no\0" \
  168 + "use_static_ipaddr=no\0" \
  169 + "static_ipaddr=192.168.90.10\0" \
  170 + "static_netmask=255.255.255.0\0" \
  171 + "static_gateway=0.0.0.0\0" \
  172 + "initrd_name=uInitrd.mvbc-p-rfs\0" \
  173 + "zcip=no\0" \
  174 + "netboot=yes\0" \
  175 + "mvtest=Ff\0" \
  176 + "tried_bootfromflash=no\0" \
  177 + "tried_bootfromnet=no\0" \
  178 + "use_dhcp=yes\0" \
  179 + "gev_start=yes\0" \
  180 + "mvbcdma_debug=0\0" \
  181 + "mvbcia_debug=0\0" \
  182 + "propdev_debug=0\0" \
  183 + "gevss_debug=0\0" \
  184 + "watchdog=1\0" \
  185 + ""
  186 +
  187 +#undef XMK_STR
  188 +#undef MK_STR
  189 +
  190 +/*
  191 + * IPB Bus clocking configuration.
  192 + */
  193 +#define CFG_IPBCLK_EQUALS_XLBCLK
  194 +#define CFG_PCICLK_EQUALS_IPBCLK_DIV2
  195 +
  196 +/*
  197 + * Flash configuration
  198 + */
  199 +#undef CONFIG_FLASH_16BIT
  200 +#define CFG_FLASH_CFI
  201 +#define CFG_FLASH_CFI_DRIVER
  202 +#define CFG_FLASH_CFI_AMD_RESET 1
  203 +#define CFG_FLASH_EMPTY_INFO
  204 +
  205 +#define CFG_FLASH_ERASE_TOUT 50000
  206 +#define CFG_FLASH_WRITE_TOUT 1000
  207 +
  208 +#define CFG_MAX_FLASH_BANKS 1
  209 +#define CFG_MAX_FLASH_SECT 256
  210 +
  211 +#define CFG_LOWBOOT
  212 +#define CFG_FLASH_BASE TEXT_BASE
  213 +#define CFG_FLASH_SIZE 0x00800000
  214 +
  215 +/*
  216 + * Environment settings
  217 + */
  218 +#define CFG_ENV_IS_IN_FLASH
  219 +#undef CFG_FLASH_PROTECTION
  220 +
  221 +#define CFG_ENV_ADDR 0xFFFE0000
  222 +#define CFG_ENV_SIZE 0x10000
  223 +#define CFG_ENV_SECT_SIZE 0x10000
  224 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE)
  225 +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
  226 +
  227 +/*
  228 + * Memory map
  229 + */
  230 +#define CFG_MBAR 0xF0000000
  231 +#define CFG_SDRAM_BASE 0x00000000
  232 +#define CFG_DEFAULT_MBAR 0x80000000
  233 +
  234 +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
  235 +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
  236 +
  237 +#define CFG_GBL_DATA_SIZE 128
  238 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  239 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  240 +
  241 +#define CFG_MONITOR_BASE TEXT_BASE
  242 +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
  243 +#define CFG_RAMBOOT 1
  244 +#endif
  245 +
  246 +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
  247 +#define CFG_MONITOR_LEN (512 << 10)
  248 +#define CFG_MALLOC_LEN (512 << 10)
  249 +#define CFG_BOOTMAPSZ (8 << 20)
  250 +
  251 +/*
  252 + * Ethernet configuration
  253 + */
  254 +#define CONFIG_NET_MULTI
  255 +#define CONFIG_NET_RETRY_COUNT 5
  256 +
  257 +#define CONFIG_E1000
  258 +#define CONFIG_E1000_FALLBACK_MAC 0xb6b445ebfbc0
  259 +#undef CONFIG_MPC5xxx_FEC
  260 +#undef CONFIG_PHY_ADDR
  261 +#define CONFIG_NETDEV eth0
  262 +
  263 +/*
  264 + * Miscellaneous configurable options
  265 + */
  266 +#define CFG_HUSH_PARSER
  267 +#define CONFIG_CMDLINE_EDITING
  268 +#define CFG_PROMPT_HUSH_PS2 "> "
  269 +#undef CFG_LONGHELP
  270 +#define CFG_PROMPT "=> "
  271 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  272 +#define CFG_CBSIZE 1024
  273 +#else
  274 +#define CFG_CBSIZE 256
  275 +#endif
  276 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
  277 +#define CFG_MAXARGS 16
  278 +#define CFG_BARGSIZE CFG_CBSIZE
  279 +
  280 +#define CFG_MEMTEST_START 0x00800000
  281 +#define CFG_MEMTEST_END 0x02f00000
  282 +
  283 +#define CFG_HZ 1000
  284 +
  285 +/* default load address */
  286 +#define CFG_LOAD_ADDR 0x02000000
  287 +/* default location for tftp and bootm */
  288 +#define CONFIG_LOADADDR 0x00200000
  289 +
  290 +/*
  291 + * Various low-level settings
  292 + */
  293 +#define CFG_GPS_PORT_CONFIG 0x20000004
  294 +
  295 +#define CFG_HID0_INIT (HID0_ICE | HID0_ICFI)
  296 +#define CFG_HID0_FINAL HID0_ICE
  297 +
  298 +#define CFG_BOOTCS_START CFG_FLASH_BASE
  299 +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
  300 +#define CFG_BOOTCS_CFG 0x00047800
  301 +#define CFG_CS0_START CFG_FLASH_BASE
  302 +#define CFG_CS0_SIZE CFG_FLASH_SIZE
  303 +
  304 +#define CFG_CS_BURST 0x000000f0
  305 +#define CFG_CS_DEADCYCLE 0x33333303
  306 +
  307 +#define CFG_RESET_ADDRESS 0x00000100
  308 +
  309 +#undef FPGA_DEBUG
  310 +#undef CFG_FPGA_PROG_FEEDBACK
  311 +#define CONFIG_FPGA CFG_ALTERA_CYCLON2
  312 +#define CONFIG_FPGA_ALTERA 1
  313 +#define CONFIG_FPGA_CYCLON2 1
  314 +#define CONFIG_FPGA_COUNT 1
  315 +
  316 +#endif
... ... @@ -198,6 +198,35 @@
198 198 #define GPIO_PSC3_9 0x04000000UL
199 199 #define GPIO_PSC1_4 0x01000000UL
200 200  
  201 +#define MPC5XXX_GPIO_SIMPLE_PSC6_3 0x20000000UL
  202 +#define MPC5XXX_GPIO_SIMPLE_PSC6_2 0x10000000UL
  203 +#define MPC5XXX_GPIO_SIMPLE_PSC3_7 0x00002000UL
  204 +#define MPC5XXX_GPIO_SIMPLE_PSC3_6 0x00001000UL
  205 +#define MPC5XXX_GPIO_SIMPLE_PSC3_3 0x00000800UL
  206 +#define MPC5XXX_GPIO_SIMPLE_PSC3_2 0x00000400UL
  207 +#define MPC5XXX_GPIO_SIMPLE_PSC3_1 0x00000200UL
  208 +#define MPC5XXX_GPIO_SIMPLE_PSC3_0 0x00000100UL
  209 +#define MPC5XXX_GPIO_SIMPLE_PSC2_3 0x00000080UL
  210 +#define MPC5XXX_GPIO_SIMPLE_PSC2_2 0x00000040UL
  211 +#define MPC5XXX_GPIO_SIMPLE_PSC2_1 0x00000020UL
  212 +#define MPC5XXX_GPIO_SIMPLE_PSC2_0 0x00000010UL
  213 +#define MPC5XXX_GPIO_SIMPLE_PSC1_3 0x00000008UL
  214 +#define MPC5XXX_GPIO_SIMPLE_PSC1_2 0x00000004UL
  215 +#define MPC5XXX_GPIO_SIMPLE_PSC1_1 0x00000002UL
  216 +#define MPC5XXX_GPIO_SIMPLE_PSC1_0 0x00000001UL
  217 +
  218 +#define MPC5XXX_GPIO_SINT_PSC3_5 0x02
  219 +#define MPC5XXX_GPIO_SINT_PSC3_4 0x01
  220 +
  221 +#define MPC5XXX_GPIO_WKUP_7 0x80
  222 +#define MPC5XXX_GPIO_WKUP_6 0x40
  223 +#define MPC5XXX_GPIO_WKUP_PSC6_1 0x20
  224 +#define MPC5XXX_GPIO_WKUP_PSC6_0 0x10
  225 +#define MPC5XXX_GPIO_WKUP_ETH17 0x08
  226 +#define MPC5XXX_GPIO_WKUP_PSC3_9 0x04
  227 +#define MPC5XXX_GPIO_WKUP_PSC2_4 0x02
  228 +#define MPC5XXX_GPIO_WKUP_PSC1_4 0x01
  229 +
201 230 /* PCI registers */
202 231 #define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
203 232 #define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)