Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 5e1dae5c3db7f4026f31b6a2a81ecd9e9dee475f

Authored by William Juul
Committed by Scott Wood
1 parent 4cbb651b29
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Fixing coding style issues 

- Fixing leading white spaces
 - Fixing indentation where 4 spaces are used instead of tab
 - Removing C++ comments (//), wherever I introduced them

Signed-off-by: William Juul <william.juul@tandberg.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

Showing 18 changed files with 106 additions and 99 deletions Side-by-side Diff

board/bf537-stamp/nand.c
Diff comments   View file @ 5e1dae5
... ... @@ -40,7 +40,7 @@
40 40 static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
41 41 {
42 42 register struct nand_chip *this = mtd->priv;
43   - u32 IO_ADDR_W = (u32) this->IO_ADDR_W;
  43 + u32 IO_ADDR_W = (u32) this->IO_ADDR_W;
44 44  
45 45 if (ctrl & NAND_CTRL_CHANGE) {
46 46 if( ctrl & NAND_CLE )
board/dave/PPChameleonEVB/nand.c
Diff comments   View file @ 5e1dae5
... ... @@ -36,7 +36,7 @@
36 36 struct nand_chip *this = mtd->priv;
37 37 ulong base = (ulong) this->IO_ADDR_W;
38 38  
39   - if (ctrl & NAND_CTRL_CHANGE) {
  39 + if (ctrl & NAND_CTRL_CHANGE) {
40 40 if ( ctrl & NAND_CLE )
41 41 MACRO_NAND_CTL_SETCLE((unsigned long)base);
42 42 else
... ... @@ -51,7 +51,7 @@
51 51 MACRO_NAND_DISABLE_CE((unsigned long)base);
52 52 }
53 53  
54   - if (cmd != NAND_CMD_NONE)
  54 + if (cmd != NAND_CMD_NONE)
55 55 writeb(cmd, this->IO_ADDR_W);
56 56 }
57 57  
... ... @@ -549,7 +549,7 @@
549 549 nand->write_buf = dfc_write_buf;
550 550  
551 551 nand->cmdfunc = dfc_cmdfunc;
552   -// nand->autooob = &delta_oob;
  552 +/* nand->autooob = &delta_oob; */
553 553 nand->badblock_pattern = &delta_bbt_descr;
554 554 return 0;
555 555 }
board/esd/common/esd405ep_nand.c
Diff comments   View file @ 5e1dae5
... ... @@ -32,8 +32,8 @@
32 32 */
33 33 static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
34 34 {
35   - struct nand_chip *this = mtd->priv;
36   - if (ctrl & NAND_CTRL_CHANGE) {
  35 + struct nand_chip *this = mtd->priv;
  36 + if (ctrl & NAND_CTRL_CHANGE) {
37 37 if ( ctrl & NAND_CLE )
38 38 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
39 39 else
... ... @@ -48,7 +48,7 @@
48 48 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
49 49 }
50 50  
51   - if (cmd != NAND_CMD_NONE)
  51 + if (cmd != NAND_CMD_NONE)
52 52 writeb(cmd, this->IO_ADDR_W);
53 53 }
54 54  
... ... @@ -36,7 +36,7 @@
36 36 {
37 37 struct nand_chip *this = mtd->priv;
38 38  
39   - if (ctrl & NAND_CTRL_CHANGE) {
  39 + if (ctrl & NAND_CTRL_CHANGE) {
40 40 if ( ctrl & NAND_CLE )
41 41 this->IO_ADDR_W += 2;
42 42 else
... ... @@ -47,7 +47,7 @@
47 47 this->IO_ADDR_W -= 1;
48 48 }
49 49  
50   - if (cmd != NAND_CMD_NONE)
  50 + if (cmd != NAND_CMD_NONE)
51 51 writeb(cmd, this->IO_ADDR_W);
52 52 }
53 53 #elif defined(CONFIG_IDS852_REV2)
... ... @@ -58,7 +58,7 @@
58 58 {
59 59 struct nand_chip *this = mtd->priv;
60 60  
61   - if (ctrl & NAND_CTRL_CHANGE) {
  61 + if (ctrl & NAND_CTRL_CHANGE) {
62 62 if ( ctrl & NAND_CLE )
63 63 writeb(0, (volatile __u8 *) this->IO_ADDR_W + 0xa);
64 64 else
... ... @@ -73,7 +73,7 @@
73 73 writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0xc);
74 74 }
75 75  
76   - if (cmd != NAND_CMD_NONE)
  76 + if (cmd != NAND_CMD_NONE)
77 77 writeb(cmd, this->IO_ADDR_W);
78 78 }
79 79 #else
board/netstar/nand.c
Diff comments   View file @ 5e1dae5
... ... @@ -47,7 +47,7 @@
47 47 }
48 48 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
49 49  
50   - if (cmd != NAND_CMD_NONE)
  50 + if (cmd != NAND_CMD_NONE)
51 51 writeb(cmd, this->IO_ADDR_W);
52 52 }
53 53  
board/prodrive/alpr/nand.c
Diff comments   View file @ 5e1dae5
... ... @@ -58,7 +58,7 @@
58 58 */
59 59 static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
60 60 {
61   - struct nand_chip *this = mtd->priv;
  61 + struct nand_chip *this = mtd->priv;
62 62  
63 63 if (ctrl & NAND_CTRL_CHANGE) {
64 64 if ( ctrl & NAND_CLE )
board/prodrive/pdnb3/nand.c
Diff comments   View file @ 5e1dae5
... ... @@ -54,7 +54,7 @@
54 54 */
55 55 static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
56 56 {
57   - struct nand_chip *this = mtd->priv;
  57 + struct nand_chip *this = mtd->priv;
58 58  
59 59 if (ctrl & NAND_CTRL_CHANGE) {
60 60 if ( ctrl & NAND_CLE )
... ... @@ -41,8 +41,8 @@
41 41  
42 42 static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
43 43 {
44   - struct nand_chip *this = mtd->priv;
45   - if (ctrl & NAND_CTRL_CHANGE) {
  44 + struct nand_chip *this = mtd->priv;
  45 + if (ctrl & NAND_CTRL_CHANGE) {
46 46 if ( ctrl & NAND_CLE )
47 47 set_bit (SC3_NAND_CLE, sc3_control_base);
48 48 else
... ... @@ -57,7 +57,7 @@
57 57 clear_bit (SC3_NAND_CE, sc3_control_base);
58 58 }
59 59  
60   - if (cmd != NAND_CMD_NONE)
  60 + if (cmd != NAND_CMD_NONE)
61 61 writeb(cmd, this->IO_ADDR_W);
62 62 }
63 63  
board/tqc/tqm8272/tqm8272.c
Diff comments   View file @ 5e1dae5
... ... @@ -1070,7 +1070,7 @@
1070 1070  
1071 1071 static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
1072 1072 {
1073   - struct nand_chip *this = mtd->priv;
  1073 + struct nand_chip *this = mtd->priv;
1074 1074  
1075 1075 if (ctrl & NAND_CTRL_CHANGE) {
1076 1076 if ( ctrl & NAND_CLE )
board/zylonite/nand.c
Diff comments   View file @ 5e1dae5
... ... @@ -553,7 +553,7 @@
553 553 nand->write_buf = dfc_write_buf;
554 554  
555 555 nand->cmdfunc = dfc_cmdfunc;
556   -// nand->autooob = &delta_oob;
  556 +/* nand->autooob = &delta_oob; */
557 557 nand->badblock_pattern = &delta_bbt_descr;
558 558 return 0;
559 559 }
... ... @@ -35,7 +35,7 @@
35 35 int mtdparts_init(void);
36 36 int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num);
37 37 int find_dev_and_part(const char *id, struct mtd_device **dev,
38   - u8 *part_num, struct part_info **part);
  38 + u8 *part_num, struct part_info **part);
39 39 #endif
40 40  
41 41 static int nand_dump_oob(nand_info_t *nand, ulong off)
... ... @@ -340,7 +340,7 @@
340 340 opts.length = size;
341 341 opts.offset = off;
342 342 opts.quiet = quiet;
343   -// ret = nand_read_opts(nand, &opts);
  343 +/* ret = nand_read_opts(nand, &opts); */
344 344 } else {
345 345 /* write */
346 346 mtd_oob_ops_t opts;
347 347  
348 348  
349 349  
350 350  
... ... @@ -406,44 +406,48 @@
406 406 }
407 407  
408 408 if (status) {
409   -// ulong block_start = 0;
410 409 ulong off;
411   -// int last_status = -1;
412   -
  410 +/* ulong block_start = 0;
  411 + int last_status = -1;
  412 +*/
413 413 struct nand_chip *nand_chip = nand->priv;
414 414 /* check the WP bit */
415 415 nand_chip->cmdfunc (nand, NAND_CMD_STATUS, -1, -1);
416 416 printf("device is %swrite protected\n",
417 417 (nand_chip->read_byte(nand) & 0x80 ?
418   - "NOT " : "" ) );
  418 + "NOT " : ""));
419 419  
420 420 for (off = 0; off < nand->size; off += nand->writesize) {
421   -// int s = nand_get_lock_status(nand, off);
422   -//
423   -// /* print message only if status has changed
424   -// * or at end of chip
425   -// */
426   -// if (off == nand->size - nand->writesize
427   -// || (s != last_status && off != 0)) {
428   -//
429   -// printf("%08lx - %08lx: %8d pages %s%s%s\n",
430   -// block_start,
431   -// off-1,
432   -// (off-block_start)/nand->writesize,
433   -// ((last_status & NAND_LOCK_STATUS_TIGHT) ? "TIGHT " : ""),
434   -// ((last_status & NAND_LOCK_STATUS_LOCK) ? "LOCK " : ""),
435   -// ((last_status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : ""));
436   -// }
437   -//
438   -// last_status = s;
  421 +#if 0 /* must be fixed */
  422 + int s = nand_get_lock_status(nand, off);
  423 +
  424 + /* print message only if status has changed
  425 + * or at end of chip
  426 + */
  427 + if (off == nand->size - nand->writesize
  428 + || (s != last_status && off != 0)) {
  429 +
  430 + printf("%08lx - %08lx: %8d pages %s%s%s\n",
  431 + block_start,
  432 + off-1,
  433 + (off-block_start)/nand->writesize,
  434 + ((last_status & NAND_LOCK_STATUS_TIGHT) ? "TIGHT " : ""),
  435 + ((last_status & NAND_LOCK_STATUS_LOCK) ? "LOCK " : ""),
  436 + ((last_status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : ""));
  437 + }
  438 +
  439 + last_status = s;
  440 +#endif
439 441 }
440 442 } else {
441   -// if (!nand_lock(nand, tight)) {
442   -// puts("NAND flash successfully locked\n");
443   -// } else {
444   -// puts("Error locking NAND flash\n");
445   -// return 1;
446   -// }
  443 +#if 0 /* must be fixed */
  444 + if (!nand_lock(nand, tight)) {
  445 + puts("NAND flash successfully locked\n");
  446 + } else {
  447 + puts("Error locking NAND flash\n");
  448 + return 1;
  449 + }
  450 +#endif
447 451 }
448 452 return 0;
449 453 }
... ... @@ -452,13 +456,15 @@
452 456 if (arg_off_size(argc - 2, argv + 2, nand, &off, &size) < 0)
453 457 return 1;
454 458  
455   -// if (!nand_unlock(nand, off, size)) {
456   -// puts("NAND flash successfully unlocked\n");
457   -// } else {
458   -// puts("Error unlocking NAND flash, "
459   -// "write and erase will probably fail\n");
460   -// return 1;
461   -// }
  459 +#if 0 /* must be fixed */
  460 + if (!nand_unlock(nand, off, size)) {
  461 + puts("NAND flash successfully unlocked\n");
  462 + } else {
  463 + puts("Error unlocking NAND flash, "
  464 + "write and erase will probably fail\n");
  465 + return 1;
  466 + }
  467 +#endif
462 468 return 0;
463 469 }
464 470  
... ... @@ -691,7 +697,7 @@
691 697 void archflashwp(void *archdata, int wp);
692 698 #endif
693 699  
694   -#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
  700 +#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
695 701  
696 702 #undef NAND_DEBUG
697 703 #undef PSYCHO_DEBUG
... ... @@ -715,9 +721,9 @@
715 721 #define CONFIG_MTD_NAND_ECC_JFFS2
716 722  
717 723 /* bits for nand_legacy_rw() `cmd'; or together as needed */
718   -#define NANDRW_READ 0x01
719   -#define NANDRW_WRITE 0x00
720   -#define NANDRW_JFFS2 0x02
  724 +#define NANDRW_READ 0x01
  725 +#define NANDRW_WRITE 0x00
  726 +#define NANDRW_JFFS2 0x02
721 727 #define NANDRW_JFFS2_SKIP 0x04
722 728  
723 729 /*
724 730  
725 731  
726 732  
... ... @@ -726,15 +732,15 @@
726 732 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
727 733 extern int curr_device;
728 734 extern int nand_legacy_erase(struct nand_chip *nand, size_t ofs,
729   - size_t len, int clean);
  735 + size_t len, int clean);
730 736 extern int nand_legacy_rw(struct nand_chip *nand, int cmd, size_t start,
731   - size_t len, size_t *retlen, u_char *buf);
  737 + size_t len, size_t *retlen, u_char *buf);
732 738 extern void nand_print(struct nand_chip *nand);
733 739 extern void nand_print_bad(struct nand_chip *nand);
734 740 extern int nand_read_oob(struct nand_chip *nand, size_t ofs,
735   - size_t len, size_t *retlen, u_char *buf);
  741 + size_t len, size_t *retlen, u_char *buf);
736 742 extern int nand_write_oob(struct nand_chip *nand, size_t ofs,
737   - size_t len, size_t *retlen, const u_char *buf);
  743 + size_t len, size_t *retlen, const u_char *buf);
738 744  
739 745  
740 746 int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
... ... @@ -828,11 +834,11 @@
828 834  
829 835 if (strncmp (argv[1], "read", 4) == 0 ||
830 836 strncmp (argv[1], "write", 5) == 0) {
831   - ulong addr = simple_strtoul (argv[2], NULL, 16);
832   - off_t off = simple_strtoul (argv[3], NULL, 16);
833   - size_t size = simple_strtoul (argv[4], NULL, 16);
834   - int cmd = (strncmp (argv[1], "read", 4) == 0) ?
835   - NANDRW_READ : NANDRW_WRITE;
  837 + ulong addr = simple_strtoul (argv[2], NULL, 16);
  838 + off_t off = simple_strtoul (argv[3], NULL, 16);
  839 + size_t size = simple_strtoul (argv[4], NULL, 16);
  840 + int cmd = (strncmp (argv[1], "read", 4) == 0) ?
  841 + NANDRW_READ : NANDRW_WRITE;
836 842 size_t total;
837 843 int ret;
838 844 char *cmdtail = strchr (argv[1], '.');
839 845  
... ... @@ -923,9 +929,9 @@
923 929 "nand device [dev] - show or set current device\n"
924 930 "nand read[.jffs2[s]] addr off size\n"
925 931 "nand write[.jffs2] addr off size - read/write `size' bytes starting\n"
926   - " at offset `off' to/from memory address `addr'\n"
  932 + " at offset `off' to/from memory address `addr'\n"
927 933 "nand erase [clean] [off size] - erase `size' bytes from\n"
928   - " offset `off' (entire device if not specified)\n"
  934 + " offset `off' (entire device if not specified)\n"
929 935 "nand bad - show bad blocks\n"
930 936 "nand read.oob addr off size - read out-of-band data\n"
931 937 "nand write.oob addr off size - read out-of-band data\n"
cpu/arm926ejs/davinci/nand.c
Diff comments   View file @ 5e1dae5
... ... @@ -68,7 +68,7 @@
68 68 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
69 69 }
70 70  
71   - if (cmd != NAND_CMD_NONE)
  71 + if (cmd != NAND_CMD_NONE)
72 72 writeb(cmd, this->IO_ADDR_W);
73 73 }
74 74  
75 75  
76 76  
77 77  
... ... @@ -363,22 +363,22 @@
363 363 #endif
364 364 #ifdef CFG_NAND_HW_ECC
365 365 #ifdef CFG_NAND_LARGEPAGE
366   - nand->ecc.mode = NAND_ECC_HW;
367   - nand->ecc.size = 2048;
368   - nand->ecc.bytes = 12;
  366 + nand->ecc.mode = NAND_ECC_HW;
  367 + nand->ecc.size = 2048;
  368 + nand->ecc.bytes = 12;
369 369 #elif defined(CFG_NAND_SMALLPAGE)
370   - nand->ecc.mode = NAND_ECC_HW;
371   - nand->ecc.size = 512;
372   - nand->ecc.bytes = 3;
  370 + nand->ecc.mode = NAND_ECC_HW;
  371 + nand->ecc.size = 512;
  372 + nand->ecc.bytes = 3;
373 373 #else
374 374 #error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
375 375 #endif
376   -// nand->autooob = &davinci_nand_oobinfo;
  376 +/* nand->autooob = &davinci_nand_oobinfo; */
377 377 nand->ecc.calculate = nand_davinci_calculate_ecc;
378 378 nand->ecc.correct = nand_davinci_correct_data;
379 379 nand->ecc.hwctl = nand_davinci_enable_hwecc;
380 380 #else
381   - nand->ecc.mode = NAND_ECC_SOFT;
  381 + nand->ecc.mode = NAND_ECC_SOFT;
382 382 #endif
383 383  
384 384 /* Set address of hardware control function */
... ... @@ -48,7 +48,7 @@
48 48  
49 49 static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
50 50 {
51   - struct nand_chip *this = mtd->priv;
  51 + struct nand_chip *this = mtd->priv;
52 52  
53 53 if (ctrl & NAND_CTRL_CHANGE) {
54 54 if ( ctrl & NAND_CLE )
... ... @@ -183,12 +183,12 @@
183 183 nand->read_buf = ndfc_read_buf;
184 184 nand->dev_ready = ndfc_dev_ready;
185 185  
186   - nand->ecc.correct = nand_correct_data;
187   - nand->ecc.hwctl = ndfc_enable_hwecc;
188   - nand->ecc.calculate = ndfc_calculate_ecc;
189   - nand->ecc.mode = NAND_ECC_HW;
190   - nand->ecc.size = 256;
191   - nand->ecc.bytes = 3;
  186 + nand->ecc.correct = nand_correct_data;
  187 + nand->ecc.hwctl = ndfc_enable_hwecc;
  188 + nand->ecc.calculate = ndfc_calculate_ecc;
  189 + nand->ecc.mode = NAND_ECC_HW;
  190 + nand->ecc.size = 256;
  191 + nand->ecc.bytes = 3;
192 192  
193 193 #ifndef CONFIG_NAND_SPL
194 194 nand->write_buf = ndfc_write_buf;
drivers/mtd/nand/diskonchip.c
Diff comments   View file @ 5e1dae5
... ... @@ -500,11 +500,11 @@
500 500 struct doc_priv *doc = this->priv;
501 501 void __iomem *docptr = doc->virtadr;
502 502  
503   - //ReadDOC(docptr, CDSNSlowIO);
  503 + /*ReadDOC(docptr, CDSNSlowIO); */
504 504 /* 11.4.5 -- delay twice to allow extended length cycle */
505 505 DoC_Delay(doc, 2);
506 506 ReadDOC(docptr, ReadPipeInit);
507   - //return ReadDOC(docptr, Mil_CDSN_IO);
  507 + /*return ReadDOC(docptr, Mil_CDSN_IO); */
508 508 return ReadDOC(docptr, LastDataRead);
509 509 }
510 510  
... ... @@ -1051,7 +1051,7 @@
1051 1051 return ret;
1052 1052 }
1053 1053  
1054   -//u_char mydatabuf[528];
  1054 +/*u_char mydatabuf[528]; */
1055 1055  
1056 1056 /* The strange out-of-order .oobfree list below is a (possibly unneeded)
1057 1057 * attempt to retain compatibility. It used to read:
1058 1058  
... ... @@ -1623,11 +1623,11 @@
1623 1623 if (ChipID == DOC_ChipID_DocMilPlus16) {
1624 1624 WriteDOC(~newval, virtadr, Mplus_AliasResolution);
1625 1625 oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution);
1626   - WriteDOC(newval, virtadr, Mplus_AliasResolution); // restore it
  1626 + WriteDOC(newval, virtadr, Mplus_AliasResolution); /* restore it */
1627 1627 } else {
1628 1628 WriteDOC(~newval, virtadr, AliasResolution);
1629 1629 oldval = ReadDOC(doc->virtadr, AliasResolution);
1630   - WriteDOC(newval, virtadr, AliasResolution); // restore it
  1630 + WriteDOC(newval, virtadr, AliasResolution); /* restore it */
1631 1631 }
1632 1632 newval = ~newval;
1633 1633 if (oldval == newval) {
drivers/mtd/nand/nand_base.c
Diff comments   View file @ 5e1dae5
... ... @@ -2557,7 +2557,7 @@
2557 2557 default:
2558 2558 printk(KERN_WARNING "No oob scheme defined for "
2559 2559 "oobsize %d\n", mtd->oobsize);
2560   -// BUG();
  2560 +/* BUG(); */
2561 2561 }
2562 2562 }
2563 2563  
include/linux/mtd/compat.h
Diff comments   View file @ 5e1dae5
... ... @@ -18,10 +18,10 @@
18 18 #define KERN_DEBUG
19 19  
20 20 #define kmalloc(size, flags) malloc(size)
21   -#define kzalloc(size, flags) calloc(size, 1)
  21 +#define kzalloc(size, flags) calloc(size, 1)
22 22 #define vmalloc(size) malloc(size)
23   -#define kfree(ptr) free(ptr)
24   -#define vfree(ptr) free(ptr)
  23 +#define kfree(ptr) free(ptr)
  24 +#define vfree(ptr) free(ptr)
25 25  
26 26 #define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
27 27  
include/linux/mtd/nand.h
Diff comments   View file @ 5e1dae5
... ... @@ -236,11 +236,12 @@
236 236 * used instead of the per chip wait queue when a hw controller is available
237 237 */
238 238 struct nand_hw_control {
  239 +/* XXX U-BOOT XXX */
239 240 #if 0
240   - spinlock_t lock;
241   - wait_queue_head_t wq;
  241 + spinlock_t lock;
  242 + wait_queue_head_t wq;
242 243 #endif
243   - struct nand_chip *active;
  244 + struct nand_chip *active;
244 245 };
245 246  
246 247 /**