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Commit 5e5097c110ab5d6bda7f18b7a795d17f27ac3d36

Authored by Shaveta Leekha
Committed by York Sun
1 parent e4b87e5b1d
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

board/b4860qds: Add support to make Aurora work on B4860QDS 

1) Add new SerDes1 protocols having Aurora in them
2) Add VSC cross point connections for Aurora to work with
   CPRI and SGMIIs
3) Configure VSC crossbar switch to connect SerDes1
   lanes to aurora on board, by checking SerDes1 protocols
4) SerDes1 Refclks have been set properly to make
   Aurora, CPRI and SGMIIs to work together properly

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 3 changed files with 111 additions and 4 deletions Inline Diff

arch/powerpc/cpu/mpc85xx/b4860_serdes.c
Diff comments   View file @ 5e5097c
1 /* 1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc. 2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <asm/fsl_serdes.h> 8 #include <asm/fsl_serdes.h>
9 #include <asm/processor.h> 9 #include <asm/processor.h>
10 #include <asm/io.h> 10 #include <asm/io.h>
11 #include "fsl_corenet2_serdes.h" 11 #include "fsl_corenet2_serdes.h"
12 12
13 struct serdes_config { 13 struct serdes_config {
14 u8 protocol; 14 u8 protocol;
15 u8 lanes[SRDS_MAX_LANES]; 15 u8 lanes[SRDS_MAX_LANES];
16 }; 16 };
17 17
18 #ifdef CONFIG_PPC_B4860 18 #ifdef CONFIG_PPC_B4860
19 static struct serdes_config serdes1_cfg_tbl[] = { 19 static struct serdes_config serdes1_cfg_tbl[] = {
20 /* SerDes 1 */ 20 /* SerDes 1 */
21 {0x02, {AURORA, AURORA, CPRI6, CPRI5,
22 CPRI4, CPRI3, CPRI2, CPRI1} },
23 {0x04, {AURORA, AURORA, CPRI6, CPRI5,
24 CPRI4, CPRI3, CPRI2, CPRI1} },
25 {0x05, {AURORA, AURORA, CPRI6, CPRI5,
26 CPRI4, CPRI3, CPRI2, CPRI1} },
27 {0x06, {AURORA, AURORA, CPRI6, CPRI5,
28 CPRI4, CPRI3, CPRI2, CPRI1} },
29 {0x08, {AURORA, AURORA, CPRI6, CPRI5,
30 CPRI4, CPRI3, CPRI2, CPRI1} },
31 {0x09, {AURORA, AURORA, CPRI6, CPRI5,
32 CPRI4, CPRI3, CPRI2, CPRI1} },
33 {0x0A, {AURORA, AURORA, CPRI6, CPRI5,
34 CPRI4, CPRI3, CPRI2, CPRI1} },
35 {0x0B, {AURORA, AURORA, CPRI6, CPRI5,
36 CPRI4, CPRI3, CPRI2, CPRI1} },
37 {0x0C, {AURORA, AURORA, CPRI6, CPRI5,
38 CPRI4, CPRI3, CPRI2, CPRI1} },
21 {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5, 39 {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
22 CPRI4, CPRI3, CPRI2, CPRI1}}, 40 CPRI4, CPRI3, CPRI2, CPRI1}},
23 {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5, 41 {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
24 CPRI4, CPRI3, CPRI2, CPRI1}}, 42 CPRI4, CPRI3, CPRI2, CPRI1}},
25 {0x12, {CPRI8, CPRI7, CPRI6, CPRI5, 43 {0x12, {CPRI8, CPRI7, CPRI6, CPRI5,
26 CPRI4, CPRI3, CPRI2, CPRI1}}, 44 CPRI4, CPRI3, CPRI2, CPRI1}},
27 {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 45 {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
28 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 46 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
29 {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 47 {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
30 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 48 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
31 {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 49 {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
32 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 50 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
33 {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 51 {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
34 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 52 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
35 {0x30, {AURORA, AURORA, 53 {0x30, {AURORA, AURORA,
36 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 54 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
37 CPRI4, CPRI3, CPRI2, CPRI1}}, 55 CPRI4, CPRI3, CPRI2, CPRI1}},
38 {0x32, {AURORA, AURORA, 56 {0x32, {AURORA, AURORA,
39 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 57 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
40 CPRI4, CPRI3, CPRI2, CPRI1}}, 58 CPRI4, CPRI3, CPRI2, CPRI1}},
41 {0x33, {AURORA, AURORA, 59 {0x33, {AURORA, AURORA,
42 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 60 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
43 CPRI4, CPRI3, CPRI2, CPRI1}}, 61 CPRI4, CPRI3, CPRI2, CPRI1}},
44 {0x34, {AURORA, AURORA, 62 {0x34, {AURORA, AURORA,
45 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 63 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
46 CPRI4, CPRI3, CPRI2, CPRI1}}, 64 CPRI4, CPRI3, CPRI2, CPRI1}},
65 {0x39, {AURORA, AURORA, CPRI6, CPRI5,
66 CPRI4, CPRI3, CPRI2, CPRI1} },
67 {0x3A, {AURORA, AURORA, CPRI6, CPRI5,
68 CPRI4, CPRI3, CPRI2, CPRI1} },
69 {0x3C, {AURORA, AURORA, CPRI6, CPRI5,
70 CPRI4, CPRI3, CPRI2, CPRI1} },
71 {0x3D, {AURORA, AURORA, CPRI6, CPRI5,
72 CPRI4, CPRI3, CPRI2, CPRI1} },
47 {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5, 73 {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
48 CPRI4, CPRI3, CPRI2, CPRI1}}, 74 CPRI4, CPRI3, CPRI2, CPRI1}},
75 {0x5C, {AURORA, AURORA,
76 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
77 CPRI4, CPRI3, CPRI2, CPRI1} },
78 {0x5D, {AURORA, AURORA,
79 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
80 CPRI4, CPRI3, CPRI2, CPRI1} },
49 {} 81 {}
50 }; 82 };
51 static struct serdes_config serdes2_cfg_tbl[] = { 83 static struct serdes_config serdes2_cfg_tbl[] = {
52 /* SerDes 2 */ 84 /* SerDes 2 */
53 {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 85 {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
54 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 86 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
55 AURORA, AURORA, SRIO1, SRIO1}}, 87 AURORA, AURORA, SRIO1, SRIO1}},
56 {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 88 {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
57 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 89 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
58 AURORA, AURORA, SRIO1, SRIO1}}, 90 AURORA, AURORA, SRIO1, SRIO1}},
59 {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 91 {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
60 SRIO2, SRIO2, 92 SRIO2, SRIO2,
61 AURORA, AURORA, SRIO1, SRIO1}}, 93 AURORA, AURORA, SRIO1, SRIO1}},
62 {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 94 {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
63 SRIO2, SRIO2, 95 SRIO2, SRIO2,
64 AURORA, AURORA, 96 AURORA, AURORA,
65 SRIO1, SRIO1}}, 97 SRIO1, SRIO1}},
66 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 98 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
67 SGMII_FM1_DTSEC3, AURORA, 99 SGMII_FM1_DTSEC3, AURORA,
68 SRIO1, SRIO1, SRIO1, SRIO1}}, 100 SRIO1, SRIO1, SRIO1, SRIO1}},
69 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 101 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
70 SGMII_FM1_DTSEC3, AURORA, 102 SGMII_FM1_DTSEC3, AURORA,
71 SRIO1, SRIO1, SRIO1, SRIO1}}, 103 SRIO1, SRIO1, SRIO1, SRIO1}},
72 {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 104 {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
73 SGMII_FM1_DTSEC3, AURORA, 105 SGMII_FM1_DTSEC3, AURORA,
74 SRIO1, SRIO1, SRIO1, SRIO1}}, 106 SRIO1, SRIO1, SRIO1, SRIO1}},
75 {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 107 {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
76 SGMII_FM1_DTSEC3, AURORA, 108 SGMII_FM1_DTSEC3, AURORA,
77 SRIO1, SRIO1, SRIO1, SRIO1}}, 109 SRIO1, SRIO1, SRIO1, SRIO1}},
78 {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2, 110 {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
79 SRIO1, SRIO1, SRIO1, SRIO1}}, 111 SRIO1, SRIO1, SRIO1, SRIO1}},
80 {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 112 {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
81 SRIO2, SRIO2, AURORA, AURORA, 113 SRIO2, SRIO2, AURORA, AURORA,
82 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 114 XFI_FM1_MAC9, XFI_FM1_MAC10}},
83 {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 115 {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
84 SRIO2, SRIO2, AURORA, AURORA, 116 SRIO2, SRIO2, AURORA, AURORA,
85 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 117 XFI_FM1_MAC9, XFI_FM1_MAC10}},
86 {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 118 {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
87 SRIO2, SRIO2, 119 SRIO2, SRIO2,
88 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 120 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
89 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 121 XFI_FM1_MAC9, XFI_FM1_MAC10}},
90 {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2, 122 {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
91 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 123 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
92 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 124 XFI_FM1_MAC9, XFI_FM1_MAC10}},
93 {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 125 {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
94 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 126 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
95 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 127 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
96 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 128 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
97 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, 129 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
98 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 130 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
99 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 131 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
100 {0x9A, {PCIE1, PCIE1, 132 {0x9A, {PCIE1, PCIE1,
101 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 133 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
102 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 134 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
103 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 135 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
104 {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1, 136 {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
105 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 137 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
106 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 138 XFI_FM1_MAC9, XFI_FM1_MAC10}},
107 {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 139 {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
108 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 140 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
109 SRIO1, SRIO1, SRIO1, SRIO1}}, 141 SRIO1, SRIO1, SRIO1, SRIO1}},
110 {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 142 {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
111 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 143 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
112 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 144 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
113 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 145 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
114 {} 146 {}
115 }; 147 };
116 #endif 148 #endif
117 149
118 #ifdef CONFIG_PPC_B4420 150 #ifdef CONFIG_PPC_B4420
119 static struct serdes_config serdes1_cfg_tbl[] = { 151 static struct serdes_config serdes1_cfg_tbl[] = {
120 {0x0D, {NONE, NONE, CPRI6, CPRI5, 152 {0x0D, {NONE, NONE, CPRI6, CPRI5,
121 CPRI4, CPRI3, NONE, NONE} }, 153 CPRI4, CPRI3, NONE, NONE} },
122 {0x0E, {NONE, NONE, CPRI8, CPRI5, 154 {0x0E, {NONE, NONE, CPRI8, CPRI5,
123 CPRI4, CPRI3, NONE, NONE} }, 155 CPRI4, CPRI3, NONE, NONE} },
124 {0x0F, {NONE, NONE, CPRI6, CPRI5, 156 {0x0F, {NONE, NONE, CPRI6, CPRI5,
125 CPRI4, CPRI3, NONE, NONE} }, 157 CPRI4, CPRI3, NONE, NONE} },
126 {0x18, {NONE, NONE, 158 {0x18, {NONE, NONE,
127 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 159 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
128 NONE, NONE, NONE, NONE} }, 160 NONE, NONE, NONE, NONE} },
129 {0x1B, {NONE, NONE, 161 {0x1B, {NONE, NONE,
130 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 162 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
131 NONE, NONE, NONE, NONE} }, 163 NONE, NONE, NONE, NONE} },
132 {0x1E, {NONE, NONE, AURORA, AURORA, 164 {0x1E, {NONE, NONE, AURORA, AURORA,
133 NONE, NONE, NONE, NONE} }, 165 NONE, NONE, NONE, NONE} },
134 {0x21, {NONE, NONE, AURORA, AURORA, 166 {0x21, {NONE, NONE, AURORA, AURORA,
135 NONE, NONE, NONE, NONE} }, 167 NONE, NONE, NONE, NONE} },
136 {0x3E, {NONE, NONE, CPRI6, CPRI5, 168 {0x3E, {NONE, NONE, CPRI6, CPRI5,
137 CPRI4, CPRI3, NONE, NONE} }, 169 CPRI4, CPRI3, NONE, NONE} },
138 {} 170 {}
139 }; 171 };
140 static struct serdes_config serdes2_cfg_tbl[] = { 172 static struct serdes_config serdes2_cfg_tbl[] = {
141 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 173 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
142 SGMII_FM1_DTSEC3, AURORA, 174 SGMII_FM1_DTSEC3, AURORA,
143 NONE, NONE, NONE, NONE} }, 175 NONE, NONE, NONE, NONE} },
144 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 176 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
145 SGMII_FM1_DTSEC3, AURORA, 177 SGMII_FM1_DTSEC3, AURORA,
146 NONE, NONE, NONE, NONE} }, 178 NONE, NONE, NONE, NONE} },
147 {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 179 {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
148 AURORA, AURORA, NONE, NONE, NONE, NONE} }, 180 AURORA, AURORA, NONE, NONE, NONE, NONE} },
149 {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 181 {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
150 AURORA, AURORA, NONE, NONE, NONE, NONE} }, 182 AURORA, AURORA, NONE, NONE, NONE, NONE} },
151 {0x9A, {PCIE1, PCIE1, 183 {0x9A, {PCIE1, PCIE1,
152 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 184 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
153 NONE, NONE, NONE, NONE} }, 185 NONE, NONE, NONE, NONE} },
154 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, 186 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
155 NONE, NONE, NONE, NONE} }, 187 NONE, NONE, NONE, NONE} },
156 {} 188 {}
157 }; 189 };
158 #endif 190 #endif
159 191
160 static struct serdes_config *serdes_cfg_tbl[] = { 192 static struct serdes_config *serdes_cfg_tbl[] = {
161 serdes1_cfg_tbl, 193 serdes1_cfg_tbl,
162 serdes2_cfg_tbl, 194 serdes2_cfg_tbl,
163 }; 195 };
164 196
165 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 197 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
166 { 198 {
167 struct serdes_config *ptr; 199 struct serdes_config *ptr;
168 200
169 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 201 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
170 return 0; 202 return 0;
171 203
172 ptr = serdes_cfg_tbl[serdes]; 204 ptr = serdes_cfg_tbl[serdes];
173 while (ptr->protocol) { 205 while (ptr->protocol) {
174 if (ptr->protocol == cfg) 206 if (ptr->protocol == cfg)
175 return ptr->lanes[lane]; 207 return ptr->lanes[lane];
176 ptr++; 208 ptr++;
177 } 209 }
178 210
179 return 0; 211 return 0;
180 } 212 }
181 213
182 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 214 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
183 { 215 {
184 int i; 216 int i;
185 struct serdes_config *ptr; 217 struct serdes_config *ptr;
186 218
187 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 219 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
188 return 0; 220 return 0;
189 221
190 ptr = serdes_cfg_tbl[serdes]; 222 ptr = serdes_cfg_tbl[serdes];
191 while (ptr->protocol) { 223 while (ptr->protocol) {
192 if (ptr->protocol == prtcl) 224 if (ptr->protocol == prtcl)
193 break; 225 break;
194 ptr++; 226 ptr++;
195 } 227 }
196 228
197 if (!ptr->protocol) 229 if (!ptr->protocol)
198 return 0; 230 return 0;
199 231
200 for (i = 0; i < SRDS_MAX_LANES; i++) { 232 for (i = 0; i < SRDS_MAX_LANES; i++) {
201 if (ptr->lanes[i] != NONE) 233 if (ptr->lanes[i] != NONE)
202 return 1; 234 return 1;
203 } 235 }
204 236
205 return 0; 237 return 0;
206 } 238 }
207 239
board/freescale/b4860qds/b4860qds.c
Diff comments   View file @ 5e5097c
1 /* 1 /*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <command.h> 8 #include <command.h>
9 #include <i2c.h> 9 #include <i2c.h>
10 #include <netdev.h> 10 #include <netdev.h>
11 #include <linux/compiler.h> 11 #include <linux/compiler.h>
12 #include <asm/mmu.h> 12 #include <asm/mmu.h>
13 #include <asm/processor.h> 13 #include <asm/processor.h>
14 #include <asm/cache.h> 14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h> 15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h> 16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h> 17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h> 18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h> 19 #include <asm/fsl_liodn.h>
20 #include <fm_eth.h> 20 #include <fm_eth.h>
21 21
22 #include "../common/qixis.h" 22 #include "../common/qixis.h"
23 #include "../common/vsc3316_3308.h" 23 #include "../common/vsc3316_3308.h"
24 #include "../common/idt8t49n222a_serdes_clk.h" 24 #include "../common/idt8t49n222a_serdes_clk.h"
25 #include "b4860qds.h" 25 #include "b4860qds.h"
26 #include "b4860qds_qixis.h" 26 #include "b4860qds_qixis.h"
27 #include "b4860qds_crossbar_con.h" 27 #include "b4860qds_crossbar_con.h"
28 28
29 #define CLK_MUX_SEL_MASK 0x4 29 #define CLK_MUX_SEL_MASK 0x4
30 #define ETH_PHY_CLK_OUT 0x4 30 #define ETH_PHY_CLK_OUT 0x4
31 #define PLL_NUM 2 31 #define PLL_NUM 2
32 32
33 DECLARE_GLOBAL_DATA_PTR; 33 DECLARE_GLOBAL_DATA_PTR;
34 34
35 int checkboard(void) 35 int checkboard(void)
36 { 36 {
37 char buf[64]; 37 char buf[64];
38 u8 sw; 38 u8 sw;
39 struct cpu_type *cpu = gd->arch.cpu; 39 struct cpu_type *cpu = gd->arch.cpu;
40 static const char *const freq[] = {"100", "125", "156.25", "161.13", 40 static const char *const freq[] = {"100", "125", "156.25", "161.13",
41 "122.88", "122.88", "122.88"}; 41 "122.88", "122.88", "122.88"};
42 int clock; 42 int clock;
43 43
44 printf("Board: %sQDS, ", cpu->name); 44 printf("Board: %sQDS, ", cpu->name);
45 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", 45 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
46 QIXIS_READ(id), QIXIS_READ(arch)); 46 QIXIS_READ(id), QIXIS_READ(arch));
47 47
48 sw = QIXIS_READ(brdcfg[0]); 48 sw = QIXIS_READ(brdcfg[0]);
49 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 49 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
50 50
51 if (sw < 0x8) 51 if (sw < 0x8)
52 printf("vBank: %d\n", sw); 52 printf("vBank: %d\n", sw);
53 else if (sw >= 0x8 && sw <= 0xE) 53 else if (sw >= 0x8 && sw <= 0xE)
54 puts("NAND\n"); 54 puts("NAND\n");
55 else 55 else
56 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 56 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
57 57
58 printf("FPGA: v%d (%s), build %d", 58 printf("FPGA: v%d (%s), build %d",
59 (int)QIXIS_READ(scver), qixis_read_tag(buf), 59 (int)QIXIS_READ(scver), qixis_read_tag(buf),
60 (int)qixis_read_minor()); 60 (int)qixis_read_minor());
61 /* the timestamp string contains "\n" at the end */ 61 /* the timestamp string contains "\n" at the end */
62 printf(" on %s", qixis_read_time(buf)); 62 printf(" on %s", qixis_read_time(buf));
63 63
64 /* 64 /*
65 * Display the actual SERDES reference clocks as configured by the 65 * Display the actual SERDES reference clocks as configured by the
66 * dip switches on the board. Note that the SWx registers could 66 * dip switches on the board. Note that the SWx registers could
67 * technically be set to force the reference clocks to match the 67 * technically be set to force the reference clocks to match the
68 * values that the SERDES expects (or vice versa). For now, however, 68 * values that the SERDES expects (or vice versa). For now, however,
69 * we just display both values and hope the user notices when they 69 * we just display both values and hope the user notices when they
70 * don't match. 70 * don't match.
71 */ 71 */
72 puts("SERDES Reference Clocks: "); 72 puts("SERDES Reference Clocks: ");
73 sw = QIXIS_READ(brdcfg[2]); 73 sw = QIXIS_READ(brdcfg[2]);
74 clock = (sw >> 5) & 7; 74 clock = (sw >> 5) & 7;
75 printf("Bank1=%sMHz ", freq[clock]); 75 printf("Bank1=%sMHz ", freq[clock]);
76 sw = QIXIS_READ(brdcfg[4]); 76 sw = QIXIS_READ(brdcfg[4]);
77 clock = (sw >> 6) & 3; 77 clock = (sw >> 6) & 3;
78 printf("Bank2=%sMHz\n", freq[clock]); 78 printf("Bank2=%sMHz\n", freq[clock]);
79 79
80 return 0; 80 return 0;
81 } 81 }
82 82
83 int select_i2c_ch_pca(u8 ch) 83 int select_i2c_ch_pca(u8 ch)
84 { 84 {
85 int ret; 85 int ret;
86 86
87 /* Selecting proper channel via PCA*/ 87 /* Selecting proper channel via PCA*/
88 ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1); 88 ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
89 if (ret) { 89 if (ret) {
90 printf("PCA: failed to select proper channel.\n"); 90 printf("PCA: failed to select proper channel.\n");
91 return ret; 91 return ret;
92 } 92 }
93 93
94 return 0; 94 return 0;
95 } 95 }
96 96
97 int configure_vsc3316_3308(void) 97 int configure_vsc3316_3308(void)
98 { 98 {
99 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 99 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
100 unsigned int num_vsc16_con, num_vsc08_con; 100 unsigned int num_vsc16_con, num_vsc08_con;
101 u32 serdes1_prtcl, serdes2_prtcl; 101 u32 serdes1_prtcl, serdes2_prtcl;
102 int ret; 102 int ret;
103 103
104 serdes1_prtcl = in_be32(&gur->rcwsr[4]) & 104 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
105 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 105 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
106 if (!serdes1_prtcl) { 106 if (!serdes1_prtcl) {
107 printf("SERDES1 is not enabled\n"); 107 printf("SERDES1 is not enabled\n");
108 return 0; 108 return 0;
109 } 109 }
110 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 110 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
111 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); 111 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
112 112
113 serdes2_prtcl = in_be32(&gur->rcwsr[4]) & 113 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
114 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 114 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
115 if (!serdes2_prtcl) { 115 if (!serdes2_prtcl) {
116 printf("SERDES2 is not enabled\n"); 116 printf("SERDES2 is not enabled\n");
117 return 0; 117 return 0;
118 } 118 }
119 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 119 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
120 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); 120 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
121 121
122 switch (serdes1_prtcl) { 122 switch (serdes1_prtcl) {
123 case 0x2a: 123 case 0x2a:
124 case 0x2C: 124 case 0x2C:
125 case 0x2D: 125 case 0x2D:
126 case 0x2E: 126 case 0x2E:
127 /* 127 /*
128 * Configuration: 128 * Configuration:
129 * SERDES: 1 129 * SERDES: 1
130 * Lanes: A,B: SGMII 130 * Lanes: A,B: SGMII
131 * Lanes: C,D,E,F,G,H: CPRI 131 * Lanes: C,D,E,F,G,H: CPRI
132 */ 132 */
133 debug("Configuring crossbar to use onboard SGMII PHYs:" 133 debug("Configuring crossbar to use onboard SGMII PHYs:"
134 "srds_prctl:%x\n", serdes1_prtcl); 134 "srds_prctl:%x\n", serdes1_prtcl);
135 num_vsc16_con = NUM_CON_VSC3316; 135 num_vsc16_con = NUM_CON_VSC3316;
136 /* Configure VSC3316 crossbar switch */ 136 /* Configure VSC3316 crossbar switch */
137 ret = select_i2c_ch_pca(I2C_CH_VSC3316); 137 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
138 if (!ret) { 138 if (!ret) {
139 ret = vsc3316_config(VSC3316_TX_ADDRESS, 139 ret = vsc3316_config(VSC3316_TX_ADDRESS,
140 vsc16_tx_4sfp_sgmii_12_56, 140 vsc16_tx_4sfp_sgmii_12_56,
141 num_vsc16_con); 141 num_vsc16_con);
142 if (ret) 142 if (ret)
143 return ret; 143 return ret;
144 ret = vsc3316_config(VSC3316_RX_ADDRESS, 144 ret = vsc3316_config(VSC3316_RX_ADDRESS,
145 vsc16_rx_4sfp_sgmii_12_56, 145 vsc16_rx_4sfp_sgmii_12_56,
146 num_vsc16_con); 146 num_vsc16_con);
147 if (ret) 147 if (ret)
148 return ret; 148 return ret;
149 } else { 149 } else {
150 return ret; 150 return ret;
151 } 151 }
152 break; 152 break;
153 153
154 case 0x02:
155 case 0x04:
156 case 0x05:
157 case 0x06:
158 case 0x08:
159 case 0x09:
160 case 0x0A:
161 case 0x0B:
162 case 0x0C:
163 case 0x30:
164 case 0x32:
165 case 0x33:
166 case 0x34:
167 case 0x39:
168 case 0x3A:
169 case 0x3C:
170 case 0x3D:
171 case 0x5C:
172 case 0x5D:
173 /*
174 * Configuration:
175 * SERDES: 1
176 * Lanes: A,B: AURORA
177 * Lanes: C,d: SGMII
178 * Lanes: E,F,G,H: CPRI
179 */
180 debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
181 " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
182 num_vsc16_con = NUM_CON_VSC3316;
183 /* Configure VSC3316 crossbar switch */
184 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
185 if (!ret) {
186 ret = vsc3316_config(VSC3316_TX_ADDRESS,
187 vsc16_tx_sfp_sgmii_aurora,
188 num_vsc16_con);
189 if (ret)
190 return ret;
191 ret = vsc3316_config(VSC3316_RX_ADDRESS,
192 vsc16_rx_sfp_sgmii_aurora,
193 num_vsc16_con);
194 if (ret)
195 return ret;
196 } else {
197 return ret;
198 }
199 break;
200
154 #ifdef CONFIG_PPC_B4420 201 #ifdef CONFIG_PPC_B4420
155 case 0x18: 202 case 0x18:
156 /* 203 /*
157 * Configuration: 204 * Configuration:
158 * SERDES: 1 205 * SERDES: 1
159 * Lanes: A,B,C,D: SGMII 206 * Lanes: A,B,C,D: SGMII
160 * Lanes: E,F,G,H: CPRI 207 * Lanes: E,F,G,H: CPRI
161 */ 208 */
162 debug("Configuring crossbar to use onboard SGMII PHYs:" 209 debug("Configuring crossbar to use onboard SGMII PHYs:"
163 "srds_prctl:%x\n", serdes1_prtcl); 210 "srds_prctl:%x\n", serdes1_prtcl);
164 num_vsc16_con = NUM_CON_VSC3316; 211 num_vsc16_con = NUM_CON_VSC3316;
165 /* Configure VSC3316 crossbar switch */ 212 /* Configure VSC3316 crossbar switch */
166 ret = select_i2c_ch_pca(I2C_CH_VSC3316); 213 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
167 if (!ret) { 214 if (!ret) {
168 ret = vsc3316_config(VSC3316_TX_ADDRESS, 215 ret = vsc3316_config(VSC3316_TX_ADDRESS,
169 vsc16_tx_sgmii_lane_cd, num_vsc16_con); 216 vsc16_tx_sgmii_lane_cd, num_vsc16_con);
170 if (ret) 217 if (ret)
171 return ret; 218 return ret;
172 ret = vsc3316_config(VSC3316_RX_ADDRESS, 219 ret = vsc3316_config(VSC3316_RX_ADDRESS,
173 vsc16_rx_sgmii_lane_cd, num_vsc16_con); 220 vsc16_rx_sgmii_lane_cd, num_vsc16_con);
174 if (ret) 221 if (ret)
175 return ret; 222 return ret;
176 } else { 223 } else {
177 return ret; 224 return ret;
178 } 225 }
179 break; 226 break;
180 #endif 227 #endif
181 228
182 case 0x3E: 229 case 0x3E:
183 case 0x0D: 230 case 0x0D:
184 case 0x0E: 231 case 0x0E:
185 case 0x12: 232 case 0x12:
186 num_vsc16_con = NUM_CON_VSC3316; 233 num_vsc16_con = NUM_CON_VSC3316;
187 /* Configure VSC3316 crossbar switch */ 234 /* Configure VSC3316 crossbar switch */
188 ret = select_i2c_ch_pca(I2C_CH_VSC3316); 235 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
189 if (!ret) { 236 if (!ret) {
190 ret = vsc3316_config(VSC3316_TX_ADDRESS, 237 ret = vsc3316_config(VSC3316_TX_ADDRESS,
191 vsc16_tx_sfp, num_vsc16_con); 238 vsc16_tx_sfp, num_vsc16_con);
192 if (ret) 239 if (ret)
193 return ret; 240 return ret;
194 ret = vsc3316_config(VSC3316_RX_ADDRESS, 241 ret = vsc3316_config(VSC3316_RX_ADDRESS,
195 vsc16_rx_sfp, num_vsc16_con); 242 vsc16_rx_sfp, num_vsc16_con);
196 if (ret) 243 if (ret)
197 return ret; 244 return ret;
198 } else { 245 } else {
199 return ret; 246 return ret;
200 } 247 }
201 break; 248 break;
202 default: 249 default:
203 printf("WARNING:VSC crossbars programming not supported for:%x" 250 printf("WARNING:VSC crossbars programming not supported for:%x"
204 " SerDes1 Protocol.\n", serdes1_prtcl); 251 " SerDes1 Protocol.\n", serdes1_prtcl);
205 return -1; 252 return -1;
206 } 253 }
207 254
208 switch (serdes2_prtcl) { 255 switch (serdes2_prtcl) {
209 case 0x9E: 256 case 0x9E:
210 case 0x9A: 257 case 0x9A:
211 case 0x98: 258 case 0x98:
212 case 0xb2: 259 case 0xb2:
213 case 0x49: 260 case 0x49:
214 case 0x4E: 261 case 0x4E:
215 case 0x8D: 262 case 0x8D:
216 case 0x7A: 263 case 0x7A:
217 num_vsc08_con = NUM_CON_VSC3308; 264 num_vsc08_con = NUM_CON_VSC3308;
218 /* Configure VSC3308 crossbar switch */ 265 /* Configure VSC3308 crossbar switch */
219 ret = select_i2c_ch_pca(I2C_CH_VSC3308); 266 ret = select_i2c_ch_pca(I2C_CH_VSC3308);
220 if (!ret) { 267 if (!ret) {
221 ret = vsc3308_config(VSC3308_TX_ADDRESS, 268 ret = vsc3308_config(VSC3308_TX_ADDRESS,
222 vsc08_tx_amc, num_vsc08_con); 269 vsc08_tx_amc, num_vsc08_con);
223 if (ret) 270 if (ret)
224 return ret; 271 return ret;
225 ret = vsc3308_config(VSC3308_RX_ADDRESS, 272 ret = vsc3308_config(VSC3308_RX_ADDRESS,
226 vsc08_rx_amc, num_vsc08_con); 273 vsc08_rx_amc, num_vsc08_con);
227 if (ret) 274 if (ret)
228 return ret; 275 return ret;
229 } else { 276 } else {
230 return ret; 277 return ret;
231 } 278 }
232 break; 279 break;
233 default: 280 default:
234 printf("WARNING:VSC crossbars programming not supported for: %x" 281 printf("WARNING:VSC crossbars programming not supported for: %x"
235 " SerDes2 Protocol.\n", serdes2_prtcl); 282 " SerDes2 Protocol.\n", serdes2_prtcl);
236 return -1; 283 return -1;
237 } 284 }
238 285
239 return 0; 286 return 0;
240 } 287 }
241 288
242 int config_serdes1_refclks(void) 289 int config_serdes1_refclks(void)
243 { 290 {
244 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 291 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
245 serdes_corenet_t *srds_regs = 292 serdes_corenet_t *srds_regs =
246 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 293 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
247 u32 serdes1_prtcl, lane; 294 u32 serdes1_prtcl, lane;
248 unsigned int flag_sgmii_prtcl = 0; 295 unsigned int flag_sgmii_aurora_prtcl = 0;
249 int ret, i; 296 int ret, i;
250 297
251 serdes1_prtcl = in_be32(&gur->rcwsr[4]) & 298 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
252 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 299 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
253 if (!serdes1_prtcl) { 300 if (!serdes1_prtcl) {
254 printf("SERDES1 is not enabled\n"); 301 printf("SERDES1 is not enabled\n");
255 return -1; 302 return -1;
256 } 303 }
257 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 304 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
258 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); 305 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
259 306
260 /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks 307 /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks
261 */ 308 */
262 for (i = 0; i < PLL_NUM; i++) 309 for (i = 0; i < PLL_NUM; i++)
263 clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST); 310 clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST);
264 /* Reconfigure IDT idt8t49n222a device for CPRI to work 311 /* Reconfigure IDT idt8t49n222a device for CPRI to work
265 * For this SerDes1's Refclk1 and refclk2 need to be set 312 * For this SerDes1's Refclk1 and refclk2 need to be set
266 * to 122.88MHz 313 * to 122.88MHz
267 */ 314 */
268 switch (serdes1_prtcl) { 315 switch (serdes1_prtcl) {
269 case 0x2A: 316 case 0x2A:
270 case 0x2C: 317 case 0x2C:
271 case 0x2D: 318 case 0x2D:
272 case 0x2E: 319 case 0x2E:
320 case 0x02:
321 case 0x04:
322 case 0x05:
323 case 0x06:
324 case 0x08:
325 case 0x09:
326 case 0x0A:
327 case 0x0B:
328 case 0x0C:
329 case 0x30:
330 case 0x32:
331 case 0x33:
332 case 0x34:
333 case 0x39:
334 case 0x3A:
335 case 0x3C:
336 case 0x3D:
337 case 0x5C:
338 case 0x5D:
273 debug("Configuring idt8t49n222a for CPRI SerDes clks:" 339 debug("Configuring idt8t49n222a for CPRI SerDes clks:"
274 " for srds_prctl:%x\n", serdes1_prtcl); 340 " for srds_prctl:%x\n", serdes1_prtcl);
275 ret = select_i2c_ch_pca(I2C_CH_IDT); 341 ret = select_i2c_ch_pca(I2C_CH_IDT);
276 if (!ret) { 342 if (!ret) {
277 ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1, 343 ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
278 SERDES_REFCLK_122_88, 344 SERDES_REFCLK_122_88,
279 SERDES_REFCLK_122_88, 0); 345 SERDES_REFCLK_122_88, 0);
280 if (ret) { 346 if (ret) {
281 printf("IDT8T49N222A configuration failed.\n"); 347 printf("IDT8T49N222A configuration failed.\n");
282 return ret; 348 return ret;
283 } else 349 } else
284 printf("IDT8T49N222A configured.\n"); 350 printf("IDT8T49N222A configured.\n");
285 } else { 351 } else {
286 return ret; 352 return ret;
287 } 353 }
288 select_i2c_ch_pca(I2C_CH_DEFAULT); 354 select_i2c_ch_pca(I2C_CH_DEFAULT);
289 355
290 /* Change SerDes1's Refclk1 to 125MHz for on board 356 /* Change SerDes1's Refclk1 to 125MHz for on board
291 * SGMIIs to work 357 * SGMIIs or Aurora to work
292 */ 358 */
293 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 359 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
294 enum srds_prtcl lane_prtcl = serdes_get_prtcl 360 enum srds_prtcl lane_prtcl = serdes_get_prtcl
295 (0, serdes1_prtcl, lane); 361 (0, serdes1_prtcl, lane);
296 switch (lane_prtcl) { 362 switch (lane_prtcl) {
297 case SGMII_FM1_DTSEC1: 363 case SGMII_FM1_DTSEC1:
298 case SGMII_FM1_DTSEC2: 364 case SGMII_FM1_DTSEC2:
299 case SGMII_FM1_DTSEC3: 365 case SGMII_FM1_DTSEC3:
300 case SGMII_FM1_DTSEC4: 366 case SGMII_FM1_DTSEC4:
301 case SGMII_FM1_DTSEC5: 367 case SGMII_FM1_DTSEC5:
302 case SGMII_FM1_DTSEC6: 368 case SGMII_FM1_DTSEC6:
303 flag_sgmii_prtcl++; 369 case AURORA:
370 flag_sgmii_aurora_prtcl++;
304 break; 371 break;
305 default: 372 default:
306 break; 373 break;
307 } 374 }
308 } 375 }
309 376
310 if (flag_sgmii_prtcl) 377 if (flag_sgmii_aurora_prtcl)
311 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); 378 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
312 379
313 /* Steps For SerDes PLLs reset and reconfiguration after 380 /* Steps For SerDes PLLs reset and reconfiguration after
314 * changing SerDes's refclks 381 * changing SerDes's refclks
315 */ 382 */
316 for (i = 0; i < PLL_NUM; i++) { 383 for (i = 0; i < PLL_NUM; i++) {
317 debug("For PLL%d reset and reconfiguration after" 384 debug("For PLL%d reset and reconfiguration after"
318 " changing refclks\n", i+1); 385 " changing refclks\n", i+1);
319 clrbits_be32(&srds_regs->bank[i].rstctl, 386 clrbits_be32(&srds_regs->bank[i].rstctl,
320 SRDS_RSTCTL_SDRST_B); 387 SRDS_RSTCTL_SDRST_B);
321 udelay(10); 388 udelay(10);
322 clrbits_be32(&srds_regs->bank[i].rstctl, 389 clrbits_be32(&srds_regs->bank[i].rstctl,
323 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); 390 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
324 udelay(10); 391 udelay(10);
325 setbits_be32(&srds_regs->bank[i].rstctl, 392 setbits_be32(&srds_regs->bank[i].rstctl,
326 SRDS_RSTCTL_RST); 393 SRDS_RSTCTL_RST);
327 setbits_be32(&srds_regs->bank[i].rstctl, 394 setbits_be32(&srds_regs->bank[i].rstctl,
328 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B 395 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
329 | SRDS_RSTCTL_SDRST_B)); 396 | SRDS_RSTCTL_SDRST_B));
330 } 397 }
331 break; 398 break;
332 default: 399 default:
333 printf("WARNING:IDT8T49N222A configuration not" 400 printf("WARNING:IDT8T49N222A configuration not"
334 " supported for:%x SerDes1 Protocol.\n", 401 " supported for:%x SerDes1 Protocol.\n",
335 serdes1_prtcl); 402 serdes1_prtcl);
336 return -1; 403 return -1;
337 } 404 }
338 405
339 return 0; 406 return 0;
340 } 407 }
341 408
342 int board_early_init_r(void) 409 int board_early_init_r(void)
343 { 410 {
344 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 411 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
345 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 412 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
346 413
347 /* 414 /*
348 * Remap Boot flash + PROMJET region to caching-inhibited 415 * Remap Boot flash + PROMJET region to caching-inhibited
349 * so that flash can be erased properly. 416 * so that flash can be erased properly.
350 */ 417 */
351 418
352 /* Flush d-cache and invalidate i-cache of any FLASH data */ 419 /* Flush d-cache and invalidate i-cache of any FLASH data */
353 flush_dcache(); 420 flush_dcache();
354 invalidate_icache(); 421 invalidate_icache();
355 422
356 /* invalidate existing TLB entry for flash + promjet */ 423 /* invalidate existing TLB entry for flash + promjet */
357 disable_tlb(flash_esel); 424 disable_tlb(flash_esel);
358 425
359 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 426 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
360 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 427 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
361 0, flash_esel, BOOKE_PAGESZ_256M, 1); 428 0, flash_esel, BOOKE_PAGESZ_256M, 1);
362 429
363 set_liodns(); 430 set_liodns();
364 #ifdef CONFIG_SYS_DPAA_QBMAN 431 #ifdef CONFIG_SYS_DPAA_QBMAN
365 setup_portals(); 432 setup_portals();
366 #endif 433 #endif
367 /* SerDes1 refclks need to be set again, as default clks 434 /* SerDes1 refclks need to be set again, as default clks
368 * are not suitable for CPRI and onboard SGMIIs to work 435 * are not suitable for CPRI and onboard SGMIIs to work
369 * simultaneously. 436 * simultaneously.
370 * This function will set SerDes1's Refclk1 and refclk2 437 * This function will set SerDes1's Refclk1 and refclk2
371 * as per SerDes1 protocols 438 * as per SerDes1 protocols
372 */ 439 */
373 if (config_serdes1_refclks()) 440 if (config_serdes1_refclks())
374 printf("SerDes1 Refclks couldn't set properly.\n"); 441 printf("SerDes1 Refclks couldn't set properly.\n");
375 else 442 else
376 printf("SerDes1 Refclks have been set.\n"); 443 printf("SerDes1 Refclks have been set.\n");
377 444
378 /* Configure VSC3316 and VSC3308 crossbar switches */ 445 /* Configure VSC3316 and VSC3308 crossbar switches */
379 if (configure_vsc3316_3308()) 446 if (configure_vsc3316_3308())
380 printf("VSC:failed to configure VSC3316/3308.\n"); 447 printf("VSC:failed to configure VSC3316/3308.\n");
381 else 448 else
382 printf("VSC:VSC3316/3308 successfully configured.\n"); 449 printf("VSC:VSC3316/3308 successfully configured.\n");
383 450
384 select_i2c_ch_pca(I2C_CH_DEFAULT); 451 select_i2c_ch_pca(I2C_CH_DEFAULT);
385 452
386 return 0; 453 return 0;
387 } 454 }
388 455
389 unsigned long get_board_sys_clk(void) 456 unsigned long get_board_sys_clk(void)
390 { 457 {
391 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 458 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
392 459
393 switch ((sysclk_conf & 0x0C) >> 2) { 460 switch ((sysclk_conf & 0x0C) >> 2) {
394 case QIXIS_CLK_100: 461 case QIXIS_CLK_100:
395 return 100000000; 462 return 100000000;
396 case QIXIS_CLK_125: 463 case QIXIS_CLK_125:
397 return 125000000; 464 return 125000000;
398 case QIXIS_CLK_133: 465 case QIXIS_CLK_133:
399 return 133333333; 466 return 133333333;
400 } 467 }
401 return 66666666; 468 return 66666666;
402 } 469 }
403 470
404 unsigned long get_board_ddr_clk(void) 471 unsigned long get_board_ddr_clk(void)
405 { 472 {
406 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 473 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
407 474
408 switch (ddrclk_conf & 0x03) { 475 switch (ddrclk_conf & 0x03) {
409 case QIXIS_CLK_100: 476 case QIXIS_CLK_100:
410 return 100000000; 477 return 100000000;
411 case QIXIS_CLK_125: 478 case QIXIS_CLK_125:
412 return 125000000; 479 return 125000000;
413 case QIXIS_CLK_133: 480 case QIXIS_CLK_133:
414 return 133333333; 481 return 133333333;
415 } 482 }
416 return 66666666; 483 return 66666666;
417 } 484 }
418 485
419 static int serdes_refclock(u8 sw, u8 sdclk) 486 static int serdes_refclock(u8 sw, u8 sdclk)
420 { 487 {
421 unsigned int clock; 488 unsigned int clock;
422 int ret = -1; 489 int ret = -1;
423 u8 brdcfg4; 490 u8 brdcfg4;
424 491
425 if (sdclk == 1) { 492 if (sdclk == 1) {
426 brdcfg4 = QIXIS_READ(brdcfg[4]); 493 brdcfg4 = QIXIS_READ(brdcfg[4]);
427 if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT) 494 if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
428 return SRDS_PLLCR0_RFCK_SEL_125; 495 return SRDS_PLLCR0_RFCK_SEL_125;
429 else 496 else
430 clock = (sw >> 5) & 7; 497 clock = (sw >> 5) & 7;
431 } else 498 } else
432 clock = (sw >> 6) & 3; 499 clock = (sw >> 6) & 3;
433 500
434 switch (clock) { 501 switch (clock) {
435 case 0: 502 case 0:
436 ret = SRDS_PLLCR0_RFCK_SEL_100; 503 ret = SRDS_PLLCR0_RFCK_SEL_100;
437 break; 504 break;
438 case 1: 505 case 1:
439 ret = SRDS_PLLCR0_RFCK_SEL_125; 506 ret = SRDS_PLLCR0_RFCK_SEL_125;
440 break; 507 break;
441 case 2: 508 case 2:
442 ret = SRDS_PLLCR0_RFCK_SEL_156_25; 509 ret = SRDS_PLLCR0_RFCK_SEL_156_25;
443 break; 510 break;
444 case 3: 511 case 3:
445 ret = SRDS_PLLCR0_RFCK_SEL_161_13; 512 ret = SRDS_PLLCR0_RFCK_SEL_161_13;
446 break; 513 break;
447 case 4: 514 case 4:
448 case 5: 515 case 5:
449 case 6: 516 case 6:
450 ret = SRDS_PLLCR0_RFCK_SEL_122_88; 517 ret = SRDS_PLLCR0_RFCK_SEL_122_88;
451 break; 518 break;
452 default: 519 default:
453 ret = -1; 520 ret = -1;
454 break; 521 break;
455 } 522 }
456 523
457 return ret; 524 return ret;
458 } 525 }
459 526
460 #define NUM_SRDS_BANKS 2 527 #define NUM_SRDS_BANKS 2
461 528
462 int misc_init_r(void) 529 int misc_init_r(void)
463 { 530 {
464 u8 sw; 531 u8 sw;
465 serdes_corenet_t *srds_regs = 532 serdes_corenet_t *srds_regs =
466 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 533 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
467 u32 actual[NUM_SRDS_BANKS]; 534 u32 actual[NUM_SRDS_BANKS];
468 unsigned int i; 535 unsigned int i;
469 int clock; 536 int clock;
470 537
471 sw = QIXIS_READ(brdcfg[2]); 538 sw = QIXIS_READ(brdcfg[2]);
472 clock = serdes_refclock(sw, 1); 539 clock = serdes_refclock(sw, 1);
473 if (clock >= 0) 540 if (clock >= 0)
474 actual[0] = clock; 541 actual[0] = clock;
475 else 542 else
476 printf("Warning: SDREFCLK1 switch setting is unsupported\n"); 543 printf("Warning: SDREFCLK1 switch setting is unsupported\n");
477 544
478 sw = QIXIS_READ(brdcfg[4]); 545 sw = QIXIS_READ(brdcfg[4]);
479 clock = serdes_refclock(sw, 2); 546 clock = serdes_refclock(sw, 2);
480 if (clock >= 0) 547 if (clock >= 0)
481 actual[1] = clock; 548 actual[1] = clock;
482 else 549 else
483 printf("Warning: SDREFCLK2 switch setting unsupported\n"); 550 printf("Warning: SDREFCLK2 switch setting unsupported\n");
484 551
485 for (i = 0; i < NUM_SRDS_BANKS; i++) { 552 for (i = 0; i < NUM_SRDS_BANKS; i++) {
486 u32 pllcr0 = srds_regs->bank[i].pllcr0; 553 u32 pllcr0 = srds_regs->bank[i].pllcr0;
487 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 554 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
488 if (expected != actual[i]) { 555 if (expected != actual[i]) {
489 printf("Warning: SERDES bank %u expects reference clock" 556 printf("Warning: SERDES bank %u expects reference clock"
490 " %sMHz, but actual is %sMHz\n", i + 1, 557 " %sMHz, but actual is %sMHz\n", i + 1,
491 serdes_clock_to_string(expected), 558 serdes_clock_to_string(expected),
492 serdes_clock_to_string(actual[i])); 559 serdes_clock_to_string(actual[i]));
493 } 560 }
494 } 561 }
495 562
496 return 0; 563 return 0;
497 } 564 }
498 565
499 void ft_board_setup(void *blob, bd_t *bd) 566 void ft_board_setup(void *blob, bd_t *bd)
500 { 567 {
501 phys_addr_t base; 568 phys_addr_t base;
502 phys_size_t size; 569 phys_size_t size;
503 570
504 ft_cpu_setup(blob, bd); 571 ft_cpu_setup(blob, bd);
505 572
506 base = getenv_bootm_low(); 573 base = getenv_bootm_low();
507 size = getenv_bootm_size(); 574 size = getenv_bootm_size();
508 575
509 fdt_fixup_memory(blob, (u64)base, (u64)size); 576 fdt_fixup_memory(blob, (u64)base, (u64)size);
510 577
511 #ifdef CONFIG_PCI 578 #ifdef CONFIG_PCI
512 pci_of_setup(blob, bd); 579 pci_of_setup(blob, bd);
513 #endif 580 #endif
514 581
515 fdt_fixup_liodn(blob); 582 fdt_fixup_liodn(blob);
516 583
517 #ifdef CONFIG_HAS_FSL_DR_USB 584 #ifdef CONFIG_HAS_FSL_DR_USB
518 fdt_fixup_dr_usb(blob, bd); 585 fdt_fixup_dr_usb(blob, bd);
519 #endif 586 #endif
520 587
521 #ifdef CONFIG_SYS_DPAA_FMAN 588 #ifdef CONFIG_SYS_DPAA_FMAN
522 fdt_fixup_fman_ethernet(blob); 589 fdt_fixup_fman_ethernet(blob);
523 fdt_fixup_board_enet(blob); 590 fdt_fixup_board_enet(blob);
524 #endif 591 #endif
525 } 592 }
526 593
527 /* 594 /*
528 * Dump board switch settings. 595 * Dump board switch settings.
529 * The bits that cannot be read/sampled via some FPGA or some 596 * The bits that cannot be read/sampled via some FPGA or some
530 * registers, they will be displayed as 597 * registers, they will be displayed as
531 * underscore in binary format. mask[] has those bits. 598 * underscore in binary format. mask[] has those bits.
532 * Some bits are calculated differently than the actual switches 599 * Some bits are calculated differently than the actual switches
533 * if booting with overriding by FPGA. 600 * if booting with overriding by FPGA.
534 */ 601 */
535 void qixis_dump_switch(void) 602 void qixis_dump_switch(void)
536 { 603 {
537 int i; 604 int i;
538 u8 sw[5]; 605 u8 sw[5];
539 606
540 /* 607 /*
541 * Any bit with 1 means that bit cannot be reverse engineered. 608 * Any bit with 1 means that bit cannot be reverse engineered.
542 * It will be displayed as _ in binary format. 609 * It will be displayed as _ in binary format.
543 */ 610 */
544 static const u8 mask[] = {0x07, 0, 0, 0xff, 0}; 611 static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
545 char buf[10]; 612 char buf[10];
546 u8 brdcfg[16], dutcfg[16]; 613 u8 brdcfg[16], dutcfg[16];
547 614
548 for (i = 0; i < 16; i++) { 615 for (i = 0; i < 16; i++) {
549 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); 616 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
550 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); 617 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
551 } 618 }
552 619
553 sw[0] = ((brdcfg[0] & 0x0f) << 4) | \ 620 sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
554 (brdcfg[9] & 0x08); 621 (brdcfg[9] & 0x08);
555 sw[1] = ((dutcfg[1] & 0x01) << 7) | \ 622 sw[1] = ((dutcfg[1] & 0x01) << 7) | \
556 ((dutcfg[2] & 0x07) << 4) | \ 623 ((dutcfg[2] & 0x07) << 4) | \
557 ((dutcfg[6] & 0x10) >> 1) | \ 624 ((dutcfg[6] & 0x10) >> 1) | \
558 ((dutcfg[6] & 0x80) >> 5) | \ 625 ((dutcfg[6] & 0x80) >> 5) | \
559 ((dutcfg[1] & 0x40) >> 5) | \ 626 ((dutcfg[1] & 0x40) >> 5) | \
560 (dutcfg[6] & 0x01); 627 (dutcfg[6] & 0x01);
561 sw[2] = dutcfg[0]; 628 sw[2] = dutcfg[0];
562 sw[3] = 0; 629 sw[3] = 0;
563 sw[4] = ((brdcfg[1] & 0x30) << 2) | \ 630 sw[4] = ((brdcfg[1] & 0x30) << 2) | \
564 ((brdcfg[1] & 0xc0) >> 2) | \ 631 ((brdcfg[1] & 0xc0) >> 2) | \
565 (brdcfg[1] & 0x0f); 632 (brdcfg[1] & 0x0f);
566 633
567 puts("DIP switch settings:\n"); 634 puts("DIP switch settings:\n");
568 for (i = 0; i < 5; i++) { 635 for (i = 0; i < 5; i++) {
569 printf("SW%d = 0b%s (0x%02x)\n", 636 printf("SW%d = 0b%s (0x%02x)\n",
570 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); 637 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
571 } 638 }
572 } 639 }
573 640
board/freescale/b4860qds/b4860qds_crossbar_con.h
Diff comments   View file @ 5e5097c
1 /* 1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc. 2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __CROSSBAR_CONNECTIONS_H__ 7 #ifndef __CROSSBAR_CONNECTIONS_H__
8 #define __CROSSBAR_CONNECTIONS_H__ 8 #define __CROSSBAR_CONNECTIONS_H__
9 9
10 #define NUM_CON_VSC3316 8 10 #define NUM_CON_VSC3316 8
11 #define NUM_CON_VSC3308 4 11 #define NUM_CON_VSC3308 4
12 12
13 static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10}, 13 static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
14 {5, 11}, {4, 5}, {2, 6}, {12, 9} }; 14 {5, 11}, {4, 5}, {2, 6}, {12, 9} };
15 15
16 static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, 16 static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
17 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 17 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
18 18
19 static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1}, 19 static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
20 {7, 8}, {9, 0}, {2, 14}, {12, 15}, 20 {7, 8}, {9, 0}, {2, 14}, {12, 15},
21 {-1, -1}, {-1, -1} }; 21 {-1, -1}, {-1, -1} };
22 22
23 static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1}, 23 static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
24 {7, 8}, {9, 0}, {5, 14}, {4, 15}, 24 {7, 8}, {9, 0}, {5, 14}, {4, 15},
25 {-1, -1}, {-1, -1} }; 25 {-1, -1}, {-1, -1} };
26 26
27 static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
28 {7, 8}, {9, 0}, {5, 14},
29 {4, 15}, {2, 12}, {12, 13} };
30
27 #ifdef CONFIG_PPC_B4420 31 #ifdef CONFIG_PPC_B4420
28 static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, 32 static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
29 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 33 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
30 #endif 34 #endif
31 35
32 static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1}, 36 static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
33 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 37 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
34 38
35 static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9}, 39 static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
36 {11, 11}, {5, 10}, {6, 3}, {9, 12} }; 40 {11, 11}, {5, 10}, {6, 3}, {9, 12} };
37 41
38 static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, 42 static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
39 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 43 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
40 44
41 static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1}, 45 static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
42 {7, 8}, {1, 9}, {14, 3}, {15, 12}, 46 {7, 8}, {1, 9}, {14, 3}, {15, 12},
43 {-1, -1}, {-1, -1} }; 47 {-1, -1}, {-1, -1} };
44 48
45 static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1}, 49 static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
46 {7, 8}, {1, 9}, {14, 11}, {15, 10}, 50 {7, 8}, {1, 9}, {14, 11}, {15, 10},
47 {-1, -1}, {-1, -1} }; 51 {-1, -1}, {-1, -1} };
52
53 static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
54 {7, 8}, {1, 9}, {14, 11},
55 {15, 10}, {13, 3}, {12, 12} };
48 56
49 #ifdef CONFIG_PPC_B4420 57 #ifdef CONFIG_PPC_B4420
50 static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, 58 static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
51 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 59 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
52 #endif 60 #endif
53 61
54 static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1}, 62 static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1},
55 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 63 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
56 64
57 static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} }; 65 static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
58 66
59 static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} }; 67 static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} };
60 68
61 static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} }; 69 static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
62 70
63 static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} }; 71 static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} };
64 72
65 #endif 73 #endif
66 74