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Commit 5e5097c110ab5d6bda7f18b7a795d17f27ac3d36

Authored by Shaveta Leekha
Committed by York Sun
1 parent e4b87e5b1d
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

board/b4860qds: Add support to make Aurora work on B4860QDS 

1) Add new SerDes1 protocols having Aurora in them
2) Add VSC cross point connections for Aurora to work with
   CPRI and SGMIIs
3) Configure VSC crossbar switch to connect SerDes1
   lanes to aurora on board, by checking SerDes1 protocols
4) SerDes1 Refclks have been set properly to make
   Aurora, CPRI and SGMIIs to work together properly

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 3 changed files with 111 additions and 4 deletions Side-by-side Diff

arch/powerpc/cpu/mpc85xx/b4860_serdes.c
Diff comments   View file @ 5e5097c
... ... @@ -18,6 +18,24 @@
18 18 #ifdef CONFIG_PPC_B4860
19 19 static struct serdes_config serdes1_cfg_tbl[] = {
20 20 /* SerDes 1 */
  21 + {0x02, {AURORA, AURORA, CPRI6, CPRI5,
  22 + CPRI4, CPRI3, CPRI2, CPRI1} },
  23 + {0x04, {AURORA, AURORA, CPRI6, CPRI5,
  24 + CPRI4, CPRI3, CPRI2, CPRI1} },
  25 + {0x05, {AURORA, AURORA, CPRI6, CPRI5,
  26 + CPRI4, CPRI3, CPRI2, CPRI1} },
  27 + {0x06, {AURORA, AURORA, CPRI6, CPRI5,
  28 + CPRI4, CPRI3, CPRI2, CPRI1} },
  29 + {0x08, {AURORA, AURORA, CPRI6, CPRI5,
  30 + CPRI4, CPRI3, CPRI2, CPRI1} },
  31 + {0x09, {AURORA, AURORA, CPRI6, CPRI5,
  32 + CPRI4, CPRI3, CPRI2, CPRI1} },
  33 + {0x0A, {AURORA, AURORA, CPRI6, CPRI5,
  34 + CPRI4, CPRI3, CPRI2, CPRI1} },
  35 + {0x0B, {AURORA, AURORA, CPRI6, CPRI5,
  36 + CPRI4, CPRI3, CPRI2, CPRI1} },
  37 + {0x0C, {AURORA, AURORA, CPRI6, CPRI5,
  38 + CPRI4, CPRI3, CPRI2, CPRI1} },
21 39 {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
22 40 CPRI4, CPRI3, CPRI2, CPRI1}},
23 41 {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
24 42  
... ... @@ -44,8 +62,22 @@
44 62 {0x34, {AURORA, AURORA,
45 63 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
46 64 CPRI4, CPRI3, CPRI2, CPRI1}},
  65 + {0x39, {AURORA, AURORA, CPRI6, CPRI5,
  66 + CPRI4, CPRI3, CPRI2, CPRI1} },
  67 + {0x3A, {AURORA, AURORA, CPRI6, CPRI5,
  68 + CPRI4, CPRI3, CPRI2, CPRI1} },
  69 + {0x3C, {AURORA, AURORA, CPRI6, CPRI5,
  70 + CPRI4, CPRI3, CPRI2, CPRI1} },
  71 + {0x3D, {AURORA, AURORA, CPRI6, CPRI5,
  72 + CPRI4, CPRI3, CPRI2, CPRI1} },
47 73 {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
48 74 CPRI4, CPRI3, CPRI2, CPRI1}},
  75 + {0x5C, {AURORA, AURORA,
  76 + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  77 + CPRI4, CPRI3, CPRI2, CPRI1} },
  78 + {0x5D, {AURORA, AURORA,
  79 + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  80 + CPRI4, CPRI3, CPRI2, CPRI1} },
49 81 {}
50 82 };
51 83 static struct serdes_config serdes2_cfg_tbl[] = {
board/freescale/b4860qds/b4860qds.c
Diff comments   View file @ 5e5097c
... ... @@ -151,6 +151,53 @@
151 151 }
152 152 break;
153 153  
  154 + case 0x02:
  155 + case 0x04:
  156 + case 0x05:
  157 + case 0x06:
  158 + case 0x08:
  159 + case 0x09:
  160 + case 0x0A:
  161 + case 0x0B:
  162 + case 0x0C:
  163 + case 0x30:
  164 + case 0x32:
  165 + case 0x33:
  166 + case 0x34:
  167 + case 0x39:
  168 + case 0x3A:
  169 + case 0x3C:
  170 + case 0x3D:
  171 + case 0x5C:
  172 + case 0x5D:
  173 + /*
  174 + * Configuration:
  175 + * SERDES: 1
  176 + * Lanes: A,B: AURORA
  177 + * Lanes: C,d: SGMII
  178 + * Lanes: E,F,G,H: CPRI
  179 + */
  180 + debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
  181 + " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
  182 + num_vsc16_con = NUM_CON_VSC3316;
  183 + /* Configure VSC3316 crossbar switch */
  184 + ret = select_i2c_ch_pca(I2C_CH_VSC3316);
  185 + if (!ret) {
  186 + ret = vsc3316_config(VSC3316_TX_ADDRESS,
  187 + vsc16_tx_sfp_sgmii_aurora,
  188 + num_vsc16_con);
  189 + if (ret)
  190 + return ret;
  191 + ret = vsc3316_config(VSC3316_RX_ADDRESS,
  192 + vsc16_rx_sfp_sgmii_aurora,
  193 + num_vsc16_con);
  194 + if (ret)
  195 + return ret;
  196 + } else {
  197 + return ret;
  198 + }
  199 + break;
  200 +
154 201 #ifdef CONFIG_PPC_B4420
155 202 case 0x18:
156 203 /*
... ... @@ -245,7 +292,7 @@
245 292 serdes_corenet_t *srds_regs =
246 293 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
247 294 u32 serdes1_prtcl, lane;
248   - unsigned int flag_sgmii_prtcl = 0;
  295 + unsigned int flag_sgmii_aurora_prtcl = 0;
249 296 int ret, i;
250 297  
251 298 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
... ... @@ -270,6 +317,25 @@
270 317 case 0x2C:
271 318 case 0x2D:
272 319 case 0x2E:
  320 + case 0x02:
  321 + case 0x04:
  322 + case 0x05:
  323 + case 0x06:
  324 + case 0x08:
  325 + case 0x09:
  326 + case 0x0A:
  327 + case 0x0B:
  328 + case 0x0C:
  329 + case 0x30:
  330 + case 0x32:
  331 + case 0x33:
  332 + case 0x34:
  333 + case 0x39:
  334 + case 0x3A:
  335 + case 0x3C:
  336 + case 0x3D:
  337 + case 0x5C:
  338 + case 0x5D:
273 339 debug("Configuring idt8t49n222a for CPRI SerDes clks:"
274 340 " for srds_prctl:%x\n", serdes1_prtcl);
275 341 ret = select_i2c_ch_pca(I2C_CH_IDT);
... ... @@ -288,7 +354,7 @@
288 354 select_i2c_ch_pca(I2C_CH_DEFAULT);
289 355  
290 356 /* Change SerDes1's Refclk1 to 125MHz for on board
291   - * SGMIIs to work
  357 + * SGMIIs or Aurora to work
292 358 */
293 359 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
294 360 enum srds_prtcl lane_prtcl = serdes_get_prtcl
295 361  
... ... @@ -300,14 +366,15 @@
300 366 case SGMII_FM1_DTSEC4:
301 367 case SGMII_FM1_DTSEC5:
302 368 case SGMII_FM1_DTSEC6:
303   - flag_sgmii_prtcl++;
  369 + case AURORA:
  370 + flag_sgmii_aurora_prtcl++;
304 371 break;
305 372 default:
306 373 break;
307 374 }
308 375 }
309 376  
310   - if (flag_sgmii_prtcl)
  377 + if (flag_sgmii_aurora_prtcl)
311 378 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
312 379  
313 380 /* Steps For SerDes PLLs reset and reconfiguration after
board/freescale/b4860qds/b4860qds_crossbar_con.h
Diff comments   View file @ 5e5097c
... ... @@ -24,6 +24,10 @@
24 24 {7, 8}, {9, 0}, {5, 14}, {4, 15},
25 25 {-1, -1}, {-1, -1} };
26 26  
  27 +static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
  28 + {7, 8}, {9, 0}, {5, 14},
  29 + {4, 15}, {2, 12}, {12, 13} };
  30 +
27 31 #ifdef CONFIG_PPC_B4420
28 32 static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
29 33 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
... ... @@ -45,6 +49,10 @@
45 49 static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
46 50 {7, 8}, {1, 9}, {14, 11}, {15, 10},
47 51 {-1, -1}, {-1, -1} };
  52 +
  53 +static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
  54 + {7, 8}, {1, 9}, {14, 11},
  55 + {15, 10}, {13, 3}, {12, 12} };
48 56  
49 57 #ifdef CONFIG_PPC_B4420
50 58 static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},