Eric Lee / smarc-uboot

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Commit 5e5803e119de3bebd76fc9a57baac0b5aeccc8a3

Authored by stefano babic
Committed by Wolfgang Denk
1 parent 80172c6181
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

PXA270: Added support for TrizepsIV board. 

This patch add support for the Trizeps IV module (520Mhz).

Signed-off-by: Stefano Babic <sbabic@denx.de>

Showing 10 changed files with 1217 additions and 2 deletions Side-by-side Diff

... ... @@ -2334,6 +2334,9 @@
2334 2334 pxa255_idp_config: unconfig
2335 2335 @$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp
2336 2336  
  2337 +trizepsiv_config : unconfig
  2338 + @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv
  2339 +
2337 2340 wepep250_config : unconfig
2338 2341 @$(MKCONFIG) $(@:_config=) arm pxa wepep250
2339 2342  
board/trizepsiv/Makefile
Diff comments   View file @ 5e5803e
  1 +#
  2 +# (C) Copyright 2000-2006
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = $(obj)lib$(BOARD).a
  27 +
  28 +COBJS := conxs.o eeprom.o
  29 +SOBJS := lowlevel_init.o pxavoltage.o
  30 +
  31 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  32 +OBJS := $(addprefix $(obj),$(COBJS))
  33 +SOBJS := $(addprefix $(obj),$(SOBJS))
  34 +
  35 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
  36 + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
  37 +
  38 +clean:
  39 + rm -f $(SOBJS) $(OBJS)
  40 +
  41 +distclean: clean
  42 + rm -f $(LIB) core *.bak .depend
  43 +
  44 +#########################################################################
  45 +
  46 +# defines $(obj).depend target
  47 +include $(SRCTREE)/rules.mk
  48 +
  49 +sinclude $(obj).depend
  50 +
  51 +#########################################################################
board/trizepsiv/config.mk
Diff comments   View file @ 5e5803e
  1 +TEXT_BASE =0xa1f00000
  2 +# 0xa1700000
  3 +#TEXT_BASE = 0
board/trizepsiv/conxs.c
Diff comments   View file @ 5e5803e
  1 +/*
  2 + * (C) Copyright 2007
  3 + * Stefano Babic, DENX Gmbh, sbabic@denx.de
  4 + *
  5 + * (C) Copyright 2004
  6 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
  7 + *
  8 + * (C) Copyright 2002
  9 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  10 + *
  11 + * (C) Copyright 2002
  12 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  13 + * Marius Groeger <mgroeger@sysgo.de>
  14 + *
  15 + * See file CREDITS for list of people who contributed to this
  16 + * project.
  17 + *
  18 + * This program is free software; you can redistribute it and/or
  19 + * modify it under the terms of the GNU General Public License as
  20 + * published by the Free Software Foundation; either version 2 of
  21 + * the License, or (at your option) any later version.
  22 + *
  23 + * This program is distributed in the hope that it will be useful,
  24 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26 + * GNU General Public License for more details.
  27 + *
  28 + * You should have received a copy of the GNU General Public License
  29 + * along with this program; if not, write to the Free Software
  30 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  31 + * MA 02111-1307 USA
  32 + */
  33 +
  34 +#include <common.h>
  35 +#include <asm/arch/pxa-regs.h>
  36 +
  37 +DECLARE_GLOBAL_DATA_PTR;
  38 +
  39 +#define RH_A_PSM (1 << 8) /* power switching mode */
  40 +#define RH_A_NPS (1 << 9) /* no power switching */
  41 +
  42 +extern struct serial_device serial_ffuart_device;
  43 +extern struct serial_device serial_btuart_device;
  44 +extern struct serial_device serial_stuart_device;
  45 +
  46 +/* ------------------------------------------------------------------------- */
  47 +
  48 +/*
  49 + * Miscelaneous platform dependent initialisations
  50 + */
  51 +
  52 +void usb_board_init(void)
  53 +{
  54 + UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
  55 + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
  56 +
  57 + UHCHR |= UHCHR_FSBIR;
  58 +
  59 + while (UHCHR & UHCHR_FSBIR);
  60 +
  61 + UHCHR &= ~UHCHR_SSE;
  62 + UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
  63 +
  64 + /* Clear any OTG Pin Hold */
  65 + if (PSSR & PSSR_OTGPH)
  66 + PSSR |= PSSR_OTGPH;
  67 +
  68 + UHCRHDA &= ~(RH_A_NPS);
  69 + UHCRHDA |= RH_A_PSM;
  70 +
  71 + /* Set port power control mask bits, only 3 ports. */
  72 + UHCRHDB |= (0x7<<17);
  73 +}
  74 +
  75 +void usb_board_init_fail(void)
  76 +{
  77 + return;
  78 +}
  79 +
  80 +void usb_board_stop(void)
  81 +{
  82 + UHCHR |= UHCHR_FHR;
  83 + udelay(11);
  84 + UHCHR &= ~UHCHR_FHR;
  85 +
  86 + UHCCOMS |= 1;
  87 + udelay(10);
  88 +
  89 + CKEN &= ~CKEN10_USBHOST;
  90 +
  91 + puts("Called USB STOP\n");
  92 + return;
  93 +}
  94 +
  95 +int board_init (void)
  96 +{
  97 + /* memory and cpu-speed are setup before relocation */
  98 + /* so we do _nothing_ here */
  99 +
  100 + /* arch number of ConXS Board */
  101 + gd->bd->bi_arch_number = 776;
  102 +
  103 + /* adress of boot parameters */
  104 + gd->bd->bi_boot_params = 0xa000003c;
  105 +
  106 + return 0;
  107 +}
  108 +
  109 +int board_late_init(void)
  110 +{
  111 +#if defined(CONFIG_SERIAL_MULTI)
  112 + char *console=getenv("boot_console");
  113 +
  114 + if ((strcmp(console,"serial_btuart") == 0) ||
  115 + (strcmp(console,"serial_stuart") == 0) ||
  116 + (strcmp(console,"serial_ffuart") == 0)) {
  117 + setenv("stdout",console);
  118 + setenv("stdin", console);
  119 + setenv("stderr",console);
  120 + } else {
  121 + setenv("stdout", "serial");
  122 + setenv("stdin", "serial");
  123 + setenv("stderr", "serial");
  124 + }
  125 +#endif
  126 + return 0;
  127 +}
  128 +
  129 +struct serial_device *default_serial_console (void)
  130 +{
  131 + return &serial_ffuart_device;
  132 +}
  133 +
  134 +int dram_init (void)
  135 +{
  136 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  137 + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  138 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  139 + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  140 + gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
  141 + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
  142 + gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
  143 + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
  144 +
  145 + return 0;
  146 +}
board/trizepsiv/eeprom.c
Diff comments   View file @ 5e5803e
  1 +/*
  2 + * (C) Copyright 2007
  3 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <command.h>
  26 +
  27 +static unsigned char srom[128];
  28 +extern u16 read_srom_word(int);
  29 +extern void write_srom_word(int offset, u16 val);
  30 +
  31 +static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
  32 + int i;
  33 +
  34 + for (i=0; i < 0x40; i++) {
  35 + if (!(i % 0x10))
  36 + printf("\n%08lx:", i);
  37 + printf(" %04x", read_srom_word(i));
  38 + }
  39 + printf ("\n");
  40 + return (0);
  41 +}
  42 +
  43 +static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
  44 + int offset,value;
  45 +
  46 + if (argc < 4) {
  47 + printf ("Usage:\n%s\n", cmdtp->usage);
  48 + return 1;
  49 + }
  50 +
  51 + offset=simple_strtoul(argv[2],NULL,16);
  52 + value=simple_strtoul(argv[3],NULL,16);
  53 + if (offset > 0x40) {
  54 + printf("Wrong offset : 0x%x\n",offset);
  55 + printf ("Usage:\n%s\n", cmdtp->usage);
  56 + return 1;
  57 + }
  58 + write_srom_word(offset, value);
  59 + return (0);
  60 +}
  61 +
  62 +int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
  63 + if (argc < 2) {
  64 + printf ("Usage:\n%s\n", cmdtp->usage);
  65 + return 1;
  66 + }
  67 +
  68 + if (strcmp (argv[1],"read") == 0) {
  69 + return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv));
  70 + } else if (strcmp (argv[1],"write") == 0) {
  71 + return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv));
  72 + } else {
  73 + printf ("Usage:\n%s\n", cmdtp->usage);
  74 + return 1;
  75 + }
  76 +}
  77 +
  78 +U_BOOT_CMD(
  79 + dm9000ee,4,1,do_dm9000_eeprom,
  80 + "dm9000ee- Read/Write eeprom connected to Ethernet Controller\n",
  81 + "\ndm9000ee write <word offset> <value> \n"
  82 + "\tdm9000ee read \n"
  83 + "\tword:\t\t00-02 : MAC Address\n"
  84 + "\t\t\t03-07 : DM9000 Configuration\n"
  85 + "\t\t\t08-63 : User data\n");
board/trizepsiv/lowlevel_init.S
Diff comments   View file @ 5e5803e
  1 +/*
  2 + * This was originally from the Lubbock u-boot port.
  3 + *
  4 + * Most of this taken from Redboot hal_platform_setup.h with cleanup
  5 + *
  6 + * NOTE: I haven't clean this up considerably, just enough to get it
  7 + * running. See hal_platform_setup.h for the source. See
  8 + * board/cradle/lowlevel_init.S for another PXA250 setup that is
  9 + * much cleaner.
  10 + *
  11 + * See file CREDITS for list of people who contributed to this
  12 + * project.
  13 + *
  14 + * This program is free software; you can redistribute it and/or
  15 + * modify it under the terms of the GNU General Public License as
  16 + * published by the Free Software Foundation; either version 2 of
  17 + * the License, or (at your option) any later version.
  18 + *
  19 + * This program is distributed in the hope that it will be useful,
  20 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22 + * GNU General Public License for more details.
  23 + *
  24 + * You should have received a copy of the GNU General Public License
  25 + * along with this program; if not, write to the Free Software
  26 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27 + * MA 02111-1307 USA
  28 + */
  29 +
  30 +#include <config.h>
  31 +#include <version.h>
  32 +#include <asm/arch/pxa-regs.h>
  33 +
  34 +/* wait for coprocessor write complete */
  35 + .macro CPWAIT reg
  36 + mrc p15,0,\reg,c2,c0,0
  37 + mov \reg,\reg
  38 + sub pc,pc,#4
  39 + .endm
  40 +
  41 +
  42 +/*
  43 + * Memory setup
  44 + */
  45 +
  46 +.globl lowlevel_init
  47 +lowlevel_init:
  48 +
  49 + /* Set up GPIO pins first ----------------------------------------- */
  50 +
  51 + ldr r0, =GPSR0
  52 + ldr r1, =CFG_GPSR0_VAL
  53 + str r1, [r0]
  54 +
  55 + ldr r0, =GPSR1
  56 + ldr r1, =CFG_GPSR1_VAL
  57 + str r1, [r0]
  58 +
  59 + ldr r0, =GPSR2
  60 + ldr r1, =CFG_GPSR2_VAL
  61 + str r1, [r0]
  62 +
  63 + ldr r0, =GPSR3
  64 + ldr r1, =CFG_GPSR3_VAL
  65 + str r1, [r0]
  66 +
  67 + ldr r0, =GPCR0
  68 + ldr r1, =CFG_GPCR0_VAL
  69 + str r1, [r0]
  70 +
  71 + ldr r0, =GPCR1
  72 + ldr r1, =CFG_GPCR1_VAL
  73 + str r1, [r0]
  74 +
  75 + ldr r0, =GPCR2
  76 + ldr r1, =CFG_GPCR2_VAL
  77 + str r1, [r0]
  78 +
  79 + ldr r0, =GPCR3
  80 + ldr r1, =CFG_GPCR3_VAL
  81 + str r1, [r0]
  82 +
  83 + ldr r0, =GRER0
  84 + ldr r1, =CFG_GRER0_VAL
  85 + str r1, [r0]
  86 +
  87 + ldr r0, =GRER1
  88 + ldr r1, =CFG_GRER1_VAL
  89 + str r1, [r0]
  90 +
  91 + ldr r0, =GRER2
  92 + ldr r1, =CFG_GRER2_VAL
  93 + str r1, [r0]
  94 +
  95 + ldr r0, =GRER3
  96 + ldr r1, =CFG_GRER3_VAL
  97 + str r1, [r0]
  98 +
  99 + ldr r0, =GFER0
  100 + ldr r1, =CFG_GFER0_VAL
  101 + str r1, [r0]
  102 +
  103 + ldr r0, =GFER1
  104 + ldr r1, =CFG_GFER1_VAL
  105 + str r1, [r0]
  106 +
  107 + ldr r0, =GFER2
  108 + ldr r1, =CFG_GFER2_VAL
  109 + str r1, [r0]
  110 +
  111 + ldr r0, =GFER3
  112 + ldr r1, =CFG_GFER3_VAL
  113 + str r1, [r0]
  114 +
  115 + ldr r0, =GPDR0
  116 + ldr r1, =CFG_GPDR0_VAL
  117 + str r1, [r0]
  118 +
  119 + ldr r0, =GPDR1
  120 + ldr r1, =CFG_GPDR1_VAL
  121 + str r1, [r0]
  122 +
  123 + ldr r0, =GPDR2
  124 + ldr r1, =CFG_GPDR2_VAL
  125 + str r1, [r0]
  126 +
  127 + ldr r0, =GPDR3
  128 + ldr r1, =CFG_GPDR3_VAL
  129 + str r1, [r0]
  130 +
  131 + ldr r0, =GAFR0_L
  132 + ldr r1, =CFG_GAFR0_L_VAL
  133 + str r1, [r0]
  134 +
  135 + ldr r0, =GAFR0_U
  136 + ldr r1, =CFG_GAFR0_U_VAL
  137 + str r1, [r0]
  138 +
  139 + ldr r0, =GAFR1_L
  140 + ldr r1, =CFG_GAFR1_L_VAL
  141 + str r1, [r0]
  142 +
  143 + ldr r0, =GAFR1_U
  144 + ldr r1, =CFG_GAFR1_U_VAL
  145 + str r1, [r0]
  146 +
  147 + ldr r0, =GAFR2_L
  148 + ldr r1, =CFG_GAFR2_L_VAL
  149 + str r1, [r0]
  150 +
  151 + ldr r0, =GAFR2_U
  152 + ldr r1, =CFG_GAFR2_U_VAL
  153 + str r1, [r0]
  154 +
  155 + ldr r0, =GAFR3_L
  156 + ldr r1, =CFG_GAFR3_L_VAL
  157 + str r1, [r0]
  158 +
  159 + ldr r0, =GAFR3_U
  160 + ldr r1, =CFG_GAFR3_U_VAL
  161 + str r1, [r0]
  162 +
  163 + ldr r0, =PSSR /* enable GPIO pins */
  164 + ldr r1, =CFG_PSSR_VAL
  165 + str r1, [r0]
  166 +
  167 + /* ---------------------------------------------------------------- */
  168 + /* Enable memory interface */
  169 + /* */
  170 + /* The sequence below is based on the recommended init steps */
  171 + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
  172 + /* Chapter 10. */
  173 + /* ---------------------------------------------------------------- */
  174 +
  175 + /* ---------------------------------------------------------------- */
  176 + /* Step 1: Wait for at least 200 microsedonds to allow internal */
  177 + /* clocks to settle. Only necessary after hard reset... */
  178 + /* FIXME: can be optimized later */
  179 + /* ---------------------------------------------------------------- */
  180 +
  181 + ldr r3, =OSCR /* reset the OS Timer Count to zero */
  182 + mov r2, #0
  183 + str r2, [r3]
  184 + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
  185 + /* so 0x300 should be plenty */
  186 +1:
  187 + ldr r2, [r3]
  188 + cmp r4, r2
  189 + bgt 1b
  190 +
  191 +mem_init:
  192 +
  193 + ldr r1, =MEMC_BASE /* get memory controller base addr. */
  194 +
  195 + /* ---------------------------------------------------------------- */
  196 + /* Step 2a: Initialize Asynchronous static memory controller */
  197 + /* ---------------------------------------------------------------- */
  198 +
  199 + /* MSC registers: timing, bus width, mem type */
  200 +
  201 + /* MSC0: nCS(0,1) */
  202 + ldr r2, =CFG_MSC0_VAL
  203 + str r2, [r1, #MSC0_OFFSET]
  204 + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
  205 + /* that data latches */
  206 + /* MSC1: nCS(2,3) */
  207 + ldr r2, =CFG_MSC1_VAL
  208 + str r2, [r1, #MSC1_OFFSET]
  209 + ldr r2, [r1, #MSC1_OFFSET]
  210 +
  211 + /* MSC2: nCS(4,5) */
  212 + ldr r2, =CFG_MSC2_VAL
  213 + str r2, [r1, #MSC2_OFFSET]
  214 + ldr r2, [r1, #MSC2_OFFSET]
  215 +
  216 + /* ---------------------------------------------------------------- */
  217 + /* Step 2b: Initialize Card Interface */
  218 + /* ---------------------------------------------------------------- */
  219 +
  220 + /* MECR: Memory Expansion Card Register */
  221 + ldr r2, =CFG_MECR_VAL
  222 + str r2, [r1, #MECR_OFFSET]
  223 + ldr r2, [r1, #MECR_OFFSET]
  224 +
  225 + /* MCMEM0: Card Interface slot 0 timing */
  226 + ldr r2, =CFG_MCMEM0_VAL
  227 + str r2, [r1, #MCMEM0_OFFSET]
  228 + ldr r2, [r1, #MCMEM0_OFFSET]
  229 +
  230 + /* MCMEM1: Card Interface slot 1 timing */
  231 + ldr r2, =CFG_MCMEM1_VAL
  232 + str r2, [r1, #MCMEM1_OFFSET]
  233 + ldr r2, [r1, #MCMEM1_OFFSET]
  234 +
  235 + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
  236 + ldr r2, =CFG_MCATT0_VAL
  237 + str r2, [r1, #MCATT0_OFFSET]
  238 + ldr r2, [r1, #MCATT0_OFFSET]
  239 +
  240 + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
  241 + ldr r2, =CFG_MCATT1_VAL
  242 + str r2, [r1, #MCATT1_OFFSET]
  243 + ldr r2, [r1, #MCATT1_OFFSET]
  244 +
  245 + /* MCIO0: Card Interface I/O Space Timing, slot 0 */
  246 + ldr r2, =CFG_MCIO0_VAL
  247 + str r2, [r1, #MCIO0_OFFSET]
  248 + ldr r2, [r1, #MCIO0_OFFSET]
  249 +
  250 + /* MCIO1: Card Interface I/O Space Timing, slot 1 */
  251 + ldr r2, =CFG_MCIO1_VAL
  252 + str r2, [r1, #MCIO1_OFFSET]
  253 + ldr r2, [r1, #MCIO1_OFFSET]
  254 +
  255 + /* ---------------------------------------------------------------- */
  256 + /* Step 2c: Write FLYCNFG FIXME: what's that??? */
  257 + /* ---------------------------------------------------------------- */
  258 + ldr r2, =CFG_FLYCNFG_VAL
  259 + str r2, [r1, #FLYCNFG_OFFSET]
  260 + str r2, [r1, #FLYCNFG_OFFSET]
  261 +
  262 + /* ---------------------------------------------------------------- */
  263 + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
  264 + /* ---------------------------------------------------------------- */
  265 +
  266 + /* Before accessing MDREFR we need a valid DRI field, so we set */
  267 + /* this to power on defaults + DRI field. */
  268 +
  269 + ldr r4, [r1, #MDREFR_OFFSET]
  270 + ldr r2, =0xFFF
  271 + bic r4, r4, r2
  272 +
  273 + ldr r3, =CFG_MDREFR_VAL
  274 + and r3, r3, r2
  275 +
  276 + orr r4, r4, r3
  277 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
  278 +
  279 + orr r4, r4, #MDREFR_K0RUN
  280 + orr r4, r4, #MDREFR_K0DB4
  281 + orr r4, r4, #MDREFR_K0FREE
  282 + orr r4, r4, #MDREFR_K0DB2
  283 + orr r4, r4, #MDREFR_K1DB2
  284 + bic r4, r4, #MDREFR_K1FREE
  285 + bic r4, r4, #MDREFR_K2FREE
  286 +
  287 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
  288 + ldr r4, [r1, #MDREFR_OFFSET]
  289 +
  290 + /* Note: preserve the mdrefr value in r4 */
  291 +
  292 +
  293 + /* ---------------------------------------------------------------- */
  294 + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
  295 + /* ---------------------------------------------------------------- */
  296 +
  297 + /* Initialize SXCNFG register. Assert the enable bits */
  298 +
  299 + /* Write SXMRS to cause an MRS command to all enabled banks of */
  300 + /* synchronous static memory. Note that SXLCR need not be written */
  301 + /* at this time. */
  302 +
  303 + ldr r2, =CFG_SXCNFG_VAL
  304 + str r2, [r1, #SXCNFG_OFFSET]
  305 +
  306 + /* ---------------------------------------------------------------- */
  307 + /* Step 4: Initialize SDRAM */
  308 + /* ---------------------------------------------------------------- */
  309 +
  310 + bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
  311 +
  312 + orr r4, r4, #MDREFR_K1RUN
  313 + bic r4, r4, #MDREFR_K2DB2
  314 + str r4, [r1, #MDREFR_OFFSET]
  315 + ldr r4, [r1, #MDREFR_OFFSET]
  316 +
  317 + bic r4, r4, #MDREFR_SLFRSH
  318 + str r4, [r1, #MDREFR_OFFSET]
  319 + ldr r4, [r1, #MDREFR_OFFSET]
  320 +
  321 + orr r4, r4, #MDREFR_E1PIN
  322 + str r4, [r1, #MDREFR_OFFSET]
  323 + ldr r4, [r1, #MDREFR_OFFSET]
  324 +
  325 + nop
  326 + nop
  327 +
  328 +
  329 + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
  330 + /* configure but not enable each SDRAM partition pair. */
  331 +
  332 + ldr r4, =CFG_MDCNFG_VAL
  333 + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
  334 + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
  335 +
  336 + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
  337 + ldr r4, [r1, #MDCNFG_OFFSET]
  338 +
  339 +
  340 + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
  341 + /* 100..200 ยตsec. */
  342 +
  343 + ldr r3, =OSCR /* reset the OS Timer Count to zero */
  344 + mov r2, #0
  345 + str r2, [r3]
  346 + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
  347 + /* so 0x300 should be plenty */
  348 +1:
  349 + ldr r2, [r3]
  350 + cmp r4, r2
  351 + bgt 1b
  352 +
  353 +
  354 + /* Step 4f: Trigger a number (usually 8) refresh cycles by */
  355 + /* attempting non-burst read or write accesses to disabled */
  356 + /* SDRAM, as commonly specified in the power up sequence */
  357 + /* documented in SDRAM data sheets. The address(es) used */
  358 + /* for this purpose must not be cacheable. */
  359 +
  360 + ldr r3, =CFG_DRAM_BASE
  361 + str r2, [r3]
  362 + str r2, [r3]
  363 + str r2, [r3]
  364 + str r2, [r3]
  365 + str r2, [r3]
  366 + str r2, [r3]
  367 + str r2, [r3]
  368 + str r2, [r3]
  369 +
  370 +
  371 + /* Step 4g: Write MDCNFG with enable bits asserted */
  372 + /* (MDCNFG:DEx set to 1). */
  373 +
  374 + ldr r3, [r1, #MDCNFG_OFFSET]
  375 + mov r4, r3
  376 + orr r3, r3, #MDCNFG_DE0
  377 + str r3, [r1, #MDCNFG_OFFSET]
  378 + mov r0, r3
  379 +
  380 + /* Step 4h: Write MDMRS. */
  381 +
  382 + ldr r2, =CFG_MDMRS_VAL
  383 + str r2, [r1, #MDMRS_OFFSET]
  384 +
  385 + /* enable APD */
  386 + ldr r3, [r1, #MDREFR_OFFSET]
  387 + orr r3, r3, #MDREFR_APD
  388 + str r3, [r1, #MDREFR_OFFSET]
  389 +
  390 + /* We are finished with Intel's memory controller initialisation */
  391 +
  392 +
  393 +setvoltage:
  394 +
  395 + mov r10, lr
  396 + bl initPXAvoltage /* In case the board is rebooting with a */
  397 + mov lr, r10 /* low voltage raise it up to a good one. */
  398 +
  399 +#if 1
  400 + b initirqs
  401 +#endif
  402 +
  403 +wakeup:
  404 + /* Are we waking from sleep? */
  405 + ldr r0, =RCSR
  406 + ldr r1, [r0]
  407 + and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
  408 + str r1, [r0]
  409 + teq r1, #RCSR_SMR
  410 +
  411 + bne initirqs
  412 +
  413 + ldr r0, =PSSR
  414 + mov r1, #PSSR_PH
  415 + str r1, [r0]
  416 +
  417 + /* if so, resume at PSPR */
  418 + ldr r0, =PSPR
  419 + ldr r1, [r0]
  420 + mov pc, r1
  421 +
  422 + /* ---------------------------------------------------------------- */
  423 + /* Disable (mask) all interrupts at interrupt controller */
  424 + /* ---------------------------------------------------------------- */
  425 +
  426 +initirqs:
  427 +
  428 + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
  429 + ldr r2, =ICLR
  430 + str r1, [r2]
  431 +
  432 + ldr r2, =ICMR /* mask all interrupts at the controller */
  433 + str r1, [r2]
  434 +
  435 + /* ---------------------------------------------------------------- */
  436 + /* Clock initialisation */
  437 + /* ---------------------------------------------------------------- */
  438 +
  439 +initclks:
  440 +
  441 + /* Disable the peripheral clocks, and set the core clock frequency */
  442 +
  443 + /* Turn Off on-chip peripheral clocks (except for memory) */
  444 + /* for re-configuration. */
  445 + ldr r1, =CKEN
  446 + ldr r2, =CFG_CKEN
  447 + str r2, [r1]
  448 +
  449 + /* ... and write the core clock config register */
  450 + ldr r2, =CFG_CCCR
  451 + ldr r1, =CCCR
  452 + str r2, [r1]
  453 +
  454 + /* Turn on turbo mode */
  455 + mrc p14, 0, r2, c6, c0, 0
  456 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/
  457 + mcr p14, 0, r2, c6, c0, 0
  458 +
  459 + /* Re-write MDREFR */
  460 + ldr r1, =MEMC_BASE
  461 + ldr r2, [r1, #MDREFR_OFFSET]
  462 + str r2, [r1, #MDREFR_OFFSET]
  463 +#ifdef RTC
  464 + /* enable the 32Khz oscillator for RTC and PowerManager */
  465 + ldr r1, =OSCC
  466 + mov r2, #OSCC_OON
  467 + str r2, [r1]
  468 +
  469 + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
  470 + /* has settled. */
  471 +60:
  472 + ldr r2, [r1]
  473 + ands r2, r2, #1
  474 + beq 60b
  475 +#else
  476 +#error "RTC not defined"
  477 +#endif
  478 +
  479 + /* Interrupt init: Mask all interrupts */
  480 + ldr r0, =ICMR /* enable no sources */
  481 + mov r1, #0
  482 + str r1, [r0]
  483 + /* FIXME */
  484 +
  485 +#ifdef NODEBUG
  486 + /*Disable software and data breakpoints */
  487 + mov r0,#0
  488 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */
  489 + mcr p15,0,r0,c14,c9,0 /* ibcr1 */
  490 + mcr p15,0,r0,c14,c4,0 /* dbcon */
  491 +
  492 + /*Enable all debug functionality */
  493 + mov r0,#0x80000000
  494 + mcr p14,0,r0,c10,c0,0 /* dcsr */
  495 +#endif
  496 +
  497 + /* ---------------------------------------------------------------- */
  498 + /* End lowlevel_init */
  499 + /* ---------------------------------------------------------------- */
  500 +
  501 +endlowlevel_init:
  502 +
  503 + mov pc, lr
board/trizepsiv/pxavoltage.S
Diff comments   View file @ 5e5803e
  1 +/*
  2 + * (C) Copyright 2007
  3 + * Stefano Babic, DENX Gmbh, sbabic@denx.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <asm/arch/pxa-regs.h>
  25 +
  26 +
  27 + .global initPXAvoltage
  28 +
  29 +initPXAvoltage:
  30 + mov pc, lr
board/trizepsiv/u-boot.lds
Diff comments   View file @ 5e5803e
  1 +/*
  2 + * (C) Copyright 2000
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
  25 +OUTPUT_ARCH(arm)
  26 +ENTRY(_start)
  27 +SECTIONS
  28 +{
  29 + . = 0x00000000;
  30 +
  31 + . = ALIGN(4);
  32 + .text :
  33 + {
  34 + cpu/pxa/start.o (.text)
  35 + *(.text)
  36 + }
  37 +
  38 + . = ALIGN(4);
  39 + .rodata : { *(.rodata) }
  40 +
  41 + . = ALIGN(4);
  42 + .data : { *(.data) }
  43 +
  44 + . = ALIGN(4);
  45 + .got : { *(.got) }
  46 +
  47 + . = .;
  48 + __u_boot_cmd_start = .;
  49 + .u_boot_cmd : { *(.u_boot_cmd) }
  50 + __u_boot_cmd_end = .;
  51 +
  52 + . = ALIGN(4);
  53 + __bss_start = .;
  54 + .bss : { *(.bss) }
  55 + _end = .;
  56 +}
... ... @@ -99,7 +99,7 @@
99 99 static int dm9000_probe(void);
100 100 static u16 phy_read(int);
101 101 static void phy_write(int, u16);
102   -static u16 read_srom_word(int);
  102 +u16 read_srom_word(int);
103 103 static u8 DM9000_ior(int);
104 104 static void DM9000_iow(int reg, u8 value);
105 105  
... ... @@ -537,7 +537,7 @@
537 537 /*
538 538 Read a word data from SROM
539 539 */
540   -static u16
  540 +u16
541 541 read_srom_word(int offset)
542 542 {
543 543 DM9000_iow(DM9000_EPAR, offset);
... ... @@ -546,6 +546,18 @@
546 546 DM9000_iow(DM9000_EPCR, 0x0);
547 547 return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
548 548 }
  549 +
  550 +void
  551 +write_srom_word(int offset, u16 val)
  552 +{
  553 + DM9000_iow(DM9000_EPAR, offset);
  554 + DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
  555 + DM9000_iow(DM9000_EPDRL, (val & 0xff));
  556 + DM9000_iow(DM9000_EPCR, 0x12);
  557 + udelay(8000);
  558 + DM9000_iow(DM9000_EPCR, 0);
  559 +}
  560 +
549 561  
550 562 /*
551 563 Read a byte from I/O port
include/configs/trizepsiv.h
Diff comments   View file @ 5e5803e
  1 +/*
  2 + * (C) Copyright 2007
  3 + * Stefano Babic, DENX Gmbh, sbabic@denx.de
  4 + *
  5 + * (C) Copyright 2004
  6 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
  7 + *
  8 + * (C) Copyright 2002
  9 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  10 + *
  11 + * (C) Copyright 2002
  12 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  13 + * Marius Groeger <mgroeger@sysgo.de>
  14 + *
  15 + * Configuation settings for the LUBBOCK board.
  16 + *
  17 + * See file CREDITS for list of people who contributed to this
  18 + * project.
  19 + *
  20 + * This program is free software; you can redistribute it and/or
  21 + * modify it under the terms of the GNU General Public License as
  22 + * published by the Free Software Foundation; either version 2 of
  23 + * the License, or (at your option) any later version.
  24 + *
  25 + * This program is distributed in the hope that it will be useful,
  26 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28 + * GNU General Public License for more details.
  29 + *
  30 + * You should have received a copy of the GNU General Public License
  31 + * along with this program; if not, write to the Free Software
  32 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33 + * MA 02111-1307 USA
  34 + */
  35 +
  36 +#ifndef __CONFIG_H
  37 +#define __CONFIG_H
  38 +
  39 +/*
  40 + * High Level Configuration Options
  41 + * (easy to change)
  42 + */
  43 +#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
  44 +
  45 +#define LITTLEENDIAN 1 /* used by usb_ohci.c */
  46 +
  47 +#define CONFIG_MMC 1
  48 +#define BOARD_LATE_INIT 1
  49 +
  50 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
  51 +
  52 +#define RTC
  53 +
  54 +/*
  55 + * Size of malloc() pool
  56 + */
  57 +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
  58 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  59 +
  60 +/*
  61 + * Hardware drivers
  62 + */
  63 +
  64 +/*
  65 + * select serial console configuration
  66 + */
  67 +#define CONFIG_SERIAL_MULTI
  68 +#define CONFIG_FFUART 1 /* we use FFUART on Conxs */
  69 +#define CONFIG_BTUART 1 /* we use BTUART on Conxs */
  70 +#define CONFIG_STUART 1 /* we use STUART on Conxs */
  71 +
  72 +/* allow to overwrite serial and ethaddr */
  73 +#define CONFIG_ENV_OVERWRITE
  74 +
  75 +#define CONFIG_BAUDRATE 38400
  76 +
  77 +#define CONFIG_DOS_PARTITION 1
  78 +
  79 +/*
  80 + * Command line configuration.
  81 + */
  82 +#include <config_cmd_default.h>
  83 +
  84 +#define CONFIG_CMD_MMC
  85 +#define CONFIG_CMD_FAT
  86 +#define CONFIG_CMD_IMLS
  87 +#define CONFIG_CMD_PING
  88 +#define CONFIG_CMD_USB
  89 +
  90 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  91 +
  92 +#undef CONFIG_SHOW_BOOT_PROGRESS
  93 +
  94 +#define CONFIG_BOOTDELAY 3
  95 +#define CONFIG_SERVERIP 192.168.1.99
  96 +#define CONFIG_BOOTCOMMAND "run boot_flash"
  97 +#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
  98 + " rw root=/dev/ram initrd=0xa0800000,5m"
  99 +
  100 +#define CONFIG_EXTRA_ENV_SETTINGS \
  101 + "program_boot_mmc=" \
  102 + "mw.b 0xa0010000 0xff 0x20000; " \
  103 + "if mmcinit && " \
  104 + "fatload mmc 0 0xa0010000 u-boot.bin; " \
  105 + "then " \
  106 + "protect off 0x0 0x1ffff; " \
  107 + "erase 0x0 0x1ffff; " \
  108 + "cp.b 0xa0010000 0x0 0x20000; " \
  109 + "fi\0" \
  110 + "program_uzImage_mmc=" \
  111 + "mw.b 0xa0010000 0xff 0x180000; " \
  112 + "if mmcinit && " \
  113 + "fatload mmc 0 0xa0010000 uzImage; " \
  114 + "then " \
  115 + "protect off 0x40000 0x1bffff; " \
  116 + "erase 0x40000 0x1bffff; " \
  117 + "cp.b 0xa0010000 0x40000 0x180000; " \
  118 + "fi\0" \
  119 + "program_ramdisk_mmc=" \
  120 + "mw.b 0xa0010000 0xff 0x500000; " \
  121 + "if mmcinit && " \
  122 + "fatload mmc 0 0xa0010000 ramdisk.gz; " \
  123 + "then " \
  124 + "protect off 0x1c0000 0x6bffff; " \
  125 + "erase 0x1c0000 0x6bffff; " \
  126 + "cp.b 0xa0010000 0x1c0000 0x500000; " \
  127 + "fi\0" \
  128 + "boot_mmc=" \
  129 + "if mmcinit && " \
  130 + "fatload mmc 0 0xa0030000 uzImage && " \
  131 + "fatload mmc 0 0xa0800000 ramdisk.gz; " \
  132 + "then " \
  133 + "bootm 0xa0030000; " \
  134 + "fi\0" \
  135 + "boot_flash=" \
  136 + "cp.b 0x1c0000 0xa0800000 0x500000; " \
  137 + "bootm 0x40000\0" \
  138 +
  139 +#define CONFIG_SETUP_MEMORY_TAGS 1
  140 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  141 +/* #define CONFIG_INITRD_TAG 1 */
  142 +
  143 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  144 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  145 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  146 +#endif
  147 +
  148 +/*
  149 + * Miscellaneous configurable options
  150 + */
  151 +#define CFG_HUSH_PARSER 1
  152 +#define CFG_PROMPT_HUSH_PS2 "> "
  153 +
  154 +#define CFG_LONGHELP /* undef to save memory */
  155 +#ifdef CFG_HUSH_PARSER
  156 +#define CFG_PROMPT "$ " /* Monitor Command Prompt */
  157 +#else
  158 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  159 +#endif
  160 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  161 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  162 +#define CFG_MAXARGS 16 /* max number of command args */
  163 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  164 +#define CFG_DEVICE_NULLDEV 1
  165 +
  166 +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
  167 +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
  168 +
  169 +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
  170 +
  171 +#define CFG_LOAD_ADDR 0xa1000000 /* default load address */
  172 +
  173 +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
  174 +#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
  175 +
  176 + /* valid baudrates */
  177 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  178 +
  179 +#define CFG_MMC_BASE 0xF0000000
  180 +
  181 +/*
  182 + * Stack sizes
  183 + *
  184 + * The stack sizes are set up in start.S using the settings below
  185 + */
  186 +#define CONFIG_STACKSIZE (128*1024) /* regular stack */
  187 +#ifdef CONFIG_USE_IRQ
  188 +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
  189 +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
  190 +#endif
  191 +
  192 +/*
  193 + * Physical Memory Map
  194 + */
  195 +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
  196 +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
  197 +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
  198 +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
  199 +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
  200 +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
  201 +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
  202 +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
  203 +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
  204 +
  205 +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
  206 +
  207 +#define CFG_DRAM_BASE 0xa0000000
  208 +#define CFG_DRAM_SIZE 0x04000000
  209 +
  210 +#define CFG_FLASH_BASE PHYS_FLASH_1
  211 +
  212 +/*
  213 + * GPIO settings
  214 + */
  215 +#define CFG_GPSR0_VAL 0x00018000
  216 +#define CFG_GPSR1_VAL 0x00000000
  217 +#define CFG_GPSR2_VAL 0x400dc000
  218 +#define CFG_GPSR3_VAL 0x00000000
  219 +#define CFG_GPCR0_VAL 0x00000000
  220 +#define CFG_GPCR1_VAL 0x00000000
  221 +#define CFG_GPCR2_VAL 0x00000000
  222 +#define CFG_GPCR3_VAL 0x00000000
  223 +#define CFG_GPDR0_VAL 0x00018000
  224 +#define CFG_GPDR1_VAL 0x00028801
  225 +#define CFG_GPDR2_VAL 0x520dc000
  226 +#define CFG_GPDR3_VAL 0x0001E000
  227 +#define CFG_GAFR0_L_VAL 0x801c0000
  228 +#define CFG_GAFR0_U_VAL 0x00000013
  229 +#define CFG_GAFR1_L_VAL 0x6990100A
  230 +#define CFG_GAFR1_U_VAL 0x00000008
  231 +#define CFG_GAFR2_L_VAL 0xA0000000
  232 +#define CFG_GAFR2_U_VAL 0x010900F2
  233 +#define CFG_GAFR3_L_VAL 0x54000003
  234 +#define CFG_GAFR3_U_VAL 0x00002401
  235 +#define CFG_GRER0_VAL 0x00000000
  236 +#define CFG_GRER1_VAL 0x00000000
  237 +#define CFG_GRER2_VAL 0x00000000
  238 +#define CFG_GRER3_VAL 0x00000000
  239 +#define CFG_GFER0_VAL 0x00000000
  240 +#define CFG_GFER1_VAL 0x00000000
  241 +#define CFG_GFER2_VAL 0x00000000
  242 +#define CFG_GFER3_VAL 0x00000020
  243 +
  244 +
  245 +#define CFG_PSSR_VAL 0x20 /* CHECK */
  246 +
  247 +/*
  248 + * Clock settings
  249 + */
  250 +#define CFG_CKEN 0x01FFFFFF /* CHECK */
  251 +#define CFG_CCCR 0x02000290 /* 520Mhz */
  252 +
  253 +/*
  254 + * Memory settings
  255 + */
  256 +
  257 +#define CFG_MSC0_VAL 0x4df84df0
  258 +#define CFG_MSC1_VAL 0x7ff87ff4
  259 +#define CFG_MSC2_VAL 0xa26936d4
  260 +#define CFG_MDCNFG_VAL 0x880009C9
  261 +#define CFG_MDREFR_VAL 0x20ca201e
  262 +#define CFG_MDMRS_VAL 0x00220022
  263 +
  264 +#define CFG_FLYCNFG_VAL 0x00000000
  265 +#define CFG_SXCNFG_VAL 0x40044004
  266 +
  267 +/*
  268 + * PCMCIA and CF Interfaces
  269 + */
  270 +#define CFG_MECR_VAL 0x00000001
  271 +#define CFG_MCMEM0_VAL 0x00004204
  272 +#define CFG_MCMEM1_VAL 0x00010204
  273 +#define CFG_MCATT0_VAL 0x00010504
  274 +#define CFG_MCATT1_VAL 0x00010504
  275 +#define CFG_MCIO0_VAL 0x00008407
  276 +#define CFG_MCIO1_VAL 0x0000c108
  277 +
  278 +#define CONFIG_DRIVER_DM9000 1
  279 +#define CONFIG_DRIVER_DM9000 1
  280 +#define CONFIG_DM9000_BASE 0x08000000
  281 +#define DM9000_IO CONFIG_DM9000_BASE
  282 +#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
  283 +/* #define CONFIG_DM9000_USE_8BIT */
  284 +/* #define CONFIG_DM9000_USE_16BIT */
  285 +#define CONFIG_DM9000_USE_32BIT
  286 +
  287 +#define CONFIG_USB_OHCI_NEW 1
  288 +#define CFG_USB_OHCI_BOARD_INIT 1
  289 +#define CFG_USB_OHCI_MAX_ROOT_PORTS 3
  290 +#define CFG_USB_OHCI_REGS_BASE 0x4C000000
  291 +#define CFG_USB_OHCI_SLOT_NAME "trizepsiv"
  292 +#define CONFIG_USB_STORAGE 1
  293 +#define CFG_USB_OHCI_CPU_INIT 1
  294 +
  295 +/*
  296 + * FLASH and environment organization
  297 + */
  298 +
  299 +#define CFG_FLASH_CFI
  300 +#define CFG_FLASH_CFI_DRIVER 1
  301 +
  302 +#define CFG_MONITOR_BASE 0
  303 +#define CFG_MONITOR_LEN 0x40000
  304 +
  305 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  306 +#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
  307 +
  308 +/* timeout values are in ticks */
  309 +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
  310 +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
  311 +
  312 +/* write flash less slowly */
  313 +#define CFG_FLASH_USE_BUFFER_WRITE 1
  314 +
  315 +/* Flash environment locations */
  316 +#define CFG_ENV_IS_IN_FLASH 1
  317 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */
  318 +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */
  319 +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
  320 +
  321 +/* Address and size of Redundant Environment Sector */
  322 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
  323 +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
  324 +
  325 +#endif /* __CONFIG_H */