ARM: OMAP5-uevm: Add USB ehci support for the uEVM

Add the USB ehci support for the OMAP5 uEVM. Configure the uEVM mux data Add the flags to build the appropriate modules Add the usb call backs to initialize the EHCI controller Signed-off-by: Dan Murphy <dmurphy@ti.com>

ARM: OMAP5-uevm: Add USB ehci support for the uEVM
Add the USB ehci support for the OMAP5 uEVM. Configure the uEVM mux data Add the flags to build the appropriate modules Add the usb call backs to initialize the EHCI controller Signed-off-by: Dan Murphy <dmurphy@ti.com>
Dan Murphy · Marek Vasut
1 parent 120503f32e
Showing 3 changed files with 87 additions and 1 deletions Side-by-side Diff
board/ti/omap5_uevm/evm.c
board/ti/omap5_uevm/mux_data.h
include/configs/omap5_uevm.h
@@ -14,6 +14,13 @@
  
 #include "mux_data.h"
  
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ehci.h>
+#include <asm/ehci-omap.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
  
 const struct omap_sysinfo sysinfo = {
@@ -107,6 +114,59 @@
 	omap_mmc_init(0, 0, 0, -1, -1);
 	omap_mmc_init(1, 0, 0, -1, -1);
 	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI
+static struct omap_usbhs_board_data usbhs_bdata = {
+	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+	.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
+	.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
+};
+
+static void enable_host_clocks(void)
+{
+	int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
+				OPTFCLKEN_HSIC480M_P3_CLK |
+				OPTFCLKEN_HSIC60M_P2_CLK |
+				OPTFCLKEN_HSIC480M_P2_CLK |
+				OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
+
+	/* Enable port 2 and 3 clocks*/
+	setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
+
+	/* Enable port 2 and 3 usb host ports tll clocks*/
+	setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
+			(OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
+}
+
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+	int ret;
+	int auxclk;
+
+	enable_host_clocks();
+
+	auxclk = readl((*prcm)->scrm_auxclk1);
+	/* Request auxilary clock */
+	auxclk |= AUXCLK_ENABLE_MASK;
+	writel(auxclk, (*prcm)->scrm_auxclk1);
+
+	ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+	if (ret < 0) {
+		puts("Failed to initialize ehci\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+	int ret;
+
+	ret = omap_ehci_hcd_stop();
+	return ret;
 }
 #endif
@@ -42,7 +42,8 @@
 	{USBD0_SS_RX, (IEN | M0)},	/*  USBD0_SS_RX */
 	{I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
 	{I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
-
+	{HSI2_ACWAKE, (PTU | M6)},    /*  HSI2_ACWAKE */
+	{HSI2_CAFLAG, (PTU | M6)},    /*  HSI2_CAFLAG */
 };
  
 const struct pad_conf_entry wkup_padconf_array_essential[] = {
@@ -50,6 +51,7 @@
 	{SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
 	{SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
 	{SYS_32K, (IEN | M0)}, /*  SYS_32K     */
+	{FREF_CLK1_OUT, (PTD | IEN | M0)},    /*  FREF_CLK1_OUT  */
  
 };
  
@@ -40,6 +40,30 @@
 #define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4
 #define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
  
+/* USB UHH support options */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
+#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
+
+/* Enabled commands */
+#define CONFIG_NET_MULTI
+#define CONFIG_CMD_DHCP		/* DHCP Support			*/
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#define CONFIG_CMD_NFS		/* NFS support			*/
+
+/* USB Networking options */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
+#define CONFIG_SYS_PROMPT		"OMAP5432 uEVM # "
+
 #define CONSOLEDEV		"ttyO2"
 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
...	...	@@ -14,6 +14,13 @@
14	14
15	15	#include "mux_data.h"
16	16
	17	+#ifdef CONFIG_USB_EHCI
	18	+#include <usb.h>
	19	+#include <asm/arch/clock.h>
	20	+#include <asm/arch/ehci.h>
	21	+#include <asm/ehci-omap.h>
	22	+#endif
	23	+
17	24	DECLARE_GLOBAL_DATA_PTR;
18	25
19	26	const struct omap_sysinfo sysinfo = {
...	...	@@ -107,6 +114,59 @@
107	114	omap_mmc_init(0, 0, 0, -1, -1);
108	115	omap_mmc_init(1, 0, 0, -1, -1);
109	116	return 0;
	117	+}
	118	+#endif
	119	+
	120	+#ifdef CONFIG_USB_EHCI
	121	+static struct omap_usbhs_board_data usbhs_bdata = {
	122	+ .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
	123	+ .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
	124	+ .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
	125	+};
	126	+
	127	+static void enable_host_clocks(void)
	128	+{
	129	+ int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK \|
	130	+ OPTFCLKEN_HSIC480M_P3_CLK \|
	131	+ OPTFCLKEN_HSIC60M_P2_CLK \|
	132	+ OPTFCLKEN_HSIC480M_P2_CLK \|
	133	+ OPTFCLKEN_UTMI_P3_CLK \| OPTFCLKEN_UTMI_P2_CLK);
	134	+
	135	+ /* Enable port 2 and 3 clocks*/
	136	+ setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
	137	+
	138	+ /* Enable port 2 and 3 usb host ports tll clocks*/
	139	+ setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
	140	+ (OPTFCLKEN_USB_CH1_CLK_ENABLE \| OPTFCLKEN_USB_CH2_CLK_ENABLE));
	141	+}
	142	+
	143	+int ehci_hcd_init(int index, struct ehci_hccr hccr, struct ehci_hcor hcor)
	144	+{
	145	+ int ret;
	146	+ int auxclk;
	147	+
	148	+ enable_host_clocks();
	149	+
	150	+ auxclk = readl((*prcm)->scrm_auxclk1);
	151	+ /* Request auxilary clock */
	152	+ auxclk \|= AUXCLK_ENABLE_MASK;
	153	+ writel(auxclk, (*prcm)->scrm_auxclk1);
	154	+
	155	+ ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
	156	+ if (ret < 0) {
	157	+ puts("Failed to initialize ehci\n");
	158	+ return ret;
	159	+ }
	160	+
	161	+ return 0;
	162	+}
	163	+
	164	+int ehci_hcd_stop(void)
	165	+{
	166	+ int ret;
	167	+
	168	+ ret = omap_ehci_hcd_stop();
	169	+ return ret;
110	170	}
111	171	#endif
...	...	@@ -42,7 +42,8 @@
42	42	{USBD0_SS_RX, (IEN \| M0)}, /* USBD0_SS_RX */
43	43	{I2C5_SCL, (IEN \| M0)}, /* I2C5_SCL */
44	44	{I2C5_SDA, (IEN \| M0)}, /* I2C5_SDA */
45		-
	45	+ {HSI2_ACWAKE, (PTU \| M6)}, /* HSI2_ACWAKE */
	46	+ {HSI2_CAFLAG, (PTU \| M6)}, /* HSI2_CAFLAG */
46	47	};
47	48
48	49	const struct pad_conf_entry wkup_padconf_array_essential[] = {
...	...	@@ -50,6 +51,7 @@
50	51	{SR_PMIC_SCL, (PTU \| IEN \| M0)}, /* SR_PMIC_SCL */
51	52	{SR_PMIC_SDA, (PTU \| IEN \| M0)}, /* SR_PMIC_SDA */
52	53	{SYS_32K, (IEN \| M0)}, /* SYS_32K */
	54	+ {FREF_CLK1_OUT, (PTD \| IEN \| M0)}, /* FREF_CLK1_OUT */
53	55
54	56	};
55	57
...	...	@@ -40,6 +40,30 @@
40	40	#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4
41	41	#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
42	42
	43	+/* USB UHH support options */
	44	+#define CONFIG_CMD_USB
	45	+#define CONFIG_USB_HOST
	46	+#define CONFIG_USB_EHCI
	47	+#define CONFIG_USB_EHCI_OMAP
	48	+#define CONFIG_USB_STORAGE
	49	+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
	50	+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	51	+
	52	+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
	53	+#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
	54	+
	55	+/* Enabled commands */
	56	+#define CONFIG_NET_MULTI
	57	+#define CONFIG_CMD_DHCP /* DHCP Support */
	58	+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	59	+#define CONFIG_CMD_NFS /* NFS support */
	60	+
	61	+/* USB Networking options */
	62	+#define CONFIG_USB_HOST_ETHER
	63	+#define CONFIG_USB_ETHER_SMSC95XX
	64	+
	65	+#define CONFIG_SYS_PROMPT "OMAP5432 uEVM # "
	66	+
43	67	#define CONSOLEDEV "ttyO2"
44	68	#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
45	69