Commit 5f22d88f82082019ce631bb7cb635bb075170c9c
Committed by
Stefano Babic
Stefano Babic
1 parent
ccbb18713b
Exists in
v2017.01-smarct4x
and in
37 other branches
imx: mx6qsabreauto: Change to use common GPMI IO clock function
Since a clock function setup_gpmi_io_clk is implemented for GPMI IO clock settings, change to use this common function in GPMI setup. Signed-off-by: Ye.Li <B37916@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
Showing 1 changed file with 2 additions and 23 deletions Side-by-side Diff
board/freescale/mx6qsabreauto/mx6qsabreauto.c
| ... | ... | @@ -311,30 +311,9 @@ |
| 311 | 311 | /* config gpmi nand iomux */ |
| 312 | 312 | imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); |
| 313 | 313 | |
| 314 | - /* gate ENFC_CLK_ROOT clock first,before clk source switch */ | |
| 315 | - clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); | |
| 316 | - clrbits_le32(&mxc_ccm->CCGR4, | |
| 317 | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); | |
| 318 | - | |
| 319 | - /* config gpmi and bch clock to 100 MHz */ | |
| 320 | - clrsetbits_le32(&mxc_ccm->cs2cdr, | |
| 321 | - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | | |
| 322 | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | | |
| 323 | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, | |
| 324 | - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | | |
| 314 | + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | | |
| 325 | 315 | MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | |
| 326 | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); | |
| 327 | - | |
| 328 | - /* enable ENFC_CLK_ROOT clock */ | |
| 329 | - setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); | |
| 330 | - | |
| 331 | - /* enable gpmi and bch clock gating */ | |
| 332 | - setbits_le32(&mxc_ccm->CCGR4, | |
| 333 | - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
| 334 | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
| 335 | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
| 336 | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
| 337 | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); | |
| 316 | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); | |
| 338 | 317 | |
| 339 | 318 | /* enable apbh clock gating */ |
| 340 | 319 | setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); |