Commit 5f603761c3de00423cad405e064cd2fc822feab1
Committed by
Tom Rini
Tom Rini
1 parent
49ec949091
Exists in
v2017.01-smarct4x
and in
37 other branches
ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well. Signed-off-by: Praveen Rao <prao@ti.com> Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Showing 3 changed files with 13 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/omap5/hwinit.c
| ... | ... | @@ -381,4 +381,11 @@ |
| 381 | 381 | rst_val |= rst_time; |
| 382 | 382 | writel(rst_val, (*prcm)->prm_rsttime); |
| 383 | 383 | } |
| 384 | + | |
| 385 | +void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, | |
| 386 | + u32 cpu_rev_comb, u32 cpu_variant, | |
| 387 | + u32 cpu_rev) | |
| 388 | +{ | |
| 389 | + omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl); | |
| 390 | +} |
arch/arm/include/asm/arch-omap5/sys_proto.h
include/configs/ti_omap5_common.h