Commit 60b295672d61fe79e6af3d9e4f3e8bd23bf3b4ad
Committed by
York Sun
York Sun
1 parent
3345d18d5b
Exists in
v2017.01-smarct4x
and in
37 other branches
powerpc: macros for e500mc timer regs added
For e500mc cores the watchdog timer period has to be set by means of a 6bit value, that defines the bit of the timebase counter used to signal a watchdog timer exception on its 0 to 1 transition. The macro used to set the watchdog period TCR_WP, was redefined for e500mc to support 6 WP setting. The parameter (x) given to the macro specifies the prescaling factor of the time base clock (fTB): watchdog_period = 1/fTB * 2^x Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
Showing 1 changed file with 5 additions and 0 deletions Side-by-side Diff
arch/powerpc/include/asm/processor.h
| ... | ... | @@ -378,11 +378,16 @@ |
| 378 | 378 | #else |
| 379 | 379 | #define SPRN_TCR 0x154 /* Book E Timer Control Register */ |
| 380 | 380 | #endif /* CONFIG_BOOKE */ |
| 381 | +#ifdef CONFIG_E500MC | |
| 382 | +#define TCR_WP(x) (((64-x)&0x3)<<30)| \ | |
| 383 | + (((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/ | |
| 384 | +#else | |
| 381 | 385 | #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ |
| 382 | 386 | #define WP_2_17 0 /* 2^17 clocks */ |
| 383 | 387 | #define WP_2_21 1 /* 2^21 clocks */ |
| 384 | 388 | #define WP_2_25 2 /* 2^25 clocks */ |
| 385 | 389 | #define WP_2_29 3 /* 2^29 clocks */ |
| 390 | +#endif /* CONFIG_E500 */ | |
| 386 | 391 | #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ |
| 387 | 392 | #define WRC_NONE 0 /* No reset will occur */ |
| 388 | 393 | #define WRC_CORE 1 /* Core reset will occur */ |