Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels

The existing setting for rpll_sdiv generates 70.5Mhz RPLL video clock to drive 1366x768 panel on peach_pit. This clock rate is not sufficient to drive 1920x1080 panel on peach-pi. So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock which can drive peach-pi LCD. This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD divider at IP level will get set to 1(the required divider setting will be calculated and set by exynos_fimd_set_clock()) and hence peach-pit LCD still works fine. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels
The existing setting for rpll_sdiv generates 70.5Mhz RPLL video clock to drive 1366x768 panel on peach_pit. This clock rate is not sufficient to drive 1920x1080 panel on peach-pi. So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock which can drive peach-pi LCD. This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD divider at IP level will get set to 1(the required divider setting will be calculated and set by exynos_fimd_set_clock()) and hence peach-pit LCD still works fine. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Ajay Kumar · Minkyu Kang
1 parent 70b4fb660d
Showing 1 changed file with 2 additions and 2 deletions Side-by-side Diff
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -179,10 +179,10 @@
 		.spll_mdiv = 0xc8,
 		.spll_pdiv = 0x3,
 		.spll_sdiv = 0x2,
-		/* RPLL @70.5Mhz */
+		/* RPLL @141Mhz */
 		.rpll_mdiv = 0x5E,
 		.rpll_pdiv = 0x2,
-		.rpll_sdiv = 0x4,
+		.rpll_sdiv = 0x3,
  
 		.direct_cmd_msr = {
 			0x00020018, 0x00030000, 0x00010046, 0x00000d70,
...	...	@@ -179,10 +179,10 @@
179	179	.spll_mdiv = 0xc8,
180	180	.spll_pdiv = 0x3,
181	181	.spll_sdiv = 0x2,
182		- /* RPLL @70.5Mhz */
	182	+ /* RPLL @141Mhz */
183	183	.rpll_mdiv = 0x5E,
184	184	.rpll_pdiv = 0x2,
185		- .rpll_sdiv = 0x4,
	185	+ .rpll_sdiv = 0x3,
186	186
187	187	.direct_cmd_msr = {
188	188	0x00020018, 0x00030000, 0x00010046, 0x00000d70,