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Commit 615f0cba584d11944b43af03cc6d9324fc7587e3

Authored by York Sun
Committed by Andy Fleming
1 parent eb80880eb2
Exists in master and in 53 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

powerpc/mpc85xx: Fix PIR parsing for chassis2 

The PIR parsing algorithm we used is not only for E6500. It applies to all
SoCs with chassis 2.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Showing 1 changed file with 3 additions and 3 deletions Side-by-side Diff

arch/powerpc/cpu/mpc85xx/release.S
Diff comments   View file @ 615f0cb
... ... @@ -159,9 +159,9 @@
159 159 * we cannot access it yet before setting up a new TLB
160 160 */
161 161 mfspr r0,SPRN_PIR
162   -#if defined(CONFIG_E6500)
  162 +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
163 163 /*
164   - * PIR definition for E6500
  164 + * PIR definition for Chassis 2
165 165 * 0-17 Reserved (logic 0s)
166 166 * 8-19 CHIP_ID, 2'b00 - SoC 1
167 167 * all others - reserved
... ... @@ -187,7 +187,7 @@
187 187 slwi r8,r4,6 /* spin table is padded to 64 byte */
188 188 add r10,r3,r8
189 189  
190   -#ifdef CONFIG_E6500
  190 +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
191 191 mfspr r0,SPRN_PIR
192 192 /*
193 193 * core 0 thread 0: pir reset value 0x00, new pir 0