Commit 6195c47b8d8b8987ed514f9ce8c51da2653ced90
1 parent
84c7771c4b
Exists in
smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga
and in
4 other branches
MLK-21055 usb: dwc3: gadget: disable U1 and U2
Currenlty U1 and U2 low power modes are allowed in device mode. Allowing U1 and U2 low power modes during data transfers in device mode is causing U1 exit failure on some USB3 host: which will transite to SS.inactive instead of U0, then host will send warm reset and ultimately result in reenumeration. This is observed on UUU tool with some PC host. Hence disable U1 and U2 low power modes for now. USB3 spec 7.5.10.4.2 Exit from Recovery.Configuration The port shall transition to eSS.Inactive when the following conditions are met: 1. Either the Ux_EXIT_TIMER or the 6-ms timer (tRecoveryConfigurationTimeout) times out. 2. For a downstream port, the transition to Recovery is not to attempt a Hot Reset. Signed-off-by: Li Jun <jun.li@nxp.com> (cherry picked from commit ae0cdc741f7313398539f7b576ced73871f6cd71)
Showing 2 changed files with 5 additions and 25 deletions Side-by-side Diff
drivers/usb/dwc3/ep0.c
| ... | ... | @@ -391,7 +391,6 @@ |
| 391 | 391 | u32 recip; |
| 392 | 392 | u32 wValue; |
| 393 | 393 | u32 wIndex; |
| 394 | - u32 reg; | |
| 395 | 394 | int ret; |
| 396 | 395 | enum usb_device_state state; |
| 397 | 396 | |
| 398 | 397 | |
| 399 | 398 | |
| ... | ... | @@ -415,27 +414,12 @@ |
| 415 | 414 | return -EINVAL; |
| 416 | 415 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) |
| 417 | 416 | return -EINVAL; |
| 418 | - | |
| 419 | - reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
| 420 | - if (set) | |
| 421 | - reg |= DWC3_DCTL_INITU1ENA; | |
| 422 | - else | |
| 423 | - reg &= ~DWC3_DCTL_INITU1ENA; | |
| 424 | - dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
| 425 | 417 | break; |
| 426 | - | |
| 427 | 418 | case USB_DEVICE_U2_ENABLE: |
| 428 | 419 | if (state != USB_STATE_CONFIGURED) |
| 429 | 420 | return -EINVAL; |
| 430 | 421 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) |
| 431 | 422 | return -EINVAL; |
| 432 | - | |
| 433 | - reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
| 434 | - if (set) | |
| 435 | - reg |= DWC3_DCTL_INITU2ENA; | |
| 436 | - else | |
| 437 | - reg &= ~DWC3_DCTL_INITU2ENA; | |
| 438 | - dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
| 439 | 423 | break; |
| 440 | 424 | |
| 441 | 425 | case USB_DEVICE_LTM_ENABLE: |
| ... | ... | @@ -539,7 +523,6 @@ |
| 539 | 523 | enum usb_device_state state = dwc->gadget.state; |
| 540 | 524 | u32 cfg; |
| 541 | 525 | int ret; |
| 542 | - u32 reg; | |
| 543 | 526 | |
| 544 | 527 | dwc->start_config_issued = false; |
| 545 | 528 | cfg = le16_to_cpu(ctrl->wValue); |
| ... | ... | @@ -562,14 +545,6 @@ |
| 562 | 545 | if (ret == 0) |
| 563 | 546 | usb_gadget_set_state(&dwc->gadget, |
| 564 | 547 | USB_STATE_CONFIGURED); |
| 565 | - | |
| 566 | - /* | |
| 567 | - * Enable transition to U1/U2 state when | |
| 568 | - * nothing is pending from application. | |
| 569 | - */ | |
| 570 | - reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
| 571 | - reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); | |
| 572 | - dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
| 573 | 548 | |
| 574 | 549 | dwc->resize_fifos = true; |
| 575 | 550 | dev_dbg(dwc->dev, "resize FIFOs flag SET"); |
drivers/usb/dwc3/gadget.c
| ... | ... | @@ -2563,6 +2563,7 @@ |
| 2563 | 2563 | int dwc3_gadget_init(struct dwc3 *dwc) |
| 2564 | 2564 | { |
| 2565 | 2565 | int ret; |
| 2566 | + u32 reg; | |
| 2566 | 2567 | |
| 2567 | 2568 | dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req), |
| 2568 | 2569 | (unsigned long *)&dwc->ctrl_req_addr); |
| ... | ... | @@ -2620,6 +2621,10 @@ |
| 2620 | 2621 | dev_err(dwc->dev, "failed to register udc\n"); |
| 2621 | 2622 | goto err4; |
| 2622 | 2623 | } |
| 2624 | + | |
| 2625 | + reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
| 2626 | + reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA); | |
| 2627 | + dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
| 2623 | 2628 | |
| 2624 | 2629 | return 0; |
| 2625 | 2630 |