Eric Lee / smarc-uboot

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Commit 61a21e980a7b9188424d04f1c265fdc5c21c7e85

Authored by Andy Fleming
Committed by Andrew Fleming-AFLEMING
1 parent 7bd30fc4a6
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

85xx start.S cleanup and exception support 

From: Ed Swarthout <Ed.Swarthout@freescale.com>

Support external interrupts from platform to eliminate system hangs.
Define CONFIG_INTERRUPTS board configure option to enable.
Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.

Remove extra cpu initialization redundant with hardware initialization.
Whitespace cleanup.

Define and use _START_OFFSET consistent with other processors using
ppc_asm.tmpl

Move additional code from .text to boot page to make room for
exception vectors at start of image.

Handle Machine Check, External and Critical exceptions.

Fix e500 machine check error determination in traps.c

TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

Showing 5 changed files with 326 additions and 302 deletions Side-by-side Diff

cpu/mpc85xx/interrupts.c
Diff comments   View file @ 61a21e9
... ... @@ -89,6 +89,39 @@
89 89 mtspr(SPRN_TCR, TCR_PIE);
90 90 set_dec (decrementer_count);
91 91 set_msr (get_msr () | MSR_EE);
  92 +
  93 +#ifdef CONFIG_INTERRUPTS
  94 + volatile ccsr_pic_t *pic = &immr->im_pic;
  95 +
  96 + pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */
  97 + debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1);
  98 +
  99 + pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
  100 + debug("iivpr2@%x = %x\n",&pic->iivpr2, pic->iivpr2);
  101 +
  102 + pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
  103 + debug("iivpr3@%x = %x\n",&pic->iivpr3, pic->iivpr3);
  104 +
  105 +#ifdef CONFIG_PCI1
  106 + pic->iivpr8 = 0x810008; /* enable pci1 interrupts */
  107 + debug("iivpr8@%x = %x\n",&pic->iivpr8, pic->iivpr8);
  108 +#endif
  109 +#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
  110 + pic->iivpr9 = 0x810009; /* enable pci1 interrupts */
  111 + debug("iivpr9@%x = %x\n",&pic->iivpr9, pic->iivpr9);
  112 +#endif
  113 +#ifdef CONFIG_PCIE1
  114 + pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */
  115 + debug("iivpr10@%x = %x\n",&pic->iivpr10, pic->iivpr10);
  116 +#endif
  117 +#ifdef CONFIG_PCIE3
  118 + pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */
  119 + debug("iivpr11@%x = %x\n",&pic->iivpr11, pic->iivpr11);
  120 +#endif
  121 +
  122 + pic->ctpr=0; /* 40080 clear current task priority register */
  123 +#endif
  124 +
92 125 return (0);
93 126 }
94 127  
1 1 /*
2   - * Copyright 2004 Freescale Semiconductor.
  2 + * Copyright 2004, 2007 Freescale Semiconductor.
3 3 * Copyright (C) 2003 Motorola,Inc.
4   - * Xianghua Xiao<X.Xiao@motorola.com>
5 4 *
6 5 * See file CREDITS for list of people who contributed to this
7 6 * project.
... ... @@ -46,7 +45,7 @@
46 45 #endif
47 46  
48 47 #undef MSR_KERNEL
49   -#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
  48 +#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
50 49  
51 50 /*
52 51 * Set up GOT: Global Offset Table
53 52  
54 53  
55 54  
56 55  
57 56  
58 57  
59 58  
60 59  
61 60  
62 61  
... ... @@ -80,110 +79,37 @@
80 79 *
81 80 */
82 81  
83   - .section .bootpg,"ax"
84   - .globl _start_e500
  82 + .section .bootpg,"ax"
  83 + .globl _start_e500
85 84  
86 85 _start_e500:
87   - mfspr r0, PVR
88   - lis r1, PVR_85xx_REV1@h
89   - ori r1, r1, PVR_85xx_REV1@l
90   - cmpw r0, r1
91   - bne 1f
92 86  
93   - /* Semi-bogus errata fixup for Rev 1 */
94   - li r0,0x2000
95   - mtspr 977,r0
  87 +/* clear registers/arrays not reset by hardware */
96 88  
97   - /*
98   - * Before invalidating MMU L1/L2, read TLB1 Entry 0 and then
99   - * write it back immediately to fixup a Rev 1 bug (Errata CPU4)
100   - * for this initial TLB1 entry 0, otherwise the TLB1 entry 0
101   - * will be invalidated (incorrectly).
102   - */
103   - lis r2,0x1000
104   - mtspr MAS0,r2
105   - tlbre
106   - tlbwe
107   - isync
  89 + /* L1 */
  90 + li r0,2
  91 + mtspr L1CSR0,r0 /* invalidate d-cache */
  92 + mtspr L1CSR1,r0 /* invalidate i-cache */
108 93  
109   -1:
  94 + mfspr r1,DBSR
  95 + mtspr DBSR,r1 /* Clear all valid bits */
  96 +
110 97 /*
111   - * Clear and set up some registers.
112   - * Note: Some registers need strict synchronization by
113   - * sync/mbar/msync/isync when being "mtspr".
114   - * BookE: isync before PID,tlbivax,tlbwe
115   - * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe
116   - * E500: msync,isync before L1CSR0
117   - * E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1,
118   - * L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2],
119   - * SPEFCSR
  98 + * Enable L1 Caches early
  99 + *
120 100 */
121 101  
122   - /* invalidate d-cache */
123   - mfspr r0,L1CSR0
124   - ori r0,r0,0x0002
125   - msync
  102 + lis r2,L1CSR0_CPE@H /* enable parity */
  103 + ori r2,r2,L1CSR0_DCE
  104 + mtspr L1CSR0,r2 /* enable L1 Dcache */
126 105 isync
127   - mtspr L1CSR0,r0
  106 + mtspr L1CSR1,r2 /* enable L1 Icache */
128 107 isync
  108 + msync
129 109  
130   - /* disable d-cache */
131   - li r0,0x0
132   - mtspr L1CSR0,r0
133   -
134   - /* invalidate i-cache */
135   - mfspr r0,L1CSR1
136   - ori r0,r0,0x0002
137   - mtspr L1CSR1,r0
138   - isync
139   -
140   - /* disable i-cache */
141   - li r0,0x0
142   - mtspr L1CSR1,r0
143   - isync
144   -
145   - /* clear registers */
146   - li r0,0
147   - mtspr SRR0,r0
148   - mtspr SRR1,r0
149   - mtspr CSRR0,r0
150   - mtspr CSRR1,r0
151   - mtspr MCSRR0,r0
152   - mtspr MCSRR1,r0
153   -
154   - mtspr ESR,r0
155   - mtspr MCSR,r0
156   - mtspr DEAR,r0
157   -
158   - /* not needed and conflicts with some debuggers */
159   - /* mtspr DBCR0,r0 */
160   - mtspr DBCR1,r0
161   - mtspr DBCR2,r0
162   - /* not needed and conflicts with some debuggers */
163   - /* mtspr IAC1,r0 */
164   - /* mtspr IAC2,r0 */
165   - mtspr DAC1,r0
166   - mtspr DAC2,r0
167   -
168   - mfspr r1,DBSR
169   - mtspr DBSR,r1 /* Clear all valid bits */
170   -
171   - mtspr PID0,r0
172   - mtspr PID1,r0
173   - mtspr PID2,r0
174   - mtspr TCR,r0
175   -
176   - mtspr BUCSR,r0 /* disable branch prediction */
177   - mtspr MAS4,r0
178   - mtspr MAS6,r0
179   -#if defined(CONFIG_ENABLE_36BIT_PHYS)
180   - mtspr MAS7,r0
181   -#endif
182   - isync
183   -
184 110 /* Setup interrupt vectors */
185 111 lis r1,TEXT_BASE@h
186   - mtspr IVPR, r1
  112 + mtspr IVPR,r1
187 113  
188 114 li r1,0x0100
189 115 mtspr IVOR0,r1 /* 0: Critical input */
190 116  
... ... @@ -217,28 +143,8 @@
217 143 li r1,0x0f00
218 144 mtspr IVOR15,r1 /* 15: Debug */
219 145  
220   - /*
221   - * Invalidate MMU L1/L2
222   - *
223   - * Note: There is a fixup earlier for Errata CPU4 on
224   - * Rev 1 parts that must precede this MMU invalidation.
225   - */
226   - li r2, 0x001e
227   - mtspr MMUCSR0, r2
228   - isync
229 146  
230 147 /*
231   - * Invalidate all TLB0 entries.
232   - */
233   - li r3,4
234   - li r4,0
235   - tlbivax r4,r3
236   - /*
237   - * To avoid REV1 Errata CPU6 issues, make sure
238   - * the instruction following tlbivax is not a store.
239   - */
240   -
241   - /*
242 148 * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
243 149 * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
244 150 * region before we can access any CCSR registers such as L2
... ... @@ -254,14 +160,14 @@
254 160 lwzu r4,0(r5) /* how many TLB1 entries we actually use */
255 161 mtctr r4
256 162  
257   -0: lwzu r0,4(r5)
258   - lwzu r1,4(r5)
259   - lwzu r2,4(r5)
260   - lwzu r3,4(r5)
261   - mtspr MAS0,r0
262   - mtspr MAS1,r1
263   - mtspr MAS2,r2
264   - mtspr MAS3,r3
  163 +0: lwzu r6,4(r5)
  164 + lwzu r7,4(r5)
  165 + lwzu r8,4(r5)
  166 + lwzu r9,4(r5)
  167 + mtspr MAS0,r6
  168 + mtspr MAS1,r7
  169 + mtspr MAS2,r8
  170 + mtspr MAS3,r9
265 171 isync
266 172 msync
267 173 tlbwe
268 174  
269 175  
270 176  
271 177  
272 178  
... ... @@ -271,22 +177,22 @@
271 177 1:
272 178 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
273 179 /* Special sequence needed to update CCSRBAR itself */
274   - lis r4, CFG_CCSRBAR_DEFAULT@h
275   - ori r4, r4, CFG_CCSRBAR_DEFAULT@l
  180 + lis r4,CFG_CCSRBAR_DEFAULT@h
  181 + ori r4,r4,CFG_CCSRBAR_DEFAULT@l
276 182  
277   - lis r5, CFG_CCSRBAR@h
278   - ori r5, r5, CFG_CCSRBAR@l
  183 + lis r5,CFG_CCSRBAR@h
  184 + ori r5,r5,CFG_CCSRBAR@l
279 185 srwi r6,r5,12
280   - stw r6, 0(r4)
  186 + stw r6,0(r4)
281 187 isync
282 188  
283   - lis r5, 0xffff
  189 + lis r5,0xffff
284 190 ori r5,r5,0xf000
285   - lwz r5, 0(r5)
  191 + lwz r5,0(r5)
286 192 isync
287 193  
288   - lis r3, CFG_CCSRBAR@h
289   - lwz r5, CFG_CCSRBAR@l(r3)
  194 + lis r3,CFG_CCSRBAR@h
  195 + lwz r5,CFG_CCSRBAR@l(r3)
290 196 isync
291 197 #endif
292 198  
... ... @@ -300,8 +206,8 @@
300 206 lwzu r5,0(r6) /* how many windows we actually use */
301 207 mtctr r5
302 208  
303   - li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */
304   - li r1,0x0c30
  209 + li r2,0x0c28 /* the first pair is reserved for */
  210 + li r1,0x0c30 /* boot-over-rio-or-pci */
305 211  
306 212 0: lwzu r4,4(r6)
307 213 lwzu r3,4(r6)
... ... @@ -311,31 +217,6 @@
311 217 addi r1,r1,0x0020
312 218 bdnz 0b
313 219  
314   - /* Jump out the last 4K page and continue to 'normal' start */
315   -1: bl 3f
316   - b _start
317   -
318   -3: li r0,0
319   - mtspr SRR1,r0 /* Keep things disabled for now */
320   - mflr r1
321   - mtspr SRR0,r1
322   - rfi
323   -
324   -/*
325   - * r3 - 1st arg to board_init(): IMMP pointer
326   - * r4 - 2nd arg to board_init(): boot flag
327   - */
328   - .text
329   - .long 0x27051956 /* U-BOOT Magic Number */
330   - .globl version_string
331   -version_string:
332   - .ascii U_BOOT_VERSION
333   - .ascii " (", __DATE__, " - ", __TIME__, ")"
334   - .ascii CONFIG_IDENT_STRING, "\0"
335   -
336   - . = EXC_OFF_SYS_RESET
337   - .globl _start
338   -_start:
339 220 /* Clear and set up some registers. */
340 221 li r0,0x0000
341 222 lis r1,0xffff
342 223  
343 224  
... ... @@ -354,17 +235,14 @@
354 235  
355 236 /* Enable Time Base and Select Time Base Clock */
356 237 lis r0,HID0_EMCP@h /* Enable machine check */
357   - ori r0,r0,0x4000 /* time base is processor clock */
358 238 #if defined(CONFIG_ENABLE_36BIT_PHYS)
359   - ori r0,r0,0x0080 /* enable MAS7 updates */
  239 + ori r0,r0,(HID0_TBEN|HID0_ENMAS7)@l /* Enable Timebase & MAS7 */
  240 +#else
  241 + ori r0,r0,HID0_TBEN@l /* enable Timebase */
360 242 #endif
361 243 mtspr HID0,r0
362 244  
363   -#if defined(CONFIG_ADDR_STREAMING)
364   - li r0,0x3000
365   -#else
366   - li r0,0x1000
367   -#endif
  245 + li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
368 246 mtspr HID1,r0
369 247  
370 248 /* Enable Branch Prediction */
371 249  
372 250  
373 251  
374 252  
375 253  
376 254  
... ... @@ -382,35 +260,56 @@
382 260 mtspr DBCR0,r0
383 261 #endif
384 262  
385   -/* L1 DCache is used for initial RAM */
386   - mfspr r2, L1CSR0
387   - ori r2, r2, 0x0003
388   - oris r2, r2, 0x0001
389   - mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */
  263 + /* Jump out the last 4K page and continue to 'normal' start */
  264 + bl 3f
  265 + b _start_cont
  266 +
  267 +3: li r0,0
  268 + mtspr SRR1,r0 /* Keep things disabled for now */
  269 + mflr r1
  270 + mtspr SRR0,r1
  271 + rfi
390 272 isync
391 273  
  274 +
  275 + .text
  276 + .globl _start
  277 +_start:
  278 + .long 0x27051956 /* U-BOOT Magic Number */
  279 + .globl version_string
  280 +version_string:
  281 + .ascii U_BOOT_VERSION
  282 + .ascii " (", __DATE__, " - ", __TIME__, ")"
  283 + .ascii CONFIG_IDENT_STRING, "\0"
  284 +
  285 + .align 4
  286 + .globl _start_cont
  287 +_start_cont:
  288 +
  289 +/* L1 DCache is used for initial RAM */
  290 +
392 291 /* Allocate Initial RAM in data cache.
393 292 */
394   - lis r3, CFG_INIT_RAM_ADDR@h
395   - ori r3, r3, CFG_INIT_RAM_ADDR@l
396   - li r2, 512 /* 512*32=16K */
  293 + lis r3,CFG_INIT_RAM_ADDR@h
  294 + ori r3,r3,CFG_INIT_RAM_ADDR@l
  295 + li r2,512 /* 512*32=16K */
397 296 mtctr r2
398   - li r0, 0
  297 + li r0,0
399 298 1:
400   - dcbz r0, r3
401   - dcbtls 0,r0, r3
402   - addi r3, r3, 32
  299 + dcbz r0,r3
  300 + dcbtls 0,r0,r3
  301 + addi r3,r3,32
403 302 bdnz 1b
404 303  
405 304 #ifndef CFG_RAMBOOT
406 305 /* Calculate absolute address in FLASH and jump there */
407 306 /*--------------------------------------------------------------*/
408   - lis r3, CFG_MONITOR_BASE@h
409   - ori r3, r3, CFG_MONITOR_BASE@l
410   - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
  307 + lis r3,CFG_MONITOR_BASE@h
  308 + ori r3,r3,CFG_MONITOR_BASE@l
  309 + addi r3,r3,in_flash - _start + _START_OFFSET
411 310 mtlr r3
412 311 blr
413   -
  312 + .global in_flash
414 313 in_flash:
415 314 #endif /* CFG_RAMBOOT */
416 315  
417 316  
418 317  
419 318  
420 319  
421 320  
... ... @@ -424,27 +323,25 @@
424 323  
425 324 stwu r1,-8(r1) /* Save back chain and move SP */
426 325 lis r0,RESET_VECTOR@h /* Address of reset vector */
427   - ori r0,r0, RESET_VECTOR@l
  326 + ori r0,r0,RESET_VECTOR@l
428 327 stwu r1,-8(r1) /* Save back chain and move SP */
429 328 stw r0,+12(r1) /* Save return addr (underflow vect) */
430 329  
431 330 GET_GOT
432 331 bl cpu_init_f
433   - bl icache_enable
434 332 bl board_init_f
435 333 isync
436 334  
437   -/* --FIXME-- machine check with MCSRRn and rfmci */
438   -
  335 + . = EXC_OFF_SYS_RESET
439 336 .globl _start_of_vectors
440 337 _start_of_vectors:
441   -#if 0
  338 +
442 339 /* Critical input. */
443   - CRIT_EXCEPTION(0x0100, CritcalInput, CritcalInputException)
444   -#endif
445   -/* Machine check --FIXME-- Should be MACH_EXCEPTION */
446   - CRIT_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
  340 + CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
447 341  
  342 +/* Machine check */
  343 + MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  344 +
448 345 /* Data Storage exception. */
449 346 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
450 347  
... ... @@ -452,7 +349,7 @@
452 349 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
453 350  
454 351 /* External Interrupt exception. */
455   - STD_EXCEPTION(0x0500, ExtInterrupt, UnknownException)
  352 + STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
456 353  
457 354 /* Alignment exception. */
458 355 . = 0x0600
... ... @@ -469,8 +366,8 @@
469 366 mtlr r6
470 367 blrl
471 368 .L_Alignment:
472   - .long AlignmentException - _start + EXC_OFF_SYS_RESET
473   - .long int_return - _start + EXC_OFF_SYS_RESET
  369 + .long AlignmentException - _start + _START_OFFSET
  370 + .long int_return - _start + _START_OFFSET
474 371  
475 372 /* Program check exception */
476 373 . = 0x0700
... ... @@ -483,8 +380,8 @@
483 380 mtlr r6
484 381 blrl
485 382 .L_ProgramCheck:
486   - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
487   - .long int_return - _start + EXC_OFF_SYS_RESET
  383 + .long ProgramCheckException - _start + _START_OFFSET
  384 + .long int_return - _start + _START_OFFSET
488 385  
489 386 /* No FPU on MPC85xx. This exception is not supposed to happen.
490 387 */
491 388  
492 389  
493 390  
494 391  
495 392  
... ... @@ -496,23 +393,23 @@
496 393 * r3-... arguments
497 394 */
498 395 SystemCall:
499   - addis r11,r0,0 /* get functions table addr */
500   - ori r11,r11,0 /* Note: this code is patched in trap_init */
501   - addis r12,r0,0 /* get number of functions */
  396 + addis r11,r0,0 /* get functions table addr */
  397 + ori r11,r11,0 /* Note: this code is patched in trap_init */
  398 + addis r12,r0,0 /* get number of functions */
502 399 ori r12,r12,0
503 400  
504   - cmplw 0, r0, r12
  401 + cmplw 0,r0,r12
505 402 bge 1f
506 403  
507   - rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
  404 + rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
508 405 add r11,r11,r0
509 406 lwz r11,0(r11)
510 407  
511   - li r20,0xd00-4 /* Get stack pointer */
  408 + li r20,0xd00-4 /* Get stack pointer */
512 409 lwz r12,0(r20)
513   - subi r12,r12,12 /* Adjust stack pointer */
  410 + subi r12,r12,12 /* Adjust stack pointer */
514 411 li r0,0xc00+_end_back-SystemCall
515   - cmplw 0, r0, r12 /* Check stack overflow */
  412 + cmplw 0,r0,r12 /* Check stack overflow */
516 413 bgt 1f
517 414 stw r12,0(r20)
518 415  
... ... @@ -570,7 +467,7 @@
570 467 _end_of_vectors:
571 468  
572 469  
573   - . = 0x2100
  470 + . = . + (0x100 - ( . & 0xff )) /* align for debug */
574 471  
575 472 /*
576 473 * This code finishes saving the registers to the exception frame
577 474  
578 475  
579 476  
580 477  
... ... @@ -655,26 +552,58 @@
655 552 REST_GPR(31, r1)
656 553 lwz r2,_NIP(r1) /* Restore environment */
657 554 lwz r0,_MSR(r1)
658   - mtspr 990,r2 /* SRR2 */
659   - mtspr 991,r0 /* SRR3 */
  555 + mtspr SPRN_CSRR0,r2
  556 + mtspr SPRN_CSRR1,r0
660 557 lwz r0,GPR0(r1)
661 558 lwz r2,GPR2(r1)
662 559 lwz r1,GPR1(r1)
663 560 SYNC
664 561 rfci
665 562  
  563 +mck_return:
  564 + mfmsr r28 /* Disable interrupts */
  565 + li r4,0
  566 + ori r4,r4,MSR_EE
  567 + andc r28,r28,r4
  568 + SYNC /* Some chip revs need this... */
  569 + mtmsr r28
  570 + SYNC
  571 + lwz r2,_CTR(r1)
  572 + lwz r0,_LINK(r1)
  573 + mtctr r2
  574 + mtlr r0
  575 + lwz r2,_XER(r1)
  576 + lwz r0,_CCR(r1)
  577 + mtspr XER,r2
  578 + mtcrf 0xFF,r0
  579 + REST_10GPRS(3, r1)
  580 + REST_10GPRS(13, r1)
  581 + REST_8GPRS(23, r1)
  582 + REST_GPR(31, r1)
  583 + lwz r2,_NIP(r1) /* Restore environment */
  584 + lwz r0,_MSR(r1)
  585 + mtspr SPRN_MCSRR0,r2
  586 + mtspr SPRN_MCSRR1,r0
  587 + lwz r0,GPR0(r1)
  588 + lwz r2,GPR2(r1)
  589 + lwz r1,GPR1(r1)
  590 + SYNC
  591 + rfmci
  592 +
666 593 /* Cache functions.
667 594 */
668 595 invalidate_icache:
669 596 mfspr r0,L1CSR1
670   - ori r0,r0,0x0002
  597 + ori r0,r0,L1CSR1_ICFI
  598 + msync
  599 + isync
671 600 mtspr L1CSR1,r0
672 601 isync
673   - blr /* entire I cache */
  602 + blr /* entire I cache */
674 603  
675 604 invalidate_dcache:
676 605 mfspr r0,L1CSR0
677   - ori r0,r0,0x0002
  606 + ori r0,r0,L1CSR0_DCFI
678 607 msync
679 608 isync
680 609 mtspr L1CSR0,r0
... ... @@ -697,9 +626,9 @@
697 626 .globl icache_disable
698 627 icache_disable:
699 628 mfspr r0,L1CSR1
700   - lis r1,0xfffffffe@h
701   - ori r1,r1,0xfffffffe@l
702   - and r0,r0,r1
  629 + lis r3,0
  630 + ori r3,r3,L1CSR1_ICE
  631 + andc r0,r0,r3
703 632 mtspr L1CSR1,r0
704 633 isync
705 634 blr
... ... @@ -707,7 +636,7 @@
707 636 .globl icache_status
708 637 icache_status:
709 638 mfspr r3,L1CSR1
710   - andi. r3,r3,1
  639 + andi. r3,r3,L1CSR1_ICE
711 640 blr
712 641  
713 642 .globl dcache_enable
... ... @@ -727,12 +656,10 @@
727 656  
728 657 .globl dcache_disable
729 658 dcache_disable:
730   - mfspr r0,L1CSR0
731   - lis r1,0xfffffffe@h
732   - ori r1,r1,0xfffffffe@l
733   - and r0,r0,r1
734   - msync
735   - isync
  659 + mfspr r3,L1CSR0
  660 + lis r4,0
  661 + ori r4,r4,L1CSR0_DCE
  662 + andc r3,r3,r4
736 663 mtspr L1CSR0,r0
737 664 isync
738 665 blr
739 666  
740 667  
741 668  
742 669  
... ... @@ -740,27 +667,27 @@
740 667 .globl dcache_status
741 668 dcache_status:
742 669 mfspr r3,L1CSR0
743   - andi. r3,r3,1
  670 + andi. r3,r3,L1CSR0_DCE
744 671 blr
745 672  
746 673 .globl get_pir
747 674 get_pir:
748   - mfspr r3, PIR
  675 + mfspr r3,PIR
749 676 blr
750 677  
751 678 .globl get_pvr
752 679 get_pvr:
753   - mfspr r3, PVR
  680 + mfspr r3,PVR
754 681 blr
755 682  
756 683 .globl get_svr
757 684 get_svr:
758   - mfspr r3, SVR
  685 + mfspr r3,SVR
759 686 blr
760 687  
761 688 .globl wr_tcr
762 689 wr_tcr:
763   - mtspr TCR, r3
  690 + mtspr TCR,r3
764 691 blr
765 692  
766 693 /*------------------------------------------------------------------------------- */
767 694  
768 695  
... ... @@ -913,16 +840,16 @@
913 840 */
914 841 .globl relocate_code
915 842 relocate_code:
916   - mr r1, r3 /* Set new stack pointer */
917   - mr r9, r4 /* Save copy of Init Data pointer */
918   - mr r10, r5 /* Save copy of Destination Address */
  843 + mr r1,r3 /* Set new stack pointer */
  844 + mr r9,r4 /* Save copy of Init Data pointer */
  845 + mr r10,r5 /* Save copy of Destination Address */
919 846  
920   - mr r3, r5 /* Destination Address */
921   - lis r4, CFG_MONITOR_BASE@h /* Source Address */
922   - ori r4, r4, CFG_MONITOR_BASE@l
  847 + mr r3,r5 /* Destination Address */
  848 + lis r4,CFG_MONITOR_BASE@h /* Source Address */
  849 + ori r4,r4,CFG_MONITOR_BASE@l
923 850 lwz r5,GOT(__init_end)
924 851 sub r5,r5,r4
925   - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
  852 + li r6,CFG_CACHELINE_SIZE /* Cache Line Size */
926 853  
927 854 /*
928 855 * Fix GOT pointer:
929 856  
930 857  
... ... @@ -931,12 +858,12 @@
931 858 *
932 859 * Offset:
933 860 */
934   - sub r15, r10, r4
  861 + sub r15,r10,r4
935 862  
936 863 /* First our own GOT */
937   - add r14, r14, r15
  864 + add r14,r14,r15
938 865 /* the the one used by the C code */
939   - add r30, r30, r15
  866 + add r30,r30,r15
940 867  
941 868 /*
942 869 * Now relocate code
943 870  
... ... @@ -997,10 +924,10 @@
997 924 * initialization, now running from RAM.
998 925 */
999 926  
1000   - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
  927 + addi r0,r10,in_ram - _start + _START_OFFSET
1001 928 mtlr r0
1002 929 blr /* NEVER RETURNS! */
1003   -
  930 + .globl in_ram
1004 931 in_ram:
1005 932  
1006 933 /*
1007 934  
1008 935  
1009 936  
... ... @@ -1044,19 +971,19 @@
1044 971 lwz r3,GOT(__bss_start)
1045 972 lwz r4,GOT(_end)
1046 973  
1047   - cmplw 0, r3, r4
  974 + cmplw 0,r3,r4
1048 975 beq 6f
1049 976  
1050   - li r0, 0
  977 + li r0,0
1051 978 5:
1052   - stw r0, 0(r3)
1053   - addi r3, r3, 4
1054   - cmplw 0, r3, r4
  979 + stw r0,0(r3)
  980 + addi r3,r3,4
  981 + cmplw 0,r3,r4
1055 982 bne 5b
1056 983 6:
1057 984  
1058   - mr r3, r9 /* Init Data pointer */
1059   - mr r4, r10 /* Destination Address */
  985 + mr r3,r9 /* Init Data pointer */
  986 + mr r4,r10 /* Destination Address */
1060 987 bl board_init_r
1061 988  
1062 989 /*
1063 990  
1064 991  
1065 992  
1066 993  
1067 994  
1068 995  
1069 996  
1070 997  
1071 998  
1072 999  
1073 1000  
1074 1001  
1075 1002  
1076 1003  
... ... @@ -1067,52 +994,54 @@
1067 994 */
1068 995 .globl trap_init
1069 996 trap_init:
1070   - lwz r7, GOT(_start)
1071   - lwz r8, GOT(_end_of_vectors)
  997 + lwz r7,GOT(_start_of_vectors)
  998 + lwz r8,GOT(_end_of_vectors)
1072 999  
1073   - li r9, 0x100 /* reset vector always at 0x100 */
  1000 + li r9,0x100 /* reset vector always at 0x100 */
1074 1001  
1075   - cmplw 0, r7, r8
  1002 + cmplw 0,r7,r8
1076 1003 bgelr /* return if r7>=r8 - just in case */
1077 1004  
1078 1005 mflr r4 /* save link register */
1079 1006 1:
1080   - lwz r0, 0(r7)
1081   - stw r0, 0(r9)
1082   - addi r7, r7, 4
1083   - addi r9, r9, 4
1084   - cmplw 0, r7, r8
  1007 + lwz r0,0(r7)
  1008 + stw r0,0(r9)
  1009 + addi r7,r7,4
  1010 + addi r9,r9,4
  1011 + cmplw 0,r7,r8
1085 1012 bne 1b
1086 1013  
1087 1014 /*
1088 1015 * relocate `hdlr' and `int_return' entries
1089 1016 */
1090   - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
  1017 + li r7,.L_CriticalInput - _start + _START_OFFSET
1091 1018 bl trap_reloc
1092   - li r7, .L_DataStorage - _start + EXC_OFF_SYS_RESET
  1019 + li r7,.L_MachineCheck - _start + _START_OFFSET
1093 1020 bl trap_reloc
1094   - li r7, .L_InstStorage - _start + EXC_OFF_SYS_RESET
  1021 + li r7,.L_DataStorage - _start + _START_OFFSET
1095 1022 bl trap_reloc
1096   - li r7, .L_ExtInterrupt - _start + EXC_OFF_SYS_RESET
  1023 + li r7,.L_InstStorage - _start + _START_OFFSET
1097 1024 bl trap_reloc
1098   - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
  1025 + li r7,.L_ExtInterrupt - _start + _START_OFFSET
1099 1026 bl trap_reloc
1100   - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
  1027 + li r7,.L_Alignment - _start + _START_OFFSET
1101 1028 bl trap_reloc
1102   - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
  1029 + li r7,.L_ProgramCheck - _start + _START_OFFSET
1103 1030 bl trap_reloc
1104   - li r7, .L_Decrementer - _start + EXC_OFF_SYS_RESET
  1031 + li r7,.L_FPUnavailable - _start + _START_OFFSET
1105 1032 bl trap_reloc
1106   - li r7, .L_IntervalTimer - _start + EXC_OFF_SYS_RESET
1107   - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
  1033 + li r7,.L_Decrementer - _start + _START_OFFSET
  1034 + bl trap_reloc
  1035 + li r7,.L_IntervalTimer - _start + _START_OFFSET
  1036 + li r8,_end_of_vectors - _start + _START_OFFSET
1108 1037 2:
1109 1038 bl trap_reloc
1110   - addi r7, r7, 0x100 /* next exception vector */
1111   - cmplw 0, r7, r8
  1039 + addi r7,r7,0x100 /* next exception vector */
  1040 + cmplw 0,r7,r8
1112 1041 blt 2b
1113 1042  
1114 1043 lis r7,0x0
1115   - mtspr IVPR, r7
  1044 + mtspr IVPR,r7
1116 1045  
1117 1046 mtlr r4 /* restore link register */
1118 1047 blr
1119 1048  
... ... @@ -1121,13 +1050,13 @@
1121 1050 * Function: relocate entries for one exception vector
1122 1051 */
1123 1052 trap_reloc:
1124   - lwz r0, 0(r7) /* hdlr ... */
1125   - add r0, r0, r3 /* ... += dest_addr */
1126   - stw r0, 0(r7)
  1053 + lwz r0,0(r7) /* hdlr ... */
  1054 + add r0,r0,r3 /* ... += dest_addr */
  1055 + stw r0,0(r7)
1127 1056  
1128   - lwz r0, 4(r7) /* int_return ... */
1129   - add r0, r0, r3 /* ... += dest_addr */
1130   - stw r0, 4(r7)
  1057 + lwz r0,4(r7) /* int_return ... */
  1058 + add r0,r0,r3 /* ... += dest_addr */
  1059 + stw r0,4(r7)
1131 1060  
1132 1061 blr
1133 1062  
... ... @@ -1135,13 +1064,13 @@
1135 1064 .globl unlock_ram_in_cache
1136 1065 unlock_ram_in_cache:
1137 1066 /* invalidate the INIT_RAM section */
1138   - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1139   - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1140   - li r2,512
1141   - mtctr r2
1142   -1: icbi r0, r3
1143   - dcbi r0, r3
1144   - addi r3, r3, 32
  1067 + lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
  1068 + ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
  1069 + li r4,512
  1070 + mtctr r4
  1071 +1: icbi r0,r3
  1072 + dcbi r0,r3
  1073 + addi r3,r3,32
1145 1074 bdnz 1b
1146 1075 sync /* Wait for all icbi to complete on bus */
1147 1076 isync
1 1 /*
2 2 * linux/arch/ppc/kernel/traps.c
3 3 *
  4 + * Copyright 2007 Freescale Semiconductor.
4 5 * Copyright (C) 2003 Motorola
5 6 * Modified by Xianghua Xiao(x.xiao@motorola.com)
6 7 *
7 8  
... ... @@ -145,10 +146,13 @@
145 146 panic("Critical Input Exception");
146 147 }
147 148  
  149 +int machinecheck_count = 0;
  150 +int machinecheck_error = 0;
148 151 void
149 152 MachineCheckException(struct pt_regs *regs)
150 153 {
151 154 unsigned long fixup;
  155 + unsigned int mcsr, mcsrr0, mcsrr1, mcar;
152 156  
153 157 /* Probing PCI using config cycles cause this exception
154 158 * when a device is not present. Catch it and return to
155 159  
156 160  
157 161  
... ... @@ -159,34 +163,62 @@
159 163 return;
160 164 }
161 165  
  166 + mcsrr0 = mfspr(SPRN_MCSRR0);
  167 + mcsrr1 = mfspr(SPRN_MCSRR1);
  168 + mcsr = mfspr(SPRN_MCSR);
  169 + mcar = mfspr(SPRN_MCAR);
  170 +
  171 + machinecheck_count++;
  172 + machinecheck_error=1;
  173 +
162 174 #if defined(CONFIG_CMD_KGDB)
163 175 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
164 176 return;
165 177 #endif
166 178  
167 179 printf("Machine check in kernel mode.\n");
168   - printf("Caused by (from msr): ");
169   - printf("regs %p ",regs);
170   - switch( regs->msr & 0x000F0000) {
171   - case (0x80000000>>12):
172   - printf("Machine check signal - probably due to mm fault\n"
173   - "with mmu off\n");
174   - break;
175   - case (0x80000000>>13):
176   - printf("Transfer error ack signal\n");
177   - break;
178   - case (0x80000000>>14):
179   - printf("Data parity signal\n");
180   - break;
181   - case (0x80000000>>15):
182   - printf("Address parity signal\n");
183   - break;
184   - default:
185   - printf("Unknown values in msr\n");
186   - }
  180 + printf("Caused by (from mcsr): ");
  181 + printf("mcsr = 0x%08x\n", mcsr);
  182 + if (mcsr & 0x80000000)
  183 + printf("Machine check input pin\n");
  184 + if (mcsr & 0x40000000)
  185 + printf("Instruction cache parity error\n");
  186 + if (mcsr & 0x20000000)
  187 + printf("Data cache push parity error\n");
  188 + if (mcsr & 0x10000000)
  189 + printf("Data cache parity error\n");
  190 + if (mcsr & 0x00000080)
  191 + printf("Bus instruction address error\n");
  192 + if (mcsr & 0x00000040)
  193 + printf("Bus Read address error\n");
  194 + if (mcsr & 0x00000020)
  195 + printf("Bus Write address error\n");
  196 + if (mcsr & 0x00000010)
  197 + printf("Bus Instruction data bus error\n");
  198 + if (mcsr & 0x00000008)
  199 + printf("Bus Read data bus error\n");
  200 + if (mcsr & 0x00000004)
  201 + printf("Bus Write bus error\n");
  202 + if (mcsr & 0x00000002)
  203 + printf("Bus Instruction parity error\n");
  204 + if (mcsr & 0x00000001)
  205 + printf("Bus Read parity error\n");
  206 +
187 207 show_regs(regs);
  208 + printf("MCSR=0x%08x \tMCSRR0=0x%08x \nMCSRR1=0x%08x \tMCAR=0x%08x\n",
  209 + mcsr, mcsrr0, mcsrr1, mcar);
188 210 print_backtrace((unsigned long *)regs->gpr[1]);
189   - panic("machine check");
  211 + if (machinecheck_count > 10) {
  212 + panic("machine check count too high\n");
  213 + }
  214 +
  215 + if (machinecheck_count > 1) {
  216 + regs->nip += 4; /* skip offending instruction */
  217 + printf("Skipping current instr, Returning to 0x%08x\n",
  218 + regs->nip);
  219 + } else {
  220 + printf("Returning back to 0x%08x\n",regs->nip);
  221 + }
190 222 }
191 223  
192 224 void
... ... @@ -252,6 +284,33 @@
252 284 printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
253 285 regs->nip, regs->msr, regs->trap);
254 286 _exception(0, regs);
  287 +}
  288 +void
  289 +ExtIntException(struct pt_regs *regs)
  290 +{
  291 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  292 + volatile ccsr_pic_t *pic = &immap->im_pic;
  293 + uint vect;
  294 +
  295 +#if defined(CONFIG_CMD_KGDB)
  296 + if (debugger_exception_handler && (*debugger_exception_handler)(regs))
  297 + return;
  298 +#endif
  299 +
  300 + printf("External Interrupt Exception at PC: %lx, SR: %lx, vector=%lx",
  301 + regs->nip, regs->msr, regs->trap);
  302 + vect = pic->iack0;
  303 + printf(" irq IACK0@%05x=%d\n",&pic->iack0,vect);
  304 + show_regs(regs);
  305 + print_backtrace((unsigned long *)regs->gpr[1]);
  306 + machinecheck_count++;
  307 +#ifdef EXTINT_NOSKIP
  308 + printf("Returning back to 0x%08x\n",regs->nip);
  309 +#else
  310 + regs->nip += 4; /* skip offending instruction */
  311 + printf("Skipping current instr, Returning to 0x%08x\n",regs->nip);
  312 +#endif
  313 +
255 314 }
256 315  
257 316 void
include/asm-ppc/processor.h
Diff comments   View file @ 61a21e9
... ... @@ -217,12 +217,14 @@
217 217 #define HID0_DPM (1<<20)
218 218 #define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
219 219 #define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
  220 +#define HID0_TBEN (1<<14) /* Time Base Enable */
220 221 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
221 222 #define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
222 223 #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
223 224 #define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
224 225 #define HID0_DCI HID0_DCFI
225 226 #define HID0_SPD (1<<9) /* Speculative disable */
  227 +#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
226 228 #define HID0_SGE (1<<7) /* Store Gathering Enable */
227 229 #define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
228 230 #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
... ... @@ -450,6 +452,7 @@
450 452 #define SPRN_PID1 0x279 /* Process ID Register 1 */
451 453 #define SPRN_PID2 0x27a /* Process ID Register 2 */
452 454 #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
  455 +#define SPRN_MCAR 0x23d /* Machine Check Address register */
453 456 #ifdef CONFIG_440
454 457 #define MCSR_MCS 0x80000000 /* Machine Check Summary */
455 458 #define MCSR_IB 0x40000000 /* Instruction PLB Error */
1 1 /*
2   - * Copyright 2004 Freescale Semiconductor.
  2 + * Copyright 2004, 2007 Freescale Semiconductor.
3 3 * Copyright(c) 2003 Motorola Inc.
4   - * Xianghua Xiao (x.xiao@motorola.com)
5 4 */
6 5  
7 6 #ifndef __MPC85xx_H__
8 7 #define __MPC85xx_H__
9 8  
10   -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
11   -#define _START_OFFSET EXC_OFF_SYS_RESET
  9 +/* define for common ppc_asm.tmpl */
  10 +#define EXC_OFF_SYS_RESET 0x100 /* System reset */
  11 +#define _START_OFFSET 0
12 12  
13 13 #if defined(CONFIG_E500)
14 14 #include <e500.h>