Eric Lee / smarc-uboot

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Commit 61c0d6ae777b684a5bb876dadd14d548625d27c7

Authored by Tom Rini
1 parent b0d60a9812
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

gth2: Remove this platform 

After taking with the former maintainer, delete this platform.  The
patch is from the former maintainer.

Signed-off-by: Tom Rini <trini@ti.com>

Showing 14 changed files with 1 additions and 1793 deletions Side-by-side Diff

... ... @@ -1050,7 +1050,6 @@
1050 1050  
1051 1051 Thomas Lange <thomas@corelatus.se>
1052 1052 dbau1x00 MIPS32 Au1000
1053   - gth2 MIPS32 Au1000
1054 1053  
1055 1054 Vlad Lungu <vlad.lungu@windriver.com>
1056 1055 qemu_mips MIPS32
... ... @@ -411,7 +411,6 @@
411 411 dbau1100 \
412 412 dbau1500 \
413 413 dbau1550 \
414   - gth2 \
415 414 "
416 415  
417 416 LIST_mips=" \
board/gth2/Makefile
View file @ 61c0d6a
1   -#
2   -# (C) Copyright 2005-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# See file CREDITS for list of people who contributed to this
6   -# project.
7   -#
8   -# This program is free software; you can redistribute it and/or
9   -# modify it under the terms of the GNU General Public License as
10   -# published by the Free Software Foundation; either version 2 of
11   -# the License, or (at your option) any later version.
12   -#
13   -# This program is distributed in the hope that it will be useful,
14   -# but WITHOUT ANY WARRANTY; without even the implied warranty of
15   -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   -# GNU General Public License for more details.
17   -#
18   -# You should have received a copy of the GNU General Public License
19   -# along with this program; if not, write to the Free Software
20   -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   -# MA 02111-1307 USA
22   -#
23   -
24   -include $(TOPDIR)/config.mk
25   -
26   -LIB = $(obj)lib$(BOARD).o
27   -
28   -COBJS = $(BOARD).o flash.o ee_access.o
29   -SOBJS = lowlevel_init.o
30   -
31   -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
32   -OBJS := $(addprefix $(obj),$(COBJS))
33   -SOBJS := $(addprefix $(obj),$(SOBJS))
34   -
35   -$(LIB): $(obj).depend $(OBJS) $(SOBJS)
36   - $(call cmd_link_o_target, $(OBJS) $(SOBJS))
37   -
38   -#########################################################################
39   -
40   -# defines $(obj).depend target
41   -include $(SRCTREE)/rules.mk
42   -
43   -sinclude $(obj).depend
44   -
45   -#########################################################################
board/gth2/config.mk
View file @ 61c0d6a
1   -#
2   -# (C) Copyright 2004-2005
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# See file CREDITS for list of people who contributed to this
6   -# project.
7   -#
8   -# This program is free software; you can redistribute it and/or
9   -# modify it under the terms of the GNU General Public License as
10   -# published by the Free Software Foundation; either version 2 of
11   -# the License, or (at your option) any later version.
12   -#
13   -# This program is distributed in the hope that it will be useful,
14   -# but WITHOUT ANY WARRANTY; without even the implied warranty of
15   -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   -# GNU General Public License for more details.
17   -#
18   -# You should have received a copy of the GNU General Public License
19   -# along with this program; if not, write to the Free Software
20   -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   -# MA 02111-1307 USA
22   -#
23   -
24   -#
25   -# AMD Alchemy AU1000, MIPS32 core
26   -#
27   -
28   -ifeq ($(TBASE),0)
29   -CONFIG_SYS_TEXT_BASE = 0
30   -else
31   -ifeq ($(TBASE),1)
32   -CONFIG_SYS_TEXT_BASE = 0xbfc10070
33   -else
34   -ifeq ($(TBASE),2)
35   -CONFIG_SYS_TEXT_BASE = 0xbfc30070
36   -else
37   -## Only to make ordinary make work
38   -CONFIG_SYS_TEXT_BASE = 0x90000000
39   -endif
40   -endif
41   -endif
board/gth2/ee_access.c
View file @ 61c0d6a
1   -/* Module for handling DALLAS DS2438, smart battery monitor
2   - Chip can store up to 40 bytes of user data in EEPROM,
3   - perform temp, voltage and current measurements.
4   - Chip also contains a unique serial number.
5   -
6   - Always read/write LSb first
7   -
8   - For documentaion, see data sheet for DS2438, 2438.pdf
9   -
10   - By Thomas.Lange@corelatus.com 001025
11   -
12   - Copyright (C) 2000-2005 Corelatus AB */
13   -
14   -/* This program is free software; you can redistribute it and/or
15   - * modify it under the terms of the GNU General Public License as
16   - * published by the Free Software Foundation; either version 2 of
17   - * the License, or (at your option) any later version.
18   - *
19   - * This program is distributed in the hope that it will be useful,
20   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
21   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22   - * GNU General Public License for more details.
23   - *
24   - * You should have received a copy of the GNU General Public License
25   - * along with this program; if not, write to the Free Software
26   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27   - * MA 02111-1307 USA
28   - */
29   -
30   -#include <common.h>
31   -#include <command.h>
32   -#include <asm/au1x00.h>
33   -#include <asm/io.h>
34   -#include "ee_dev.h"
35   -#include "ee_access.h"
36   -
37   -/* static int Debug = 1; */
38   -#undef E_DEBUG
39   -#define E_DEBUG(fmt,args...) /* */
40   -/* #define E_DEBUG(fmt,args...) printk("EEA:"fmt,##args); */
41   -
42   -/* We dont have kernel functions */
43   -#define printk printf
44   -#define KERN_DEBUG
45   -#define KERN_ERR
46   -#define EIO 1
47   -
48   -#ifndef TRUE
49   -#define TRUE 1
50   -#endif
51   -#ifndef FALSE
52   -#define FALSE 0
53   -#endif
54   -
55   -/* lookup table ripped from DS app note 17, understanding and using cyclic redundancy checks... */
56   -
57   -static u8 crc_lookup[256] = {
58   - 0, 94, 188, 226, 97, 63, 221, 131,
59   - 194, 156, 126, 32, 163, 253, 31, 65,
60   - 157, 195, 33, 127, 252, 162, 64, 30,
61   - 95, 1, 227, 189, 62, 96, 130, 220,
62   - 35, 125, 159, 193, 66, 28, 254, 160,
63   - 225, 191, 93, 3, 128, 222, 60, 98,
64   - 190, 224, 2, 92, 223, 129, 99, 61,
65   - 124, 34, 192, 158, 29, 67, 161, 255,
66   - 70, 24, 250, 164, 39, 121, 155, 197,
67   - 132, 218, 56, 102, 229, 187, 89, 7,
68   - 219, 133, 103, 57, 186, 228, 6, 88,
69   - 25, 71, 165, 251, 120, 38, 196, 154,
70   - 101, 59, 217, 135, 4, 90, 184, 230,
71   - 167, 249, 27, 69, 198, 152, 122, 36,
72   - 248, 166, 68, 26, 153, 199, 37, 123,
73   - 58, 100, 134, 216, 91, 5, 231, 185,
74   - 140, 210, 48, 110, 237, 179, 81, 15,
75   - 78, 16, 242, 172, 47, 113, 147, 205,
76   - 17, 79, 173, 243, 112, 46, 204, 146,
77   - 211, 141, 111, 49, 178, 236, 14, 80,
78   - 175, 241, 19, 77, 206, 144, 114, 44,
79   - 109, 51, 209, 143, 12, 82, 176, 238,
80   - 50, 108, 142, 208, 83, 13, 239, 177,
81   - 240, 174, 76, 18, 145, 207, 45, 115,
82   - 202, 148, 118, 40, 171, 245, 23, 73,
83   - 8, 86, 180, 234, 105, 55, 213, 139,
84   - 87, 9, 235, 181, 54, 104, 138, 212,
85   - 149, 203, 41, 119, 244, 170, 72, 22,
86   - 233, 183, 85, 11, 136, 214, 52, 106,
87   - 43, 117, 151, 201, 74, 20, 246, 168,
88   - 116, 42, 200, 150, 21, 75, 169, 247,
89   - 182, 232, 10, 84, 215, 137, 107, 53
90   -};
91   -
92   -static void
93   -write_gpio_data(int value ){
94   - if(value){
95   - /* Tristate */
96   - gpio_tristate(GPIO_EEDQ);
97   - }
98   - else{
99   - /* Drive 0 */
100   - gpio_clear(GPIO_EEDQ);
101   - }
102   -}
103   -
104   -static u8 make_new_crc( u8 Old_crc, u8 New_value ){
105   - /* Compute a new checksum with new byte, using previous checksum as input
106   - See DS app note 17, understanding and using cyclic redundancy checks...
107   - Also see DS2438, page 11 */
108   - return( crc_lookup[Old_crc ^ New_value ]);
109   -}
110   -
111   -int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
112   - /* Check if the checksum for this buffer is correct */
113   - u8 Curr_crc=0;
114   - int i;
115   - u8 *Curr_byte = Buffer;
116   -
117   - for(i=0;i<Len;i++){
118   - Curr_crc = make_new_crc( Curr_crc, *Curr_byte);
119   - Curr_byte++;
120   - }
121   - E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
122   -
123   - if(Curr_crc == Crc){
124   - /* Good */
125   - return(TRUE);
126   - }
127   - printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
128   - return(FALSE);
129   -}
130   -
131   -static void
132   -set_idle(void){
133   - /* Send idle and keep start time
134   - Continous 1 is idle */
135   - WRITE_PORT(1);
136   -}
137   -
138   -
139   -static int
140   -do_cpu_reset(void){
141   - /* Release reset and verify that chip responds with presence pulse */
142   - int Retries=0;
143   - while(Retries<15){
144   - udelay(RESET_LOW_TIME);
145   -
146   - /* Send reset */
147   - WRITE_PORT(0);
148   - udelay(RESET_LOW_TIME);
149   -
150   - /* Release reset */
151   - WRITE_PORT(1);
152   -
153   - /* Wait for EEPROM to drive output */
154   - udelay(PRESENCE_TIMEOUT);
155   - if(!READ_PORT){
156   - /* Ok, EEPROM is driving a 0 */
157   - E_DEBUG("Presence detected\n");
158   - if(Retries){
159   - E_DEBUG("Retries %d\n",Retries);
160   - }
161   - /* Make sure chip releases pin */
162   - udelay(PRESENCE_LOW_TIME);
163   - return 0;
164   - }
165   - Retries++;
166   - }
167   -
168   - printk(KERN_ERR"eeprom did not respond when releasing reset\n");
169   -
170   - /* Make sure chip releases pin */
171   - udelay(PRESENCE_LOW_TIME);
172   -
173   - /* Set to idle again */
174   - set_idle();
175   -
176   - return(-EIO);
177   -}
178   -
179   -static u8
180   -read_cpu_byte(void){
181   - /* Read a single byte from EEPROM
182   - Read LSb first */
183   - int i;
184   - int Value;
185   - u8 Result=0;
186   - u32 Flags;
187   -
188   - E_DEBUG("Reading byte\n");
189   -
190   - for(i=0;i<8;i++){
191   - /* Small delay between pulses */
192   - udelay(1);
193   -
194   -#ifdef __KERNEL__
195   - /* Disable irq */
196   - save_flags(Flags);
197   - cli();
198   -#endif
199   -
200   - /* Pull down pin short time to start read
201   - See page 26 in data sheet */
202   -
203   - WRITE_PORT(0);
204   - udelay(READ_LOW);
205   - WRITE_PORT(1);
206   -
207   - /* Wait for chip to drive pin */
208   - udelay(READ_TIMEOUT);
209   -
210   - Value = READ_PORT;
211   - if(Value)
212   - Value=1;
213   -
214   -#ifdef __KERNEL__
215   - /* Enable irq */
216   - restore_flags(Flags);
217   -#endif
218   -
219   - /* Wait for chip to release pin */
220   - udelay(TOTAL_READ_LOW-READ_TIMEOUT);
221   -
222   - /* LSb first */
223   - Result|=Value<<i;
224   - /* E_DEBUG("Read %d\n",Value); */
225   -
226   - }
227   -
228   - E_DEBUG("Read byte 0x%x\n",Result);
229   -
230   - return(Result);
231   -}
232   -
233   -static void
234   -write_cpu_byte(u8 Byte){
235   - /* Write a single byte to EEPROM
236   - Write LSb first */
237   - int i;
238   - int Value;
239   - u32 Flags;
240   -
241   - E_DEBUG("Writing byte 0x%x\n",Byte);
242   -
243   - for(i=0;i<8;i++){
244   - /* Small delay between pulses */
245   - udelay(1);
246   - Value = Byte&1;
247   -
248   -#ifdef __KERNEL__
249   - /* Disable irq */
250   - save_flags(Flags);
251   - cli();
252   -#endif
253   -
254   - /* Pull down pin short time for a 1, long time for a 0
255   - See page 26 in data sheet */
256   -
257   - WRITE_PORT(0);
258   - if(Value){
259   - /* Write a 1 */
260   - udelay(WRITE_1_LOW);
261   - }
262   - else{
263   - /* Write a 0 */
264   - udelay(WRITE_0_LOW);
265   - }
266   -
267   - WRITE_PORT(1);
268   -
269   -#ifdef __KERNEL__
270   - /* Enable irq */
271   - restore_flags(Flags);
272   -#endif
273   -
274   - if(Value)
275   - /* Wait for chip to read the 1 */
276   - udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
277   -
278   - /* E_DEBUG("Wrote %d\n",Value); */
279   - Byte>>=1;
280   - }
281   -}
282   -
283   -int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
284   - /* Execute this command string, including
285   - giving reset and setting to idle after command
286   - if Rx_len is set, we read out data from EEPROM */
287   - int i;
288   -
289   - E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
290   -
291   - if(do_cpu_reset()){
292   - /* Failed! */
293   - return(-EIO);
294   - }
295   -
296   - if(Send_skip)
297   - /* Always send SKIP_ROM first to tell chip we are sending a command,
298   - except when we read out rom data for chip */
299   - write_cpu_byte(SKIP_ROM);
300   -
301   - /* Always have Tx data */
302   - for(i=0;i<Tx_len;i++){
303   - write_cpu_byte(Tx[i]);
304   - }
305   -
306   - if(Rx_len){
307   - for(i=0;i<Rx_len;i++){
308   - Rx[i]=read_cpu_byte();
309   - }
310   - }
311   -
312   - set_idle();
313   -
314   - E_DEBUG("Command done\n");
315   -
316   - return(0);
317   -}
318   -
319   -int ee_init_cpu_data(void){
320   - int i;
321   - u8 Tx[10];
322   -
323   - /* Leave it floting since altera is driving the same pin */
324   - set_idle();
325   -
326   - /* Copy all User EEPROM data to scratchpad */
327   - for(i=0;i<USER_PAGES;i++){
328   - Tx[0]=RECALL_MEMORY;
329   - Tx[1]=EE_USER_PAGE_0+i;
330   - if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
331   - }
332   -
333   - /* Make sure chip doesnt store measurements in NVRAM */
334   - Tx[0]=WRITE_SCRATCHPAD;
335   - Tx[1]=0; /* Page */
336   - Tx[2]=9;
337   - if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO);
338   -
339   - Tx[0]=COPY_SCRATCHPAD;
340   - if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
341   -
342   - for(i=0;i<10;i++){
343   - udelay(1000);
344   - }
345   -
346   - return(0);
347   -}
board/gth2/ee_access.h
View file @ 61c0d6a
1   -/* By Thomas.Lange@Corelatus.com 001025 */
2   -
3   -/* Definitions for EEPROM/VOLT METER DS2438 */
4   -/* Copyright (C) 2000-2005 Corelatus AB */
5   -
6   -#ifndef INCeeaccessh
7   -#define INCeeaccessh
8   -
9   -#include <asm/types.h>
10   -#include "ee_dev.h"
11   -
12   -int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip );
13   -int ee_init_cpu_data(void);
14   -
15   -int ee_crc_ok( u8 *Buffer, int Len, u8 Crc );
16   -
17   -/* Defs for altera reg */
18   -#define EE_WRITE_SHIFT 8 /* bits to shift left */
19   -#define EE_READ_SHIFT 16 /* bits to shift left */
20   -#define EE_DONE 0x80000000
21   -#define EE_BUSY 0x40000000
22   -#define EE_ERROR 0x20000000
23   -
24   -/* Commands */
25   -#define EE_CMD_NOP 0
26   -#define EE_CMD_INIT_RES 1
27   -#define EE_CMD_WR_BYTE 2
28   -#define EE_CMD_RD_BYTE 3
29   -
30   -#endif /* INCeeaccessh */
board/gth2/ee_dev.h
View file @ 61c0d6a
1   -/* By Thomas.Lange@Corelatus.com 001025 */
2   -/* Definitions for EEPROM/VOLT METER DS2438 */
3   -/* Copyright (C) 2000-2005 Corelatus AB */
4   -
5   -/* This program is free software; you can redistribute it and/or
6   - * modify it under the terms of the GNU General Public License as
7   - * published by the Free Software Foundation; either version 2 of
8   - * the License, or (at your option) any later version.
9   - *
10   - * This program is distributed in the hope that it will be useful,
11   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
12   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13   - * GNU General Public License for more details.
14   - *
15   - * You should have received a copy of the GNU General Public License
16   - * along with this program; if not, write to the Free Software
17   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18   - * MA 02111-1307 USA
19   - */
20   -
21   -#ifndef INCeedevh
22   -#define INCeedevh
23   -
24   -#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
25   -
26   -/* MIPS */
27   -#define WRITE_PORT(Value) write_gpio_data(Value)
28   -
29   -#define READ_PORT (gpio_read()&GPIO_EEDQ)
30   -
31   -/* 64 bytes chip */
32   -#define EE_CHIP_SIZE 64
33   -
34   -/* Board with new current resistor */
35   -#define EE_GTH_0304 1
36   -
37   -/* new dsp and 64 MB SDRAM */
38   -#define EE_DSP_64 0x10
39   -
40   -/* microsecs */
41   -/* Pull line down at least this long for reset pulse */
42   -#define RESET_LOW_TIME 490
43   -
44   -/* Read presence pulse after we release reset pulse */
45   -#define PRESENCE_TIMEOUT 100
46   -#define PRESENCE_LOW_TIME 200
47   -
48   -#define WRITE_0_LOW 60
49   -#define WRITE_1_LOW 1
50   -#define TOTAL_WRITE_LOW 60
51   -
52   -#define READ_LOW 1
53   -#define READ_TIMEOUT 10
54   -#define TOTAL_READ_LOW 70
55   -
56   -/* Rom function commands */
57   -#define READ_ROM 0x33
58   -#define MATCH_ROM 0x55
59   -#define SKIP_ROM 0xCC
60   -#define SEARCH_ROM 0xF0
61   -
62   -
63   -/* Memory_command_function */
64   -#define WRITE_SCRATCHPAD 0x4E
65   -#define READ_SCRATCHPAD 0xBE
66   -#define COPY_SCRATCHPAD 0x48
67   -#define RECALL_MEMORY 0xB8
68   -#define CONVERT_TEMP 0x44
69   -#define CONVERT_VOLTAGE 0xB4
70   -
71   -/* Chip is divided in 8 pages, 8 bytes each */
72   -
73   -#define EE_PAGE_SIZE 8
74   -
75   -/* All chip data we want are in page 0 */
76   -
77   -/* Bytes in page 0 */
78   -#define EE_P0_STATUS 0
79   -#define EE_P0_TEMP_LSB 1
80   -#define EE_P0_TEMP_MSB 2
81   -#define EE_P0_VOLT_LSB 3
82   -#define EE_P0_VOLT_MSB 4
83   -#define EE_P0_CURRENT_LSB 5
84   -#define EE_P0_CURRENT_MSB 6
85   -
86   -
87   -/* 40 byte user data is located at page 3-7 */
88   -#define EE_USER_PAGE_0 3
89   -#define USER_PAGES 5
90   -
91   -/* Layout of gth user pages usage */
92   -/* Bytes 0-16 ethernet addr in ascii ( len 17 ) */
93   -
94   -#define EE_ETHERNET_OFFSET 0
95   -
96   -#endif /* INCeedevh */
board/gth2/flash.c
View file @ 61c0d6a
1   -/*
2   - * (C) Copyright 2005
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -#include <common.h>
25   -
26   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
27   -
28   -/*-----------------------------------------------------------------------
29   - * flash_init()
30   - *
31   - * sets up flash_info and returns size of FLASH (bytes)
32   - */
33   -unsigned long flash_init (void)
34   -{
35   - printf ("Skipping flash_init\n");
36   - return (0);
37   -}
38   -
39   -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
40   -{
41   - printf ("write_buff not implemented\n");
42   - return (-1);
43   -}
board/gth2/gth2.c
View file @ 61c0d6a
1   -/*
2   - * (C) Copyright 2005
3   - * Thomas.Lange@corelatus.se
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -#include <common.h>
25   -#include <command.h>
26   -#include <asm/au1x00.h>
27   -#include <asm/addrspace.h>
28   -#include <asm/mipsregs.h>
29   -#include <asm/io.h>
30   -#include <watchdog.h>
31   -
32   -#include "ee_access.h"
33   -
34   -static int wdi_status = 0;
35   -
36   -#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
37   -
38   -
39   -#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096))
40   -
41   -void inline log_serial_char(char c){
42   - char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
43   - int serial_log_offset;
44   - u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
45   -
46   - serial_log_offset = *serial_log_offsetp;
47   -
48   - *(serial_log_buffer + serial_log_offset) = c;
49   -
50   - serial_log_offset++;
51   -
52   - if(serial_log_offset >= 4096){
53   - serial_log_offset = 4;
54   - }
55   - *serial_log_offsetp = serial_log_offset;
56   -}
57   -
58   -void init_log_serial(void){
59   - char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
60   - u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
61   -
62   - /* Copy buffer from last run */
63   - memcpy(serial_log_buffer + 4096,
64   - serial_log_buffer,
65   - 4096);
66   -
67   - memset(serial_log_buffer, 0, 4096);
68   -
69   - *serial_log_offsetp = 4;
70   -}
71   -
72   -
73   -void hw_watchdog_reset(void){
74   - volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
75   - volatile u32 *sys_outputclear = (volatile u32*)SYS_OUTPUTCLR;
76   - if(wdi_status){
77   - *sys_outputset = GPIO_CPU_LED|GPIO_WDI;
78   - wdi_status = 0;
79   - }
80   - else{
81   - *sys_outputclear = GPIO_CPU_LED|GPIO_WDI;
82   - wdi_status = 1;
83   - }
84   -}
85   -
86   -phys_size_t initdram(int board_type)
87   -{
88   - /* Sdram is setup by assembler code */
89   - /* If memory could be changed, we should return the true value here */
90   -
91   - WATCHDOG_RESET();
92   -
93   - return (SDRAM_SIZE);
94   -}
95   -
96   -/* In arch/mips/cpu/cpu.c */
97   -void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
98   -
99   -void set_ledcard(u32 value){
100   - /* Clock 24 bits to led card */
101   - int i;
102   - volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
103   - volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR;
104   -
105   - /* Start with known values */
106   - *sys_outputclr = GPIO_LEDCLK|GPIO_LEDD;
107   -
108   - for(i=0;i<24;i++){
109   - if(value&0x00800000){
110   - *sys_outputset = GPIO_LEDD;
111   - }
112   - else{
113   - *sys_outputclr = GPIO_LEDD;
114   - }
115   - udelay(1);
116   - *sys_outputset = GPIO_LEDCLK;
117   - udelay(1);
118   - *sys_outputclr = GPIO_LEDCLK;
119   - udelay(1);
120   -
121   - value<<=1;
122   - }
123   - /* Data is enable output */
124   - *sys_outputset = GPIO_LEDD;
125   -}
126   -
127   -int checkboard (void)
128   -{
129   - volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
130   - volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
131   - volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR;
132   - u32 proc_id;
133   -
134   - WATCHDOG_RESET();
135   -
136   - *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
137   -
138   - proc_id = read_c0_prid();
139   -
140   - switch (proc_id >> 24) {
141   - case 0:
142   - puts ("Board: GTH2\n");
143   - printf ("CPU: Au1000 500 MHz, id: 0x%02x, rev: 0x%02x\n",
144   - (proc_id >> 8) & 0xFF, proc_id & 0xFF);
145   - break;
146   - default:
147   - printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
148   - }
149   -
150   - set_io_port_base(0);
151   -
152   -#ifdef CONFIG_IDE_PCMCIA
153   - /* PCMCIA is on a 36 bit physical address.
154   - We need to map it into a 32 bit addresses */
155   - write_one_tlb(20, /* index */
156   - 0x01ffe000, /* Pagemask, 16 MB pages */
157   - CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
158   - 0x3C000017, /* Lo0 */
159   - 0x3C200017); /* Lo1 */
160   -
161   - write_one_tlb(21, /* index */
162   - 0x01ffe000, /* Pagemask, 16 MB pages */
163   - CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
164   - 0x3D000017, /* Lo0 */
165   - 0x3D200017); /* Lo1 */
166   -
167   - write_one_tlb(22, /* index */
168   - 0x01ffe000, /* Pagemask, 16 MB pages */
169   - CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
170   - 0x3E000017, /* Lo0 */
171   - 0x3E200017); /* Lo1 */
172   -
173   -#endif /* CONFIG_IDE_PCMCIA */
174   -
175   - /* Wait for GPIO ports to become stable */
176   - udelay(5000); /* FIXME */
177   -
178   - /* Release reset of ethernet PHY chips */
179   - /* Always do this, because linux does not know about it */
180   - *sys_outputset = GPIO_ERESET;
181   -
182   - /* Kill FPGA:s */
183   - *sys_outputclr = GPIO_CACONFIG|GPIO_DPACONFIG;
184   - udelay(2);
185   - *sys_outputset = GPIO_CACONFIG|GPIO_DPACONFIG;
186   -
187   - /* Turn front led yellow */
188   - set_ledcard(0x00100000);
189   -
190   - return 0;
191   -}
192   -
193   -#define POWER_OFFSET 0xF0000
194   -#define SW_WATCHDOG_REASON 13
195   -
196   -#define BOOTDATA_OFFSET 0xF8000
197   -#define MAX_ATTEMPTS 5
198   -
199   -#define FAILSAFE_BOOT 1
200   -#define SYSTEM_BOOT 2
201   -#define SYSTEM2_BOOT 3
202   -
203   -#define WRITE_FLASH16(a, d) \
204   -do \
205   -{ \
206   - *((volatile u16 *) (a)) = (d);\
207   - } while(0)
208   -
209   -static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
210   -{
211   - u16 data;
212   - volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE);
213   -
214   - switch(System){
215   - case FAILSAFE_BOOT:
216   - printf ("Setting failsafe boot in flash\n");
217   - break;
218   - case SYSTEM_BOOT:
219   - printf ("Setting system boot in flash\n");
220   - break;
221   - case SYSTEM2_BOOT:
222   - printf ("Setting system2 boot in flash\n");
223   - break;
224   - default:
225   - printf ("Invalid system data %u, setting failsafe\n", System);
226   - System = FAILSAFE_BOOT;
227   - }
228   -
229   - if ((Count < 1) | (Count > MAX_ATTEMPTS)) {
230   - printf ("Invalid boot count %u, setting 1\n", Count);
231   - Count = 1;
232   - }
233   -
234   - printf ("Boot attempt %d\n", Count);
235   -
236   - data = (System << 8) | Count;
237   - /* AMD 16 bit */
238   - WRITE_FLASH16 (&flash[0x555], 0xAAAA);
239   - WRITE_FLASH16 (&flash[0x2AA], 0x5555);
240   - WRITE_FLASH16 (&flash[0x555], 0xA0A0);
241   -
242   - WRITE_FLASH16 (addr, data);
243   -}
244   -
245   -static int random_system(void){
246   - /* EEPROM read failed. Just try to choose one
247   - system release and hope it works */
248   -
249   - /* FIXME */
250   - return(SYSTEM_BOOT);
251   -}
252   -
253   -static int switch_system(int old_system){
254   - u8 Rx[10];
255   - u8 Tx[5];
256   - int valid_release;
257   -
258   - if(old_system==FAILSAFE_BOOT){
259   - /* Find out which system release to use */
260   -
261   - /* Copy from nvram to scratchpad */
262   - Tx[0] = RECALL_MEMORY;
263   - Tx[1] = 7; /* Page */
264   - if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) {
265   - printf ("EE user page 7 recall failed\n");
266   - return (random_system());
267   - }
268   -
269   - Tx[0] = READ_SCRATCHPAD;
270   - if (ee_do_cpu_command (Tx, 2, Rx, 9, 1)) {
271   - printf ("EE user page 7 read failed\n");
272   - return (random_system());
273   - }
274   - /* Crc in 9:th byte */
275   - if (!ee_crc_ok (Rx, 8, *(Rx + 8))) {
276   - printf ("EE read failed, page 7. CRC error\n");
277   - return (random_system());
278   - }
279   -
280   - valid_release = Rx[7];
281   - if((valid_release==0xFF)|
282   - ((valid_release&1) == 0)){
283   - return(SYSTEM_BOOT);
284   - }
285   - else{
286   - return(SYSTEM2_BOOT);
287   - }
288   - }
289   - else{
290   - return(FAILSAFE_BOOT);
291   - }
292   -}
293   -
294   -static void check_boot_tries (void)
295   -{
296   - /* Count the number of boot attemps
297   - switch system if too many */
298   -
299   - int i;
300   - volatile u16 *addr;
301   - volatile u16 data;
302   - u8 system = FAILSAFE_BOOT;
303   - u8 count;
304   -
305   - addr = (u16 *) (CONFIG_SYS_FLASH_BASE + BOOTDATA_OFFSET);
306   -
307   - if (*addr == 0xFFFF) {
308   - printf ("*** No bootdata exists. ***\n");
309   - write_bootdata (addr, FAILSAFE_BOOT, 1);
310   - } else {
311   - /* Search for latest written bootdata */
312   - i = 0;
313   - while ((*(addr + 1) != 0xFFFF) & (i < 8000)) {
314   - addr++;
315   - i++;
316   - }
317   - if (i >= 8000) {
318   - /* Whoa, dont write any more */
319   - printf ("*** No bootdata found. Not updating flash***\n");
320   - } else {
321   - /* See how many times we have tried to boot real system */
322   - data = *addr;
323   - system = data >> 8;
324   - count = data & 0xFF;
325   - if ((system != SYSTEM_BOOT) &
326   - (system != SYSTEM2_BOOT) &
327   - (system != FAILSAFE_BOOT)) {
328   - printf ("*** Wrong system %d\n", system);
329   - system = FAILSAFE_BOOT;
330   - count = 1;
331   - } else {
332   - switch (count) {
333   - case 0:
334   - case 1:
335   - case 2:
336   - case 3:
337   - case 4:
338   - /* Try same system again if needed */
339   - count++;
340   - break;
341   -
342   - case 5:
343   - /* Switch system and reset tries */
344   - count = 1;
345   - system = switch_system(system);
346   - printf ("***Too many boot attempts, switching system***\n");
347   - break;
348   - default:
349   - /* Switch system, start over and hope it works */
350   - printf ("***Unexpected data on addr 0x%x, %u***\n",
351   - (u32) addr, data);
352   - count = 1;
353   - system = switch_system(system);
354   - }
355   - }
356   - write_bootdata (addr + 1, system, count);
357   - }
358   - }
359   - switch(system){
360   - case FAILSAFE_BOOT:
361   - printf ("Booting failsafe system\n");
362   - setenv ("bootargs", "panic=1 root=/dev/hda7");
363   - setenv ("bootcmd", "ide reset;disk 0x81000000 0:5;run addmisc;bootm");
364   - break;
365   -
366   - case SYSTEM_BOOT:
367   - printf ("Using normal system\n");
368   - setenv ("bootargs", "panic=1 root=/dev/hda4");
369   - setenv ("bootcmd", "ide reset;disk 0x81000000 0:2;run addmisc;bootm");
370   - break;
371   -
372   - case SYSTEM2_BOOT:
373   - printf ("Using normal system2\n");
374   - setenv ("bootargs", "panic=1 root=/dev/hda9");
375   - setenv ("bootcmd", "ide reset;disk 0x81000000 0:8;run addmisc;bootm");
376   - break;
377   - default:
378   - printf ("Invalid system %d\n", system);
379   - printf ("Hanging\n");
380   - while(1);
381   - }
382   -}
383   -
384   -int misc_init_r(void){
385   - u8 Rx[80];
386   - u8 Tx[5];
387   - int page;
388   - int read = 0;
389   -
390   - WATCHDOG_RESET();
391   -
392   - if (ee_init_cpu_data ()) {
393   - printf ("EEPROM init failed\n");
394   - return (0);
395   - }
396   -
397   - /* Check which release to boot */
398   - check_boot_tries ();
399   -
400   - /* Read the pages where ethernet address is stored */
401   -
402   - for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) {
403   - /* Copy from nvram to scratchpad */
404   - Tx[0] = RECALL_MEMORY;
405   - Tx[1] = page;
406   - if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) {
407   - printf ("EE user page %d recall failed\n", page);
408   - return (0);
409   - }
410   -
411   - Tx[0] = READ_SCRATCHPAD;
412   - if (ee_do_cpu_command (Tx, 2, Rx + read, 9, 1)) {
413   - printf ("EE user page %d read failed\n", page);
414   - return (0);
415   - }
416   - /* Crc in 9:th byte */
417   - if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) {
418   - printf ("EE read failed, page %d. CRC error\n", page);
419   - return (0);
420   - }
421   - read += 8;
422   - }
423   -
424   - /* Add eos after eth addr */
425   - Rx[17] = 0;
426   -
427   - printf ("Ethernet addr read from eeprom: %s\n\n", Rx);
428   -
429   - if ((Rx[2] != ':') |
430   - (Rx[5] != ':') |
431   - (Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
432   - printf ("*** ethernet addr invalid, using default ***\n");
433   - } else {
434   - setenv ("ethaddr", (char *)Rx);
435   - }
436   - return (0);
437   -}
board/gth2/lowlevel_init.S
View file @ 61c0d6a
1   -/* Memory sub-system initialization code */
2   -
3   -#include <config.h>
4   -#include <asm/regdef.h>
5   -#include <asm/au1x00.h>
6   -#include <asm/mipsregs.h>
7   -
8   -#define CP0_Config0 $16
9   -#define MEM_1MS ((CONFIG_SYS_MHZ) * 1000)
10   -#define GPIO_RJ1LY (1<<22)
11   -#define GPIO_CFRESET (1<<10)
12   -
13   - .text
14   - .set noreorder
15   - .set mips32
16   -
17   - .globl lowlevel_init
18   -lowlevel_init:
19   - /*
20   - * Step 2) Establish Status Register
21   - * (set BEV, clear ERL, clear EXL, clear IE)
22   - */
23   - li t1, 0x00400000
24   - mtc0 t1, CP0_STATUS
25   -
26   - /*
27   - * Step 3) Establish CP0 Config0
28   - * (set OD, set K0=3)
29   - */
30   - li t1, 0x00080003
31   - mtc0 t1, CP0_CONFIG
32   -
33   - /*
34   - * Step 4) Disable Watchpoint facilities
35   - */
36   - li t1, 0x00000000
37   - mtc0 t1, CP0_WATCHLO
38   - mtc0 t1, CP0_IWATCHLO
39   - /*
40   - * Step 5) Disable the performance counters
41   - */
42   - mtc0 zero, CP0_PERFORMANCE
43   - nop
44   -
45   - /*
46   - * Step 6) Establish EJTAG Debug register
47   - */
48   - mtc0 zero, CP0_DEBUG
49   - nop
50   -
51   - /*
52   - * Step 7) Establish Cause
53   - * (set IV bit)
54   - */
55   - li t1, 0x00800000
56   - mtc0 t1, CP0_CAUSE
57   -
58   - /* Establish Wired (and Random) */
59   - mtc0 zero, CP0_WIRED
60   - nop
61   -
62   - /* No workaround if running from ram */
63   - lui t0, 0xffc0
64   - lui t3, 0xbfc0
65   - and t1, ra, t0
66   - bne t1, t3, noCacheJump
67   - nop
68   -
69   - /*** From AMD YAMON ***/
70   - /*
71   - * Step 8) Initialize the caches
72   - */
73   - li t0, (16*1024)
74   - li t1, 32
75   - li t2, 0x80000000
76   - addu t3, t0, t2
77   -cacheloop:
78   - cache 0, 0(t2)
79   - cache 1, 0(t2)
80   - addu t2, t1
81   - bne t2, t3, cacheloop
82   - nop
83   -
84   - /* Save return address */
85   - move t3, ra
86   -
87   - /* Run from cacheable space now */
88   - bal cachehere
89   - nop
90   -cachehere:
91   - li t1, ~0x20000000 /* convert to KSEG0 */
92   - and t0, ra, t1
93   - addi t0, 5*4 /* 5 insns beyond cachehere */
94   - jr t0
95   - nop
96   -
97   - /* Restore return address */
98   - move ra, t3
99   -
100   - /*
101   - * Step 9) Initialize the TLB
102   - */
103   - li t0, 0 # index value
104   - li t1, 0x00000000 # entryhi value
105   - li t2, 32 # 32 entries
106   -
107   -tlbloop:
108   - /* Probe TLB for matching EntryHi */
109   - mtc0 t1, CP0_ENTRYHI
110   - tlbp
111   - nop
112   -
113   - /* Examine Index[P], 1=no matching entry */
114   - mfc0 t3, CP0_INDEX
115   - li t4, 0x80000000
116   - and t3, t4, t3
117   - addiu t1, t1, 1 # increment t1 (asid)
118   - beq zero, t3, tlbloop
119   - nop
120   -
121   - /* Initialize the TLB entry */
122   - mtc0 t0, CP0_INDEX
123   - mtc0 zero, CP0_ENTRYLO0
124   - mtc0 zero, CP0_ENTRYLO1
125   - mtc0 zero, CP0_PAGEMASK
126   - tlbwi
127   -
128   - /* Do it again */
129   - addiu t0, t0, 1
130   - bne t0, t2, tlbloop
131   - nop
132   -
133   - /* First setup pll:s to make serial work ok */
134   - /* We have a 12.5 MHz crystal */
135   - li t0, SYS_CPUPLL
136   - li t1, 0x28 /* CPU clock, 500 MHz */
137   - sw t1, 0(t0)
138   - sync
139   - nop
140   - nop
141   -
142   - /* wait 1mS for clocks to settle */
143   - li t1, MEM_1MS
144   -1: add t1, -1
145   - bne t1, zero, 1b
146   - nop
147   - /* Setup AUX PLL */
148   - li t0, SYS_AUXPLL
149   - li t1, 0
150   - sw t1, 0(t0) /* aux pll */
151   - sync
152   -
153   - /* Static memory controller */
154   - /* RCE0 - can not change while fetching, do so from icache */
155   - move t2, ra /* Store return address */
156   - bal getAddr
157   - nop
158   -
159   -getAddr:
160   - move t1, ra
161   - move ra, t2 /* Move return addess back */
162   -
163   - cache 0x14,0(t1)
164   - cache 0x14,32(t1)
165   - /*** /From YAMON ***/
166   -
167   -noCacheJump:
168   -
169   - /* Static memory controller */
170   -
171   - /* RCE0 AMD 29LV800 Flash */
172   - li t0, MEM_STCFG0
173   - li t1, 0x00000243
174   - sw t1, 0(t0)
175   -
176   - li t0, MEM_STTIME0
177   - li t1, 0x040181D7 /* FIXME */
178   - sw t1, 0(t0)
179   -
180   - li t0, MEM_STADDR0
181   - li t1, 0x11E03F80
182   - sw t1, 0(t0)
183   -
184   - /* RCE1 PCMCIA 250ns */
185   - li t0, MEM_STCFG1
186   - li t1, 0x00000002
187   - sw t1, 0(t0)
188   -
189   - li t0, MEM_STTIME1
190   - li t1, 0x280E3E07
191   - sw t1, 0(t0)
192   -
193   - li t0, MEM_STADDR1
194   - li t1, 0x10000000
195   - sw t1, 0(t0)
196   -
197   - /* RCE2 CP Altera */
198   - li t0, MEM_STCFG2
199   - li t1, 0x00000280 /* BE, EW */
200   - sw t1, 0(t0)
201   -
202   - li t0, MEM_STTIME2
203   - li t1, 0x0303000c
204   - sw t1, 0(t0)
205   -
206   - li t0, MEM_STADDR2
207   - li t1, 0x10c03f80 /* 1 MB */
208   - sw t1, 0(t0)
209   -
210   - /* RCE3 DP Altera */
211   - li t0, MEM_STCFG3
212   - li t1, 0x00000280 /* BE, EW */
213   - sw t1, 0(t0)
214   -
215   - li t0, MEM_STTIME3
216   - li t1, 0x0303000c
217   - sw t1, 0(t0)
218   -
219   - li t0, MEM_STADDR3
220   - li t1, 0x10e03f80 /* 1 MB */
221   - sw t1, 0(t0)
222   -
223   - sync
224   -
225   - /* Set peripherals to a known state */
226   - li t0, IC0_CFG0CLR
227   - li t1, 0xFFFFFFFF
228   - sw t1, 0(t0)
229   -
230   - li t0, IC0_CFG0CLR
231   - sw t1, 0(t0)
232   -
233   - li t0, IC0_CFG1CLR
234   - sw t1, 0(t0)
235   -
236   - li t0, IC0_CFG2CLR
237   - sw t1, 0(t0)
238   -
239   - li t0, IC0_SRCSET
240   - sw t1, 0(t0)
241   -
242   - li t0, IC0_ASSIGNSET
243   - sw t1, 0(t0)
244   -
245   - li t0, IC0_WAKECLR
246   - sw t1, 0(t0)
247   -
248   - li t0, IC0_RISINGCLR
249   - sw t1, 0(t0)
250   -
251   - li t0, IC0_FALLINGCLR
252   - sw t1, 0(t0)
253   -
254   - li t0, IC0_TESTBIT
255   - li t1, 0x00000000
256   - sw t1, 0(t0)
257   - sync
258   -
259   - li t0, IC1_CFG0CLR
260   - li t1, 0xFFFFFFFF
261   - sw t1, 0(t0)
262   -
263   - li t0, IC1_CFG0CLR
264   - sw t1, 0(t0)
265   -
266   - li t0, IC1_CFG1CLR
267   - sw t1, 0(t0)
268   -
269   - li t0, IC1_CFG2CLR
270   - sw t1, 0(t0)
271   -
272   - li t0, IC1_SRCSET
273   - sw t1, 0(t0)
274   -
275   - li t0, IC1_ASSIGNSET
276   - sw t1, 0(t0)
277   -
278   - li t0, IC1_WAKECLR
279   - sw t1, 0(t0)
280   -
281   - li t0, IC1_RISINGCLR
282   - sw t1, 0(t0)
283   -
284   - li t0, IC1_FALLINGCLR
285   - sw t1, 0(t0)
286   -
287   - li t0, IC1_TESTBIT
288   - li t1, 0x00000000
289   - sw t1, 0(t0)
290   - sync
291   -
292   - li t0, SYS_FREQCTRL0
293   - li t1, 0x00000000
294   - sw t1, 0(t0)
295   -
296   - li t0, SYS_FREQCTRL1
297   - li t1, 0x00000000
298   - sw t1, 0(t0)
299   -
300   - li t0, SYS_CLKSRC
301   - li t1, 0x00000000
302   - sw t1, 0(t0)
303   -
304   - li t0, SYS_PININPUTEN
305   - li t1, 0x00000000
306   - sw t1, 0(t0)
307   - sync
308   -
309   - li t0, 0xB1100100
310   - li t1, 0x00000000
311   - sw t1, 0(t0)
312   -
313   - li t0, 0xB1400100
314   - li t1, 0x00000000
315   - sw t1, 0(t0)
316   -
317   -
318   - li t0, SYS_WAKEMSK
319   - li t1, 0x00000000
320   - sw t1, 0(t0)
321   -
322   - li t0, SYS_WAKESRC
323   - li t1, 0x00000000
324   - sw t1, 0(t0)
325   -
326   - /* wait 1mS before setup */
327   - li t1, MEM_1MS
328   -1: add t1, -1
329   - bne t1, zero, 1b
330   - nop
331   -
332   -
333   -/* SDCS 0 SDRAM */
334   - li t0, MEM_SDMODE0
335   - li t1, 0x592CD1
336   - sw t1, 0(t0)
337   -
338   - li t0, MEM_SDMODE1
339   - li t1, 0x00000000
340   - sw t1, 0(t0)
341   -
342   - li t0, MEM_SDMODE2
343   - li t1, 0x00000000
344   - sw t1, 0(t0)
345   -
346   -/* 64 MB SDRAM at addr 0 */
347   - li t0, MEM_SDADDR0
348   - li t1, 0x001003F0
349   - sw t1, 0(t0)
350   -
351   -
352   - li t0, MEM_SDADDR1
353   - li t1, 0x00000000
354   - sw t1, 0(t0)
355   -
356   - li t0, MEM_SDADDR2
357   - li t1, 0x00000000
358   - sw t1, 0(t0)
359   -
360   - sync
361   -
362   - li t0, MEM_SDREFCFG
363   - li t1, 0x880007A1 /* Disable */
364   - sw t1, 0(t0)
365   - sync
366   -
367   - li t0, MEM_SDPRECMD
368   - sw zero, 0(t0)
369   - sync
370   -
371   - li t0, MEM_SDAUTOREF
372   - sw zero, 0(t0)
373   - sync
374   - sw zero, 0(t0)
375   - sync
376   -
377   - li t0, MEM_SDREFCFG
378   - li t1, 0x8A0007A1 /* Enable */
379   - sw t1, 0(t0)
380   - sync
381   -
382   - li t0, MEM_SDWRMD0
383   - li t1, 0x00000023
384   - sw t1, 0(t0)
385   - sync
386   -
387   - /* wait 1mS after setup */
388   - li t1, MEM_1MS
389   -1: add t1, -1
390   - bne t1, zero, 1b
391   - nop
392   -
393   - /* Setup GPIO pins */
394   -
395   - li t0, SYS_PINFUNC
396   - li t1, 0x00007025 /* 0x8080 */
397   - sw t1, 0(t0)
398   -
399   - li t0, SYS_TRIOUTCLR
400   - li t1, 0xFFFFFFFF /* 0x1FFF */
401   - sw t1, 0(t0)
402   -
403   - /* Turn yellow front led on */
404   - /* Release reset on CF */
405   - li t0, SYS_OUTPUTCLR
406   - li t1, GPIO_RJ1LG
407   - sw t1, 0(t0)
408   - li t0, SYS_OUTPUTSET
409   - li t1, GPIO_RJ1LY|GPIO_CFRESET
410   - sw t1, 0(t0)
411   - sync
412   - j clearmem
413   - nop
414   -
415   -#if 0
416   - .globl memtest
417   -#endif
418   -memtest:
419   - /* Fill memory with address */
420   - li t0, 0x80000000
421   - li t1, 0xFFF000 /* 64 MB */
422   -mt0: sw t0, 0(t0)
423   - add t1, -1
424   - add t0, 4
425   - bne t1, zero, mt0
426   - nop
427   - nop
428   - /* Verify addr */
429   - li t0, 0x80000000
430   - li t1, 0xFFF000 /* 64 MB */
431   -mt1: lw t2, 0(t0)
432   - bne t0, t2, memhang
433   - add t1, -1
434   - add t0, 4
435   - bne t1, zero, mt1
436   - nop
437   - nop
438   -#if 0
439   - .globl clearmem
440   -#endif
441   -clearmem:
442   - /* Clear memory */
443   - li t0, 0x80000000
444   - li t1, 0xFFF000 /* 64 MB */
445   -mtc: sw zero, 0(t0)
446   - add t1, -1
447   - add t0, 4
448   - bne t1, zero, mtc
449   - nop
450   - nop
451   -memtestend:
452   - jr ra
453   - nop
454   -
455   -memhang:
456   - b memhang
457   - nop
board/gth2/u-boot.lds
View file @ 61c0d6a
1   -/*
2   - * (C) Copyright 2003-2005
3   - * Wolfgang Denk Engineering, <wd@denx.de>
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -/*
25   -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
26   -*/
27   -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
28   -OUTPUT_ARCH(mips)
29   -ENTRY(_start)
30   -SECTIONS
31   -{
32   - . = 0x00000000;
33   -
34   - . = ALIGN(4);
35   - .text :
36   - {
37   - *(.text*)
38   - }
39   -
40   - . = ALIGN(4);
41   - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
42   -
43   - . = ALIGN(4);
44   - .data : { *(.data*) }
45   -
46   - . = .;
47   - _gp = ALIGN(16) + 0x7ff0;
48   -
49   - .got : {
50   - __got_start = .;
51   - *(.got)
52   - __got_end = .;
53   - }
54   -
55   - .sdata : { *(.sdata*) }
56   -
57   - .u_boot_cmd : {
58   - __u_boot_cmd_start = .;
59   - *(.u_boot_cmd)
60   - __u_boot_cmd_end = .;
61   - }
62   -
63   - uboot_end_data = .;
64   - num_got_entries = (__got_end - __got_start) >> 2;
65   -
66   - . = ALIGN(4);
67   - .sbss (NOLOAD) : { *(.sbss*) }
68   - .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
69   - uboot_end = .;
70   -}
... ... @@ -419,7 +419,6 @@
419 419 dbau1500 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1500
420 420 dbau1550 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550
421 421 dbau1550_el mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN
422   -gth2 mips mips32 - - au1x00
423 422 pb1000 mips mips32 pb1x00 - au1x00 pb1x00:PB1000
424 423 incaip mips mips32 incaip - incaip
425 424 incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000
... ... @@ -668,8 +668,7 @@
668 668  
669 669 /* We only need to swap data if we are running on a big endian cpu. */
670 670 /* But Au1x00 cpu:s already swaps data in big endian mode! */
671   -#if defined(__LITTLE_ENDIAN) || \
672   - (defined(CONFIG_SOC_AU1X00) && !defined(CONFIG_GTH2))
  671 +#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SOC_AU1X00)
673 672 #define input_swap_data(x,y,z) input_data(x,y,z)
674 673 #else
675 674 static void input_swap_data(int dev, ulong *sect_buf, int words)
include/configs/gth2.h
View file @ 61c0d6a
1   -/*
2   - * (C) Copyright 2005
3   - * Thomas.Lange@corelatus.se
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -/*
25   - * This file contains the configuration parameters for the gth2 board.
26   - */
27   -
28   -#ifndef __CONFIG_H
29   -#define __CONFIG_H
30   -
31   -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
32   -#define CONFIG_GTH2 1
33   -#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
34   -
35   -#define CONFIG_SOC_AU1000 1
36   -
37   -#define CONFIG_MISC_INIT_R 1
38   -
39   -#define CONFIG_ETHADDR DE:AD:BE:EF:01:02 /* Ethernet address */
40   -
41   -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
42   -
43   -#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */
44   -
45   -#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */
46   -
47   -#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */
48   -
49   -#define CONFIG_BAUDRATE 115200
50   -
51   -/* valid baudrates */
52   -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
53   -
54   -/* Only interrupt boot if space is pressed */
55   -/* If a long serial cable is connected but */
56   -/* other end is dead, garbage will be read */
57   -#define CONFIG_AUTOBOOT_KEYED 1
58   -#define CONFIG_AUTOBOOT_PROMPT \
59   - "Press space to abort autoboot in %d second\n", bootdelay
60   -#define CONFIG_AUTOBOOT_DELAY_STR "d"
61   -#define CONFIG_AUTOBOOT_STOP_STR " "
62   -
63   -#define CONFIG_TIMESTAMP /* Print image info with timestamp */
64   -#define CONFIG_BOOTARGS "panic=1"
65   -
66   -#define CONFIG_EXTRA_ENV_SETTINGS \
67   - "addmisc=setenv bootargs $(bootargs) " \
68   - "ethaddr=$(ethaddr) \0" \
69   - "netboot=bootp;run addmisc;bootm\0" \
70   - ""
71   -
72   -/* Boot from Compact flash partition 2 as default */
73   -#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm"
74   -
75   -
76   -/*
77   - * BOOTP options
78   - */
79   -#define CONFIG_BOOTP_BOOTFILESIZE
80   -#define CONFIG_BOOTP_BOOTPATH
81   -#define CONFIG_BOOTP_GATEWAY
82   -#define CONFIG_BOOTP_HOSTNAME
83   -
84   -
85   -/*
86   - * Command line configuration.
87   - */
88   -#include <config_cmd_default.h>
89   -
90   -#define CONFIG_CMD_IDE
91   -#define CONFIG_CMD_DHCP
92   -
93   -#undef CONFIG_CMD_BDI
94   -#undef CONFIG_CMD_BEDBUG
95   -#undef CONFIG_CMD_ELF
96   -#undef CONFIG_CMD_FAT
97   -#undef CONFIG_CMD_FLASH
98   -#undef CONFIG_CMD_FPGA
99   -#undef CONFIG_CMD_LOADB
100   -#undef CONFIG_CMD_LOADS
101   -#undef CONFIG_CMD_MII
102   -#undef CONFIG_CMD_NFS
103   -#undef CONFIG_CMD_SAVEENV
104   -#undef CONFIG_CMD_SOURCE
105   -
106   -
107   -/*
108   - * Miscellaneous configurable options
109   - */
110   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
111   -#define CONFIG_SYS_PROMPT "GTH2 # " /* Monitor Command Prompt */
112   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
113   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
114   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
115   -
116   -#define CONFIG_SYS_MALLOC_LEN 128*1024
117   -
118   -#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
119   -
120   -#define CONFIG_SYS_MHZ 500
121   -
122   -#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
123   -
124   -#define CONFIG_SYS_HZ 1000
125   -
126   -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
127   -
128   -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
129   -
130   -#define CONFIG_SYS_MEMTEST_START 0x80100000
131   -#define CONFIG_SYS_MEMTEST_END 0x83000000
132   -
133   -#define CONFIG_HW_WATCHDOG 1
134   -
135   -/*-----------------------------------------------------------------------
136   - * FLASH and environment organization
137   - */
138   -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
139   -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
140   -
141   -#define PHYS_FLASH 0xbfc00000 /* Flash Bank #1 */
142   -
143   -/* The following #defines are needed to get flash environment right */
144   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
145   -#define CONFIG_SYS_MONITOR_LEN (192 << 10)
146   -
147   -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
148   -
149   -/* We boot from this flash, selected with dip switch */
150   -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH
151   -
152   -/* timeout values are in ticks */
153   -#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
154   -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
155   -
156   -#define CONFIG_ENV_IS_NOWHERE 1
157   -
158   -/* Address and size of Primary Environment Sector */
159   -#define CONFIG_ENV_ADDR 0xB0030000
160   -#define CONFIG_ENV_SIZE 0x10000
161   -
162   -#define CONFIG_FLASH_16BIT
163   -
164   -#define CONFIG_NR_DRAM_BANKS 2
165   -
166   -
167   -#define CONFIG_MEMSIZE_IN_BYTES
168   -
169   -/*---ATA PCMCIA ------------------------------------*/
170   -#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
171   -
172   -#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
173   -#define CONFIG_SYS_PCMCIA_IO_BASE 0x28000000
174   -#define CONFIG_SYS_PCMCIA_ATTR_BASE 0x30000000
175   -
176   -#define CONFIG_PCMCIA_SLOT_A
177   -
178   -#define CONFIG_ATAPI 1
179   -#define CONFIG_MAC_PARTITION 1
180   -
181   -/* We run CF in "true ide" mode or a harddrive via pcmcia */
182   -#define CONFIG_IDE_PCMCIA 1
183   -
184   -/* We only support one slot for now */
185   -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
186   -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
187   -
188   -#undef CONFIG_IDE_LED /* LED for ide not supported */
189   -#undef CONFIG_IDE_RESET /* reset for ide not supported */
190   -
191   -#define CONFIG_SYS_ATA_IDE0_OFFSET 0
192   -
193   -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_IO_BASE
194   -
195   -/* Offset for data I/O */
196   -#define CONFIG_SYS_ATA_DATA_OFFSET 0
197   -
198   -/* Offset for normal register accesses */
199   -#define CONFIG_SYS_ATA_REG_OFFSET 0
200   -
201   -/* Offset for alternate registers */
202   -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
203   -
204   -/*-----------------------------------------------------------------------
205   - * Cache Configuration
206   - */
207   -#define CONFIG_SYS_DCACHE_SIZE 16384
208   -#define CONFIG_SYS_ICACHE_SIZE 16384
209   -#define CONFIG_SYS_CACHELINE_SIZE 32
210   -
211   -#define GPIO_CACONFIG (1<<0)
212   -#define GPIO_DPACONFIG (1<<6)
213   -#define GPIO_ERESET (1<<11)
214   -#define GPIO_EEDQ (1<<17)
215   -#define GPIO_WDI (1<<18)
216   -#define GPIO_RJ1LY (1<<22)
217   -#define GPIO_RJ1LG (1<<23)
218   -#define GPIO_LEDCLK (1<<29)
219   -#define GPIO_LEDD (1<<30)
220   -#define GPIO_CPU_LED (1<<31)
221   -
222   -#endif /* __CONFIG_H */