Eric Lee / smarc-uboot

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Commit 625509ab0edbb7d943ad9028de3c21ca48aa58be

Authored by Tom Rini
2 parents d5325eff10 0b23780ff0
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Showing 34 changed files Side-by-side Diff

... ... @@ -627,6 +627,9 @@
627 627 bool "Support hummingboard"
628 628 select CPU_V7
629 629  
  630 +config TARGET_KOSAGI_NOVENA
  631 + bool "Support Kosagi Novena"
  632 +
630 633 config TARGET_TQMA6
631 634 bool "TQ Systems TQMa6 board"
632 635 select CPU_V7
... ... @@ -892,6 +895,7 @@
892 895 source "board/isee/igep0033/Kconfig"
893 896 source "board/jornada/Kconfig"
894 897 source "board/karo/tx25/Kconfig"
  898 +source "board/kosagi/novena/Kconfig"
895 899 source "board/logicpd/imx27lite/Kconfig"
896 900 source "board/logicpd/imx31_litekit/Kconfig"
897 901 source "board/maxbcm/Kconfig"
arch/arm/cpu/armv7/mx6/clock.c
Diff comments   View file @ 625509a
... ... @@ -312,6 +312,10 @@
312 312 u32 reg, perclk_podf;
313 313  
314 314 reg = __raw_readl(&imx_ccm->cscmr1);
  315 +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
  316 + if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
  317 + return MXC_HCLK; /* OSC 24Mhz */
  318 +#endif
315 319 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
316 320  
317 321 return get_ipg_clk() / (perclk_podf + 1);
arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ 625509a
... ... @@ -240,6 +240,18 @@
240 240 writel(0, &mxc_ccm->ccdr);
241 241 }
242 242  
  243 +#ifdef CONFIG_MX6SL
  244 +static void set_preclk_from_osc(void)
  245 +{
  246 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  247 + u32 reg;
  248 +
  249 + reg = readl(&mxc_ccm->cscmr1);
  250 + reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
  251 + writel(reg, &mxc_ccm->cscmr1);
  252 +}
  253 +#endif
  254 +
243 255 int arch_cpu_init(void)
244 256 {
245 257 init_aips();
... ... @@ -254,6 +266,11 @@
254 266 */
255 267 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
256 268 set_ahb_rate(132000000);
  269 +
  270 + /* Set perclk to source from OSC 24MHz */
  271 +#if defined(CONFIG_MX6SL)
  272 + set_preclk_from_osc();
  273 +#endif
257 274  
258 275 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
259 276  
arch/arm/imx-common/iomux-v3.c
Diff comments   View file @ 625509a
... ... @@ -77,4 +77,19 @@
77 77 p += stride;
78 78 }
79 79 }
  80 +
  81 +void imx_iomux_set_gpr_register(int group, int start_bit,
  82 + int num_bits, int value)
  83 +{
  84 + int i = 0;
  85 + u32 reg;
  86 + reg = readl(base + group * 4);
  87 + while (num_bits) {
  88 + reg &= ~(1<<(start_bit + i));
  89 + i++;
  90 + num_bits--;
  91 + }
  92 + reg |= (value << start_bit);
  93 + writel(reg, base + group * 4);
  94 +}
arch/arm/imx-common/timer.c
Diff comments   View file @ 625509a
... ... @@ -12,6 +12,7 @@
12 12 #include <div64.h>
13 13 #include <asm/arch/imx-regs.h>
14 14 #include <asm/arch/clock.h>
  15 +#include <asm/arch/sys_proto.h>
15 16  
16 17 /* General purpose timers registers */
17 18 struct mxc_gpt {
18 19  
19 20  
20 21  
21 22  
22 23  
23 24  
... ... @@ -26,23 +27,59 @@
26 27  
27 28 /* General purpose timers bitfields */
28 29 #define GPTCR_SWR (1 << 15) /* Software reset */
  30 +#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
29 31 #define GPTCR_FRR (1 << 9) /* Freerun / restart */
30   -#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
  32 +#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
  33 +#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
  34 +#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
  35 +#define GPTCR_CLKSOURCE_MASK (0x7 << 6)
31 36 #define GPTCR_TEN 1 /* Timer enable */
32 37  
  38 +#define GPTPR_PRESCALER24M_SHIFT 12
  39 +#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
  40 +
33 41 DECLARE_GLOBAL_DATA_PTR;
34 42  
  43 +static inline int gpt_has_clk_source_osc(void)
  44 +{
  45 +#if defined(CONFIG_MX6)
  46 + if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
  47 + (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) ||
  48 + is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
  49 + return 1;
  50 +
  51 + return 0;
  52 +#else
  53 + return 0;
  54 +#endif
  55 +}
  56 +
  57 +static inline ulong gpt_get_clk(void)
  58 +{
  59 +#ifdef CONFIG_MXC_GPT_HCLK
  60 + if (gpt_has_clk_source_osc())
  61 + return MXC_HCLK >> 3;
  62 + else
  63 + return mxc_get_clock(MXC_IPG_PERCLK);
  64 +#else
  65 + return MXC_CLK32;
  66 +#endif
  67 +}
35 68 static inline unsigned long long tick_to_time(unsigned long long tick)
36 69 {
  70 + ulong gpt_clk = gpt_get_clk();
  71 +
37 72 tick *= CONFIG_SYS_HZ;
38   - do_div(tick, MXC_CLK32);
  73 + do_div(tick, gpt_clk);
39 74  
40 75 return tick;
41 76 }
42 77  
43 78 static inline unsigned long long us_to_tick(unsigned long long usec)
44 79 {
45   - usec = usec * MXC_CLK32 + 999999;
  80 + ulong gpt_clk = gpt_get_clk();
  81 +
  82 + usec = usec * gpt_clk + 999999;
46 83 do_div(usec, 1000000);
47 84  
48 85 return usec;
49 86  
50 87  
... ... @@ -59,12 +96,32 @@
59 96 for (i = 0; i < 100; i++)
60 97 __raw_writel(0, &cur_gpt->control);
61 98  
62   - __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
63   -
64   - /* Freerun Mode, PERCLK1 input */
65 99 i = __raw_readl(&cur_gpt->control);
66   - __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
  100 + i &= ~GPTCR_CLKSOURCE_MASK;
67 101  
  102 +#ifdef CONFIG_MXC_GPT_HCLK
  103 + if (gpt_has_clk_source_osc()) {
  104 + i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
  105 +
  106 + /* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */
  107 + if (is_cpu_type(MXC_CPU_MX6DL) ||
  108 + is_cpu_type(MXC_CPU_MX6SOLO) ||
  109 + is_cpu_type(MXC_CPU_MX6SX)) {
  110 + i |= GPTCR_24MEN;
  111 +
  112 + /* Produce 3Mhz clock */
  113 + __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
  114 + &cur_gpt->prescaler);
  115 + }
  116 + } else {
  117 + i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
  118 + }
  119 +#else
  120 + __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
  121 + i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
  122 +#endif
  123 + __raw_writel(i, &cur_gpt->control);
  124 +
68 125 gd->arch.tbl = __raw_readl(&cur_gpt->counter);
69 126 gd->arch.tbu = 0;
70 127  
... ... @@ -86,7 +143,7 @@
86 143 {
87 144 /*
88 145 * get_ticks() returns a long long (64 bit), it wraps in
89   - * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
  146 + * 2^64 / GPT_CLK = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
90 147 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
91 148 * 5 * 10^6 days - long enough.
92 149 */
... ... @@ -117,6 +174,6 @@
117 174 */
118 175 ulong get_tbclk(void)
119 176 {
120   - return MXC_CLK32;
  177 + return gpt_get_clk();
121 178 }
arch/arm/include/asm/arch-mx6/crm_regs.h
Diff comments   View file @ 625509a
... ... @@ -89,7 +89,7 @@
89 89 u32 analog_pll_video_tog;
90 90 u32 analog_pll_video_num; /* 0x40b0 */
91 91 u32 analog_reserved6[3];
92   - u32 analog_pll_vedio_denon; /* 0x40c0 */
  92 + u32 analog_pll_video_denom; /* 0x40c0 */
93 93 u32 analog_reserved7[7];
94 94 u32 analog_pll_enet; /* 0x40e0 */
95 95 u32 analog_pll_enet_set;
... ... @@ -228,6 +228,8 @@
228 228 #ifdef CONFIG_MX6SX
229 229 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
230 230 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
  231 +#endif
  232 +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
231 233 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
232 234 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
233 235 #endif
... ... @@ -931,10 +933,10 @@
931 933 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
932 934 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
933 935 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
934   -#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
935   -#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
936   -#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
937   - (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
  936 +#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
  937 +#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
  938 +#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
  939 + (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
938 940 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
939 941 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
940 942 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
arch/arm/include/asm/arch-mx6/mx6sl_pins.h
Diff comments   View file @ 625509a
... ... @@ -14,12 +14,31 @@
14 14 MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0),
15 15 MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0),
16 16 MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0),
  17 + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0),
  18 + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0),
  19 + MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0),
  20 + MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0),
  21 + MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0),
  22 + MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0),
  23 + MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0),
  24 + MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0),
  25 + MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0),
  26 + MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0),
  27 + MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0),
17 28 MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
18 29 MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
19 30 MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
20 31 MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
21 32 MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
22 33 MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
  34 + MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0),
  35 + MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0),
  36 + MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0),
  37 + MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0),
  38 + MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0),
  39 + MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0),
  40 + MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0),
  41 + MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0),
23 42 MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
24 43 MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
25 44  
arch/arm/include/asm/imx-common/iomux-v3.h
Diff comments   View file @ 625509a
... ... @@ -182,6 +182,11 @@
182 182 void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
183 183 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
184 184 unsigned count);
  185 +/*
  186 +* Set bits for general purpose registers
  187 +*/
  188 +void imx_iomux_set_gpr_register(int group, int start_bit,
  189 + int num_bits, int value);
185 190  
186 191 /* macros for declaring and using pinmux array */
187 192 #if defined(CONFIG_MX6QDL)
board/aristainetos/aristainetos.c
Diff comments   View file @ 625509a
... ... @@ -230,6 +230,12 @@
230 230 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
231 231 };
232 232  
  233 +int board_spi_cs_gpio(unsigned bus, unsigned cs)
  234 +{
  235 + return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
  236 + ? (IMX_GPIO_NR(3, 20)) : -1;
  237 +}
  238 +
233 239 static void setup_spi(void)
234 240 {
235 241 int i;
board/bachmann/ot1200/ot1200.c
Diff comments   View file @ 625509a
... ... @@ -104,10 +104,25 @@
104 104 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
105 105 }
106 106  
  107 +static iomux_v3_cfg_t const feature_pads[] = {
  108 + /* SD card detect */
  109 + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
  110 +
  111 + /* eMMC soldered? */
  112 + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
  113 +};
  114 +
  115 +static void setup_iomux_features(void)
  116 +{
  117 + imx_iomux_v3_setup_multiple_pads(feature_pads,
  118 + ARRAY_SIZE(feature_pads));
  119 +}
  120 +
107 121 int board_early_init_f(void)
108 122 {
109 123 setup_iomux_uart();
110 124 setup_iomux_spi();
  125 + setup_iomux_features();
111 126  
112 127 return 0;
113 128 }
114 129  
115 130  
116 131  
117 132  
118 133  
119 134  
120 135  
121 136  
... ... @@ -126,23 +141,68 @@
126 141 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 142 };
128 143  
  144 +iomux_v3_cfg_t const usdhc4_pads[] = {
  145 + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  146 + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  147 + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  148 + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  149 + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  150 + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  151 +};
  152 +
129 153 int board_mmc_getcd(struct mmc *mmc)
130 154 {
131   - return 1;
  155 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  156 + int ret;
  157 +
  158 + if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
  159 + gpio_direction_input(IMX_GPIO_NR(4, 5));
  160 + ret = gpio_get_value(IMX_GPIO_NR(4, 5));
  161 + } else {
  162 + gpio_direction_input(IMX_GPIO_NR(1, 4));
  163 + ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
  164 + }
  165 +
  166 + return ret;
132 167 }
133 168  
134   -struct fsl_esdhc_cfg usdhc_cfg[] = {
  169 +struct fsl_esdhc_cfg usdhc_cfg[2] = {
135 170 {USDHC3_BASE_ADDR},
  171 + {USDHC4_BASE_ADDR},
136 172 };
137 173  
138 174 int board_mmc_init(bd_t *bis)
139 175 {
  176 + s32 status = 0;
  177 + u32 index = 0;
  178 +
140 179 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  180 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  181 +
141 182 usdhc_cfg[0].max_bus_width = 8;
  183 + usdhc_cfg[1].max_bus_width = 4;
142 184  
143   - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  185 + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  186 + switch (index) {
  187 + case 0:
  188 + imx_iomux_v3_setup_multiple_pads(
  189 + usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  190 + break;
  191 + case 1:
  192 + imx_iomux_v3_setup_multiple_pads(
  193 + usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  194 + break;
  195 + default:
  196 + printf("Warning: you configured more USDHC controllers"
  197 + "(%d) then supported by the board (%d)\n",
  198 + index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  199 + return status;
  200 + }
144 201  
145   - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  202 + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  203 + }
  204 +
  205 + return status;
146 206 }
147 207  
148 208 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
board/compulab/cm_fx6/cm_fx6.c
Diff comments   View file @ 625509a
... ... @@ -31,12 +31,12 @@
31 31 #ifdef CONFIG_DWC_AHSATA
32 32 static int cm_fx6_issd_gpios[] = {
33 33 /* The order of the GPIOs in the array is important! */
  34 + CM_FX6_SATA_LDO_EN,
34 35 CM_FX6_SATA_PHY_SLP,
35 36 CM_FX6_SATA_NRSTDLY,
36 37 CM_FX6_SATA_PWREN,
37 38 CM_FX6_SATA_NSTANDBY1,
38 39 CM_FX6_SATA_NSTANDBY2,
39   - CM_FX6_SATA_LDO_EN,
40 40 };
41 41  
42 42 static void cm_fx6_sata_power(int on)
board/compulab/cm_fx6/spl.c
Diff comments   View file @ 625509a
... ... @@ -235,10 +235,11 @@
235 235  
236 236 spl_mx6s_dram_init(DDR_32BIT_1GB, false);
237 237 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
238   - if (bank1_size == 0x40000000)
239   - return 0;
240   -
  238 + bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000);
241 239 if (bank1_size == 0x20000000) {
  240 + if (bank2_size == 0x20000000)
  241 + return 0;
  242 +
242 243 spl_mx6s_dram_init(DDR_32BIT_512MB, true);
243 244 return 0;
244 245 }
board/freescale/mx6qsabreauto/mx6qsabreauto.c
Diff comments   View file @ 625509a
... ... @@ -27,6 +27,7 @@
27 27 #include <asm/arch/mxc_hdmi.h>
28 28 #include <asm/imx-common/video.h>
29 29 #include <asm/arch/crm_regs.h>
  30 +#include <pca953x.h>
30 31  
31 32 DECLARE_GLOBAL_DATA_PTR;
32 33  
... ... @@ -116,6 +117,44 @@
116 117 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
117 118 };
118 119  
  120 +/*Define for building port exp gpio, pin starts from 0*/
  121 +#define PORTEXP_IO_NR(chip, pin) \
  122 + ((chip << 5) + pin)
  123 +
  124 +/*Get the chip addr from a ioexp gpio*/
  125 +#define PORTEXP_IO_TO_CHIP(gpio_nr) \
  126 + (gpio_nr >> 5)
  127 +
  128 +/*Get the pin number from a ioexp gpio*/
  129 +#define PORTEXP_IO_TO_PIN(gpio_nr) \
  130 + (gpio_nr & 0x1f)
  131 +
  132 +static int port_exp_direction_output(unsigned gpio, int value)
  133 +{
  134 + int ret;
  135 +
  136 + i2c_set_bus_num(2);
  137 + ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
  138 + if (ret)
  139 + return ret;
  140 +
  141 + ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
  142 + (1 << PORTEXP_IO_TO_PIN(gpio)),
  143 + (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
  144 +
  145 + if (ret)
  146 + return ret;
  147 +
  148 + ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
  149 + (1 << PORTEXP_IO_TO_PIN(gpio)),
  150 + (value << PORTEXP_IO_TO_PIN(gpio)));
  151 +
  152 + if (ret)
  153 + return ret;
  154 +
  155 + return 0;
  156 +}
  157 +
119 158 static void setup_iomux_enet(void)
120 159 {
121 160 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
... ... @@ -361,4 +400,58 @@
361 400  
362 401 return 0;
363 402 }
  403 +
  404 +#ifdef CONFIG_USB_EHCI_MX6
  405 +#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
  406 +#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
  407 +
  408 +iomux_v3_cfg_t const usb_otg_pads[] = {
  409 + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
  410 +};
  411 +
  412 +int board_ehci_hcd_init(int port)
  413 +{
  414 + switch (port) {
  415 + case 0:
  416 + imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
  417 + ARRAY_SIZE(usb_otg_pads));
  418 +
  419 + /*
  420 + * Set daisy chain for otg_pin_id on 6q.
  421 + * For 6dl, this bit is reserved.
  422 + */
  423 + imx_iomux_set_gpr_register(1, 13, 1, 0);
  424 + break;
  425 + case 1:
  426 + break;
  427 + default:
  428 + printf("MXC USB port %d not yet supported\n", port);
  429 + return -EINVAL;
  430 + }
  431 + return 0;
  432 +}
  433 +
  434 +int board_ehci_power(int port, int on)
  435 +{
  436 + switch (port) {
  437 + case 0:
  438 + if (on)
  439 + port_exp_direction_output(USB_OTG_PWR, 1);
  440 + else
  441 + port_exp_direction_output(USB_OTG_PWR, 0);
  442 + break;
  443 + case 1:
  444 + if (on)
  445 + port_exp_direction_output(USB_HOST1_PWR, 1);
  446 + else
  447 + port_exp_direction_output(USB_HOST1_PWR, 0);
  448 + break;
  449 + default:
  450 + printf("MXC USB port %d not yet supported\n", port);
  451 + return -EINVAL;
  452 + }
  453 +
  454 + return 0;
  455 +}
  456 +#endif
board/freescale/mx6sabresd/mx6sabresd.c
Diff comments   View file @ 625509a
... ... @@ -51,6 +51,8 @@
51 51  
52 52 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
53 53  
  54 +#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
  55 +
54 56 int dram_init(void)
55 57 {
56 58 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
... ... @@ -141,6 +143,45 @@
141 143 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
142 144 };
143 145  
  146 +static iomux_v3_cfg_t const rgb_pads[] = {
  147 + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
  148 + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  149 + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  150 + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
  151 + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  152 + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  153 + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
  154 + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  155 + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
  156 + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  157 + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  158 + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
  159 + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  160 + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  161 + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  162 + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  163 + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  164 + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  165 + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
  166 + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  167 + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  168 + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
  169 + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
  170 + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
  171 + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
  172 + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
  173 + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
  174 + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  175 + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
  176 + MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
  177 +};
  178 +
  179 +static void enable_rgb(struct display_info_t const *dev)
  180 +{
  181 + imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
  182 + gpio_direction_output(DISP0_PWR_EN, 1);
  183 +}
  184 +
144 185 static struct i2c_pads_info i2c_pad_info1 = {
145 186 .scl = {
146 187 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
... ... @@ -356,6 +397,26 @@
356 397 .hsync_len = 60,
357 398 .vsync_len = 10,
358 399 .sync = FB_SYNC_EXT,
  400 + .vmode = FB_VMODE_NONINTERLACED
  401 +} }, {
  402 + .bus = 0,
  403 + .addr = 0,
  404 + .pixfmt = IPU_PIX_FMT_RGB24,
  405 + .detect = NULL,
  406 + .enable = enable_rgb,
  407 + .mode = {
  408 + .name = "SEIKO-WVGA",
  409 + .refresh = 60,
  410 + .xres = 800,
  411 + .yres = 480,
  412 + .pixclock = 29850,
  413 + .left_margin = 89,
  414 + .right_margin = 164,
  415 + .upper_margin = 23,
  416 + .lower_margin = 10,
  417 + .hsync_len = 10,
  418 + .vsync_len = 10,
  419 + .sync = 0,
359 420 .vmode = FB_VMODE_NONINTERLACED
360 421 } } };
361 422 size_t display_count = ARRAY_SIZE(displays);
board/freescale/mx6slevk/mx6slevk.c
Diff comments   View file @ 625509a
... ... @@ -52,6 +52,23 @@
52 52 MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
53 53 };
54 54  
  55 +static iomux_v3_cfg_t const usdhc1_pads[] = {
  56 + /* 8 bit SD */
  57 + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  58 + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  59 + MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  60 + MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  61 + MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  62 + MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  63 + MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  64 + MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  65 + MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66 + MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67 +
  68 + /*CD pin*/
  69 + MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
  70 +};
  71 +
55 72 static iomux_v3_cfg_t const usdhc2_pads[] = {
56 73 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 74 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 75  
... ... @@ -59,8 +76,23 @@
59 76 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60 77 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
61 78 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79 +
  80 + /*CD pin*/
  81 + MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
62 82 };
63 83  
  84 +static iomux_v3_cfg_t const usdhc3_pads[] = {
  85 + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86 + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87 + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88 + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89 + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90 + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91 +
  92 + /*CD pin*/
  93 + MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  94 +};
  95 +
64 96 static iomux_v3_cfg_t const fec_pads[] = {
65 97 MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 98 MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 99  
68 100  
69 101  
... ... @@ -109,21 +141,82 @@
109 141 gpio_set_value(ETH_PHY_RESET, 1);
110 142 }
111 143  
112   -static struct fsl_esdhc_cfg usdhc_cfg[1] = {
113   - {USDHC2_BASE_ADDR},
  144 +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
  145 +#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
  146 +#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
  147 +
  148 +static struct fsl_esdhc_cfg usdhc_cfg[3] = {
  149 + {USDHC1_BASE_ADDR},
  150 + {USDHC2_BASE_ADDR, 0, 4},
  151 + {USDHC3_BASE_ADDR, 0, 4},
114 152 };
115 153  
116 154 int board_mmc_getcd(struct mmc *mmc)
117 155 {
118   - return 1; /* Assume boot SD always present */
  156 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  157 + int ret = 0;
  158 +
  159 + switch (cfg->esdhc_base) {
  160 + case USDHC1_BASE_ADDR:
  161 + ret = !gpio_get_value(USDHC1_CD_GPIO);
  162 + break;
  163 + case USDHC2_BASE_ADDR:
  164 + ret = !gpio_get_value(USDHC2_CD_GPIO);
  165 + break;
  166 + case USDHC3_BASE_ADDR:
  167 + ret = !gpio_get_value(USDHC3_CD_GPIO);
  168 + break;
  169 + }
  170 +
  171 + return ret;
119 172 }
120 173  
121 174 int board_mmc_init(bd_t *bis)
122 175 {
123   - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  176 + int i, ret;
124 177  
125   - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
126   - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  178 + /*
  179 + * According to the board_mmc_init() the following map is done:
  180 + * (U-boot device node) (Physical Port)
  181 + * mmc0 USDHC1
  182 + * mmc1 USDHC2
  183 + * mmc2 USDHC3
  184 + */
  185 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  186 + switch (i) {
  187 + case 0:
  188 + imx_iomux_v3_setup_multiple_pads(
  189 + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  190 + gpio_direction_input(USDHC1_CD_GPIO);
  191 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  192 + break;
  193 + case 1:
  194 + imx_iomux_v3_setup_multiple_pads(
  195 + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  196 + gpio_direction_input(USDHC2_CD_GPIO);
  197 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  198 + break;
  199 + case 2:
  200 + imx_iomux_v3_setup_multiple_pads(
  201 + usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  202 + gpio_direction_input(USDHC3_CD_GPIO);
  203 + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  204 + break;
  205 + default:
  206 + printf("Warning: you configured more USDHC controllers"
  207 + "(%d) than supported by the board\n", i + 1);
  208 + return -EINVAL;
  209 + }
  210 +
  211 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  212 + if (ret) {
  213 + printf("Warning: failed to initialize "
  214 + "mmc dev %d\n", i);
  215 + return ret;
  216 + }
  217 + }
  218 +
  219 + return 0;
127 220 }
128 221  
129 222 #ifdef CONFIG_FEC_MXC
board/kosagi/novena/Kconfig
Diff comments   View file @ 625509a
  1 +if TARGET_KOSAGI_NOVENA
  2 +
  3 +config SYS_CPU
  4 + default "armv7"
  5 +
  6 +config SYS_BOARD
  7 + default "novena"
  8 +
  9 +config SYS_VENDOR
  10 + default "kosagi"
  11 +
  12 +config SYS_SOC
  13 + default "mx6"
  14 +
  15 +config SYS_CONFIG_NAME
  16 + default "novena"
  17 +
  18 +endif
board/kosagi/novena/Makefile
Diff comments   View file @ 625509a
  1 +#
  2 +# Copyright (C) 2014 Marek Vasut <marex@denx.de>
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +ifdef CONFIG_SPL_BUILD
  8 +obj-y := novena_spl.o
  9 +else
  10 +obj-y := novena.o
  11 +endif
board/kosagi/novena/novena.c
Diff comments   View file @ 625509a
  1 +/*
  2 + * Novena board support
  3 + *
  4 + * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <asm/errno.h>
  11 +#include <asm/gpio.h>
  12 +#include <asm/io.h>
  13 +#include <asm/arch/clock.h>
  14 +#include <asm/arch/crm_regs.h>
  15 +#include <asm/arch/imx-regs.h>
  16 +#include <asm/arch/iomux.h>
  17 +#include <asm/arch/mxc_hdmi.h>
  18 +#include <asm/arch/sys_proto.h>
  19 +#include <asm/imx-common/boot_mode.h>
  20 +#include <asm/imx-common/iomux-v3.h>
  21 +#include <asm/imx-common/mxc_i2c.h>
  22 +#include <asm/imx-common/sata.h>
  23 +#include <asm/imx-common/video.h>
  24 +#include <fsl_esdhc.h>
  25 +#include <i2c.h>
  26 +#include <input.h>
  27 +#include <ipu_pixfmt.h>
  28 +#include <linux/fb.h>
  29 +#include <linux/input.h>
  30 +#include <malloc.h>
  31 +#include <micrel.h>
  32 +#include <miiphy.h>
  33 +#include <mmc.h>
  34 +#include <netdev.h>
  35 +#include <power/pmic.h>
  36 +#include <power/pfuze100_pmic.h>
  37 +#include <stdio_dev.h>
  38 +
  39 +DECLARE_GLOBAL_DATA_PTR;
  40 +
  41 +#define NOVENA_BUTTON_GPIO IMX_GPIO_NR(4, 14)
  42 +#define NOVENA_SD_WP IMX_GPIO_NR(1, 2)
  43 +#define NOVENA_SD_CD IMX_GPIO_NR(1, 4)
  44 +
  45 +/*
  46 + * GPIO button
  47 + */
  48 +#ifdef CONFIG_KEYBOARD
  49 +static struct input_config button_input;
  50 +
  51 +static int novena_gpio_button_read_keys(struct input_config *input)
  52 +{
  53 + int key = KEY_ENTER;
  54 + if (gpio_get_value(NOVENA_BUTTON_GPIO))
  55 + return 0;
  56 + input_send_keycodes(&button_input, &key, 1);
  57 + return 1;
  58 +}
  59 +
  60 +static int novena_gpio_button_getc(struct stdio_dev *dev)
  61 +{
  62 + return input_getc(&button_input);
  63 +}
  64 +
  65 +static int novena_gpio_button_tstc(struct stdio_dev *dev)
  66 +{
  67 + return input_tstc(&button_input);
  68 +}
  69 +
  70 +static int novena_gpio_button_init(struct stdio_dev *dev)
  71 +{
  72 + gpio_direction_input(NOVENA_BUTTON_GPIO);
  73 + input_set_delays(&button_input, 250, 250);
  74 + return 0;
  75 +}
  76 +
  77 +int drv_keyboard_init(void)
  78 +{
  79 + int error;
  80 + struct stdio_dev dev = {
  81 + .name = "button",
  82 + .flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM,
  83 + .start = novena_gpio_button_init,
  84 + .getc = novena_gpio_button_getc,
  85 + .tstc = novena_gpio_button_tstc,
  86 + };
  87 +
  88 + error = input_init(&button_input, 0);
  89 + if (error) {
  90 + debug("%s: Cannot set up input\n", __func__);
  91 + return -1;
  92 + }
  93 + button_input.read_keys = novena_gpio_button_read_keys;
  94 +
  95 + error = input_stdio_register(&dev);
  96 + if (error)
  97 + return error;
  98 +
  99 + return 0;
  100 +}
  101 +#endif
  102 +
  103 +/*
  104 + * SDHC
  105 + */
  106 +#ifdef CONFIG_FSL_ESDHC
  107 +static struct fsl_esdhc_cfg usdhc_cfg[] = {
  108 + { USDHC3_BASE_ADDR, 0, 4 }, /* Micro SD */
  109 + { USDHC2_BASE_ADDR, 0, 4 }, /* Big SD */
  110 +};
  111 +
  112 +int board_mmc_getcd(struct mmc *mmc)
  113 +{
  114 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  115 +
  116 + /* There is no CD for a microSD card, assume always present. */
  117 + if (cfg->esdhc_base == USDHC3_BASE_ADDR)
  118 + return 1;
  119 + else
  120 + return !gpio_get_value(NOVENA_SD_CD);
  121 +}
  122 +
  123 +int board_mmc_getwp(struct mmc *mmc)
  124 +{
  125 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  126 +
  127 + /* There is no WP for a microSD card, assume always read-write. */
  128 + if (cfg->esdhc_base == USDHC3_BASE_ADDR)
  129 + return 0;
  130 + else
  131 + return gpio_get_value(NOVENA_SD_WP);
  132 +}
  133 +
  134 +
  135 +int board_mmc_init(bd_t *bis)
  136 +{
  137 + s32 status = 0;
  138 + int index;
  139 +
  140 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  141 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  142 +
  143 + /* Big SD write-protect and card-detect */
  144 + gpio_direction_input(NOVENA_SD_WP);
  145 + gpio_direction_input(NOVENA_SD_CD);
  146 +
  147 + for (index = 0; index < ARRAY_SIZE(usdhc_cfg); index++) {
  148 + status = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  149 + if (status)
  150 + return status;
  151 + }
  152 +
  153 + return status;
  154 +}
  155 +#endif
  156 +
  157 +/*
  158 + * Video over HDMI
  159 + */
  160 +#if defined(CONFIG_VIDEO_IPUV3)
  161 +static void enable_hdmi(struct display_info_t const *dev)
  162 +{
  163 + imx_enable_hdmi_phy();
  164 +}
  165 +
  166 +struct display_info_t const displays[] = {
  167 + {
  168 + /* HDMI Output */
  169 + .bus = -1,
  170 + .addr = 0,
  171 + .pixfmt = IPU_PIX_FMT_RGB24,
  172 + .detect = detect_hdmi,
  173 + .enable = enable_hdmi,
  174 + .mode = {
  175 + .name = "HDMI",
  176 + .refresh = 60,
  177 + .xres = 1024,
  178 + .yres = 768,
  179 + .pixclock = 15385,
  180 + .left_margin = 220,
  181 + .right_margin = 40,
  182 + .upper_margin = 21,
  183 + .lower_margin = 7,
  184 + .hsync_len = 60,
  185 + .vsync_len = 10,
  186 + .sync = FB_SYNC_EXT,
  187 + .vmode = FB_VMODE_NONINTERLACED
  188 + }
  189 + }
  190 +};
  191 +
  192 +size_t display_count = ARRAY_SIZE(displays);
  193 +
  194 +static void setup_display(void)
  195 +{
  196 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  197 + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  198 +
  199 + enable_ipu_clock();
  200 + imx_setup_hdmi();
  201 +
  202 + /* Turn on LDB0,IPU,IPU DI0 clocks */
  203 + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  204 +
  205 + /* set LDB0, LDB1 clk select to 011/011 */
  206 + clrsetbits_le32(&mxc_ccm->cs2cdr,
  207 + MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
  208 + MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK,
  209 + (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
  210 + (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
  211 +
  212 + setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  213 +
  214 + setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
  215 + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  216 +
  217 + writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
  218 + IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
  219 + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  220 + IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
  221 + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
  222 + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  223 + IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
  224 + IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
  225 + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
  226 + &iomux->gpr[2]);
  227 +
  228 + clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
  229 + IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  230 + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  231 +}
  232 +#endif
  233 +
  234 +int board_early_init_f(void)
  235 +{
  236 +#if defined(CONFIG_VIDEO_IPUV3)
  237 + setup_display();
  238 +#endif
  239 +
  240 + return 0;
  241 +}
  242 +
  243 +int board_init(void)
  244 +{
  245 + /* address of boot parameters */
  246 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  247 +
  248 +#ifdef CONFIG_CMD_SATA
  249 + setup_sata();
  250 +#endif
  251 +
  252 + return 0;
  253 +}
  254 +
  255 +int checkboard(void)
  256 +{
  257 + puts("Board: Novena 4x\n");
  258 + return 0;
  259 +}
  260 +
  261 +int dram_init(void)
  262 +{
  263 + gd->ram_size = imx_ddr_size();
  264 + return 0;
  265 +}
  266 +
  267 +/* setup board specific PMIC */
  268 +int power_init_board(void)
  269 +{
  270 + struct pmic *p;
  271 + u32 reg;
  272 + int ret;
  273 +
  274 + power_pfuze100_init(1);
  275 + p = pmic_get("PFUZE100");
  276 + if (!p)
  277 + return -EINVAL;
  278 +
  279 + ret = pmic_probe(p);
  280 + if (ret)
  281 + return ret;
  282 +
  283 + pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
  284 + printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
  285 +
  286 + /* Set SWBST to 5.0V and enable (for USB) */
  287 + pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
  288 + reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
  289 + reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
  290 + pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
  291 +
  292 + return 0;
  293 +}
  294 +
  295 +/* EEPROM configuration data */
  296 +struct novena_eeprom_data {
  297 + uint8_t signature[6];
  298 + uint8_t version;
  299 + uint8_t reserved;
  300 + uint32_t serial;
  301 + uint8_t mac[6];
  302 + uint16_t features;
  303 +};
  304 +
  305 +int misc_init_r(void)
  306 +{
  307 + struct novena_eeprom_data data;
  308 + uchar *datap = (uchar *)&data;
  309 + const char *signature = "Novena";
  310 + int ret;
  311 +
  312 + /* If 'ethaddr' is already set, do nothing. */
  313 + if (getenv("ethaddr"))
  314 + return 0;
  315 +
  316 + /* EEPROM is at bus 2. */
  317 + ret = i2c_set_bus_num(2);
  318 + if (ret) {
  319 + puts("Cannot select EEPROM I2C bus.\n");
  320 + return 0;
  321 + }
  322 +
  323 + /* EEPROM is at address 0x56. */
  324 + ret = eeprom_read(0x56, 0, datap, sizeof(data));
  325 + if (ret) {
  326 + puts("Cannot read I2C EEPROM.\n");
  327 + return 0;
  328 + }
  329 +
  330 + /* Check EEPROM signature. */
  331 + if (memcmp(data.signature, signature, 6)) {
  332 + puts("Invalid I2C EEPROM signature.\n");
  333 + return 0;
  334 + }
  335 +
  336 + /* Set ethernet address from EEPROM. */
  337 + eth_setenv_enetaddr("ethaddr", data.mac);
  338 +
  339 + return ret;
  340 +}
board/kosagi/novena/novena_spl.c
Diff comments   View file @ 625509a
  1 +/*
  2 + * Novena SPL
  3 + *
  4 + * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <asm/io.h>
  11 +#include <asm/arch/clock.h>
  12 +#include <asm/arch/iomux.h>
  13 +#include <asm/arch/mx6-ddr.h>
  14 +#include <asm/arch/mx6-pins.h>
  15 +#include <asm/arch/sys_proto.h>
  16 +#include <asm/gpio.h>
  17 +#include <asm/imx-common/boot_mode.h>
  18 +#include <asm/imx-common/iomux-v3.h>
  19 +#include <asm/imx-common/mxc_i2c.h>
  20 +#include <i2c.h>
  21 +#include <mmc.h>
  22 +#include <fsl_esdhc.h>
  23 +#include <spl.h>
  24 +
  25 +#include <asm/arch/mx6-ddr.h>
  26 +
  27 +DECLARE_GLOBAL_DATA_PTR;
  28 +
  29 +#define UART_PAD_CTRL \
  30 + (PAD_CTL_PKE | PAD_CTL_PUE | \
  31 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  32 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  33 +
  34 +#define USDHC_PAD_CTRL \
  35 + (PAD_CTL_PKE | PAD_CTL_PUE | \
  36 + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  37 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  38 +
  39 +#define ENET_PAD_CTRL \
  40 + (PAD_CTL_PKE | PAD_CTL_PUE | \
  41 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  42 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  43 +
  44 +#define ENET_PHY_CFG_PAD_CTRL \
  45 + (PAD_CTL_PKE | PAD_CTL_PUE | \
  46 + PAD_CTL_PUS_22K_UP | PAD_CTL_HYS)
  47 +
  48 +#define RGMII_PAD_CTRL \
  49 + (PAD_CTL_PKE | PAD_CTL_PUE | \
  50 + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  51 +
  52 +#define SPI_PAD_CTRL \
  53 + (PAD_CTL_HYS | \
  54 + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
  55 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  56 +
  57 +#define I2C_PAD_CTRL \
  58 + (PAD_CTL_PKE | PAD_CTL_PUE | \
  59 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  60 + PAD_CTL_DSE_240ohm | PAD_CTL_HYS | \
  61 + PAD_CTL_ODE)
  62 +
  63 +#define BUTTON_PAD_CTRL \
  64 + (PAD_CTL_PKE | PAD_CTL_PUE | \
  65 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  66 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  67 +
  68 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  69 +
  70 +#define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17)
  71 +#define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7)
  72 +#define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4)
  73 +#define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29)
  74 +#define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12)
  75 +#define NOVENA_PCIE_WAKE_UP_GPIO IMX_GPIO_NR(3, 22)
  76 +#define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16)
  77 +
  78 +/*
  79 + * Audio
  80 + */
  81 +static iomux_v3_cfg_t audio_pads[] = {
  82 + /* AUD_PWRON */
  83 + MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
  84 +};
  85 +
  86 +static void novena_spl_setup_iomux_audio(void)
  87 +{
  88 + imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads));
  89 + gpio_direction_output(NOVENA_AUDIO_PWRON, 1);
  90 +}
  91 +
  92 +/*
  93 + * ENET
  94 + */
  95 +static iomux_v3_cfg_t enet_pads1[] = {
  96 + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  97 + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98 + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  99 + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  100 + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  101 + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  102 + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  103 + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  104 + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  105 +
  106 + /* pin 35, PHY_AD2 */
  107 + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  108 + /* pin 32, MODE0 */
  109 + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  110 + /* pin 31, MODE1 */
  111 + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  112 + /* pin 28, MODE2 */
  113 + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  114 + /* pin 27, MODE3 */
  115 + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  116 + /* pin 33, CLK125_EN */
  117 + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  118 +
  119 + /* pin 42 PHY nRST */
  120 + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
  121 +};
  122 +
  123 +static iomux_v3_cfg_t enet_pads2[] = {
  124 + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  125 + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  126 + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  127 + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  128 + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  129 + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  130 +};
  131 +
  132 +static void novena_spl_setup_iomux_enet(void)
  133 +{
  134 + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
  135 +
  136 + /* Assert Ethernet PHY nRST */
  137 + gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
  138 +
  139 + /*
  140 + * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset
  141 + * de-assertion. The intention is to use weak signal drivers (pull-ups)
  142 + * to prevent the conflict between PHY pins becoming outputs after
  143 + * reset and imx6 still driving the pins. The issue is described in PHY
  144 + * datasheet, p.14
  145 + */
  146 + gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */
  147 + gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */
  148 + gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */
  149 + gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */
  150 + gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */
  151 + gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */
  152 +
  153 + /* Following reset timing (p.53, fig.8 from the PHY datasheet) */
  154 + mdelay(10);
  155 +
  156 + /* De-assert Ethernet PHY nRST */
  157 + gpio_set_value(IMX_GPIO_NR(3, 23), 1);
  158 +
  159 + /* PHY is now configured, connect FEC to the pads */
  160 + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
  161 +
  162 + /*
  163 + * PHY datasheet recommends on p.53 to wait at least 100us after reset
  164 + * before using MII, so we enforce the delay here
  165 + */
  166 + udelay(100);
  167 +}
  168 +
  169 +/*
  170 + * FPGA
  171 + */
  172 +static iomux_v3_cfg_t fpga_pads[] = {
  173 + /* FPGA_RESET_N */
  174 + MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  175 +};
  176 +
  177 +static void novena_spl_setup_iomux_fpga(void)
  178 +{
  179 + imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads));
  180 + gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0);
  181 +}
  182 +
  183 +/*
  184 + * GPIO Button
  185 + */
  186 +static iomux_v3_cfg_t button_pads[] = {
  187 + /* Debug */
  188 + MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  189 +};
  190 +
  191 +static void novena_spl_setup_iomux_buttons(void)
  192 +{
  193 + imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads));
  194 +}
  195 +
  196 +/*
  197 + * I2C
  198 + */
  199 +/*
  200 + * I2C1:
  201 + * 0x1d ... MMA7455L
  202 + * 0x30 ... SO-DIMM temp sensor
  203 + * 0x44 ... STMPE610
  204 + * 0x50 ... SO-DIMM ID
  205 + */
  206 +struct i2c_pads_info i2c_pad_info0 = {
  207 + .scl = {
  208 + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  209 + .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
  210 + .gp = IMX_GPIO_NR(3, 21)
  211 + },
  212 + .sda = {
  213 + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  214 + .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
  215 + .gp = IMX_GPIO_NR(3, 28)
  216 + }
  217 +};
  218 +
  219 +/*
  220 + * I2C2:
  221 + * 0x08 ... PMIC
  222 + * 0x3a ... HDMI DCC
  223 + * 0x50 ... HDMI DCC
  224 + */
  225 +static struct i2c_pads_info i2c_pad_info1 = {
  226 + .scl = {
  227 + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
  228 + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
  229 + .gp = IMX_GPIO_NR(2, 30)
  230 + },
  231 + .sda = {
  232 + .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
  233 + .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
  234 + .gp = IMX_GPIO_NR(3, 16)
  235 + }
  236 +};
  237 +
  238 +/*
  239 + * I2C3:
  240 + * 0x11 ... ES8283
  241 + * 0x50 ... LCD EDID
  242 + * 0x56 ... EEPROM
  243 + */
  244 +static struct i2c_pads_info i2c_pad_info2 = {
  245 + .scl = {
  246 + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
  247 + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
  248 + .gp = IMX_GPIO_NR(3, 17)
  249 + },
  250 + .sda = {
  251 + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
  252 + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
  253 + .gp = IMX_GPIO_NR(3, 18)
  254 + }
  255 +};
  256 +
  257 +static void novena_spl_setup_iomux_i2c(void)
  258 +{
  259 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
  260 + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  261 + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  262 +}
  263 +
  264 +/*
  265 + * PCI express
  266 + */
  267 +#ifdef CONFIG_CMD_PCI
  268 +static iomux_v3_cfg_t pcie_pads[] = {
  269 + /* "Reset" pin */
  270 + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  271 + /* "Power on" pin */
  272 + MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  273 + /* "Wake up" pin (input) */
  274 + MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  275 + /* "Disable endpoint" (rfkill) pin */
  276 + MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
  277 +};
  278 +
  279 +static void novena_spl_setup_iomux_pcie(void)
  280 +{
  281 + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
  282 +
  283 + /* Ensure PCIe is powered down */
  284 + gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0);
  285 +
  286 + /* Put the card into reset */
  287 + gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0);
  288 +
  289 + /* Input signal to wake system from mPCIe card */
  290 + gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO);
  291 +
  292 + /* Drive RFKILL high, to ensure the radio is turned on */
  293 + gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1);
  294 +}
  295 +#else
  296 +static inline void novena_spl_setup_iomux_pcie(void) {}
  297 +#endif
  298 +
  299 +/*
  300 + * SDHC
  301 + */
  302 +static iomux_v3_cfg_t usdhc2_pads[] = {
  303 + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  304 + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  305 + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  306 + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  307 + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  308 + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  309 + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
  310 + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  311 +};
  312 +
  313 +static iomux_v3_cfg_t usdhc3_pads[] = {
  314 + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  315 + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  316 + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  317 + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  318 + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  319 + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  320 +};
  321 +
  322 +static void novena_spl_setup_iomux_sdhc(void)
  323 +{
  324 + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  325 + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  326 +
  327 + /* Big SD write-protect and card-detect */
  328 + gpio_direction_input(IMX_GPIO_NR(1, 2));
  329 + gpio_direction_input(IMX_GPIO_NR(1, 4));
  330 +}
  331 +
  332 +/*
  333 + * SPI
  334 + */
  335 +#ifdef CONFIG_MXC_SPI
  336 +static iomux_v3_cfg_t ecspi3_pads[] = {
  337 + /* SS1 */
  338 + MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  339 + MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  340 + MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  341 + MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  342 + MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  343 + MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  344 + MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL),
  345 +};
  346 +
  347 +static void novena_spl_setup_iomux_spi(void)
  348 +{
  349 + imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
  350 + /* De-assert the nCS */
  351 + gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1);
  352 + gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1);
  353 + gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1);
  354 +}
  355 +#else
  356 +static void novena_spl_setup_iomux_spi(void) {}
  357 +#endif
  358 +
  359 +/*
  360 + * UART
  361 + */
  362 +static iomux_v3_cfg_t const uart2_pads[] = {
  363 + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  364 + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  365 +};
  366 +
  367 +static iomux_v3_cfg_t const uart3_pads[] = {
  368 + MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  369 + MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  370 +};
  371 +
  372 +static iomux_v3_cfg_t const uart4_pads[] = {
  373 + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  374 + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  375 + MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  376 + MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  377 +
  378 +};
  379 +
  380 +static void novena_spl_setup_iomux_uart(void)
  381 +{
  382 + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  383 + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  384 + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  385 +}
  386 +
  387 +/*
  388 + * Video
  389 + */
  390 +#ifdef CONFIG_VIDEO
  391 +static iomux_v3_cfg_t hdmi_pads[] = {
  392 + /* "Ghost HPD" pin */
  393 + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  394 +};
  395 +
  396 +static void novena_spl_setup_iomux_video(void)
  397 +{
  398 + imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads));
  399 + gpio_direction_input(NOVENA_HDMI_GHOST_HPD);
  400 +}
  401 +#else
  402 +static inline void novena_spl_setup_iomux_video(void) {}
  403 +#endif
  404 +
  405 +/*
  406 + * SPL boots from uSDHC card
  407 + */
  408 +#ifdef CONFIG_FSL_ESDHC
  409 +static struct fsl_esdhc_cfg usdhc_cfg = {
  410 + USDHC3_BASE_ADDR, 0, 4
  411 +};
  412 +
  413 +int board_mmc_getcd(struct mmc *mmc)
  414 +{
  415 + /* There is no CD for a microSD card, assume always present. */
  416 + return 1;
  417 +}
  418 +
  419 +int board_mmc_init(bd_t *bis)
  420 +{
  421 + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  422 + return fsl_esdhc_initialize(bis, &usdhc_cfg);
  423 +}
  424 +#endif
  425 +
  426 +/* Configure MX6Q/DUAL mmdc DDR io registers */
  427 +static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = {
  428 + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  429 + .dram_sdclk_0 = 0x00020038,
  430 + .dram_sdclk_1 = 0x00020038,
  431 + .dram_cas = 0x00000038,
  432 + .dram_ras = 0x00000038,
  433 + .dram_reset = 0x00000038,
  434 + /* SDCKE[0:1]: 100k pull-up */
  435 + .dram_sdcke0 = 0x00003000,
  436 + .dram_sdcke1 = 0x00003000,
  437 + /* SDBA2: pull-up disabled */
  438 + .dram_sdba2 = 0x00000000,
  439 + /* SDODT[0:1]: 100k pull-up, 40 ohm */
  440 + .dram_sdodt0 = 0x00000038,
  441 + .dram_sdodt1 = 0x00000038,
  442 + /* SDQS[0:7]: Differential input, 40 ohm */
  443 + .dram_sdqs0 = 0x00000038,
  444 + .dram_sdqs1 = 0x00000038,
  445 + .dram_sdqs2 = 0x00000038,
  446 + .dram_sdqs3 = 0x00000038,
  447 + .dram_sdqs4 = 0x00000038,
  448 + .dram_sdqs5 = 0x00000038,
  449 + .dram_sdqs6 = 0x00000038,
  450 + .dram_sdqs7 = 0x00000038,
  451 +
  452 + /* DQM[0:7]: Differential input, 40 ohm */
  453 + .dram_dqm0 = 0x00000038,
  454 + .dram_dqm1 = 0x00000038,
  455 + .dram_dqm2 = 0x00000038,
  456 + .dram_dqm3 = 0x00000038,
  457 + .dram_dqm4 = 0x00000038,
  458 + .dram_dqm5 = 0x00000038,
  459 + .dram_dqm6 = 0x00000038,
  460 + .dram_dqm7 = 0x00000038,
  461 +};
  462 +
  463 +/* Configure MX6Q/DUAL mmdc GRP io registers */
  464 +static struct mx6dq_iomux_grp_regs novena_grp_ioregs = {
  465 + /* DDR3 */
  466 + .grp_ddr_type = 0x000c0000,
  467 + .grp_ddrmode_ctl = 0x00020000,
  468 + /* Disable DDR pullups */
  469 + .grp_ddrpke = 0x00000000,
  470 + /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  471 + .grp_addds = 0x00000038,
  472 + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  473 + .grp_ctlds = 0x00000038,
  474 + /* DATA[00:63]: Differential input, 40 ohm */
  475 + .grp_ddrmode = 0x00020000,
  476 + .grp_b0ds = 0x00000038,
  477 + .grp_b1ds = 0x00000038,
  478 + .grp_b2ds = 0x00000038,
  479 + .grp_b3ds = 0x00000038,
  480 + .grp_b4ds = 0x00000038,
  481 + .grp_b5ds = 0x00000038,
  482 + .grp_b6ds = 0x00000038,
  483 + .grp_b7ds = 0x00000038,
  484 +};
  485 +
  486 +static struct mx6_mmdc_calibration novena_mmdc_calib = {
  487 + /* write leveling calibration determine */
  488 + .p0_mpwldectrl0 = 0x00420048,
  489 + .p0_mpwldectrl1 = 0x006f0059,
  490 + .p1_mpwldectrl0 = 0x005a0104,
  491 + .p1_mpwldectrl1 = 0x01070113,
  492 + /* Read DQS Gating calibration */
  493 + .p0_mpdgctrl0 = 0x437c040b,
  494 + .p0_mpdgctrl1 = 0x0413040e,
  495 + .p1_mpdgctrl0 = 0x444f0446,
  496 + .p1_mpdgctrl1 = 0x044d0422,
  497 + /* Read Calibration: DQS delay relative to DQ read access */
  498 + .p0_mprddlctl = 0x4c424249,
  499 + .p1_mprddlctl = 0x4e48414f,
  500 + /* Write Calibration: DQ/DM delay relative to DQS write access */
  501 + .p0_mpwrdlctl = 0x42414641,
  502 + .p1_mpwrdlctl = 0x46374b43,
  503 +};
  504 +
  505 +static struct mx6_ddr_sysinfo novena_ddr_info = {
  506 + /* Width of data bus: 0=16, 1=32, 2=64 */
  507 + .dsize = 2,
  508 + /* Config for full 4GB range so that get_mem_size() works */
  509 + .cs_density = 32, /* 32Gb per CS */
  510 + /* Single chip select */
  511 + .ncs = 1,
  512 + .cs1_mirror = 0,
  513 + .rtt_wr = 1, /* RTT_Wr = RZQ/4 */
  514 + .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
  515 + .walat = 3, /* Write additional latency */
  516 + .ralat = 7, /* Read additional latency */
  517 + .mif3_mode = 3, /* Command prediction working mode */
  518 + .bi_on = 1, /* Bank interleaving enabled */
  519 + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  520 + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  521 +};
  522 +
  523 +static struct mx6_ddr3_cfg elpida_4gib_1600 = {
  524 + .mem_speed = 1600,
  525 + .density = 4,
  526 + .width = 64,
  527 + .banks = 8,
  528 + .rowaddr = 16,
  529 + .coladdr = 10,
  530 + .pagesz = 2,
  531 + .trcd = 1300,
  532 + .trcmin = 4900,
  533 + .trasmin = 3590,
  534 +};
  535 +
  536 +/*
  537 + * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
  538 + * - we have a stack and a place to store GD, both in SRAM
  539 + * - no variable global data is available
  540 + */
  541 +void board_init_f(ulong dummy)
  542 +{
  543 + /* setup AIPS and disable watchdog */
  544 + arch_cpu_init();
  545 +
  546 + /* setup GP timer */
  547 + timer_init();
  548 +
  549 +#ifdef CONFIG_BOARD_POSTCLK_INIT
  550 + board_postclk_init();
  551 +#endif
  552 +#ifdef CONFIG_FSL_ESDHC
  553 + get_clocks();
  554 +#endif
  555 +
  556 + /* Setup IOMUX and configure basics. */
  557 + novena_spl_setup_iomux_audio();
  558 + novena_spl_setup_iomux_buttons();
  559 + novena_spl_setup_iomux_enet();
  560 + novena_spl_setup_iomux_fpga();
  561 + novena_spl_setup_iomux_i2c();
  562 + novena_spl_setup_iomux_pcie();
  563 + novena_spl_setup_iomux_sdhc();
  564 + novena_spl_setup_iomux_spi();
  565 + novena_spl_setup_iomux_uart();
  566 + novena_spl_setup_iomux_video();
  567 +
  568 + /* UART clocks enabled and gd valid - init serial console */
  569 + preloader_console_init();
  570 +
  571 + /* Start the DDR DRAM */
  572 + mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
  573 + mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);
  574 +
  575 + /* Clear the BSS. */
  576 + memset(__bss_start, 0, __bss_end - __bss_start);
  577 +
  578 + /* load/boot image from boot device */
  579 + board_init_r(NULL, 0);
  580 +}
  581 +
  582 +void reset_cpu(ulong addr)
  583 +{
  584 +}
board/kosagi/novena/setup.cfg
Diff comments   View file @ 625509a
  1 +/*
  2 + * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +/* image version */
  13 +IMAGE_VERSION 2
  14 +
  15 +/* Boot Device : sd */
  16 +BOOT_FROM sd
  17 +
  18 +#define __ASSEMBLY__
  19 +#include <config.h>
  20 +#include "asm/arch/iomux.h"
  21 +#include "asm/arch/crm_regs.h"
  22 +
  23 +/* set the default clock gate to save power */
  24 +DATA 4, CCM_CCGR0, 0x00C03F3F
  25 +DATA 4, CCM_CCGR1, 0x0030FC03
  26 +DATA 4, CCM_CCGR2, 0x0FFFC000
  27 +DATA 4, CCM_CCGR3, 0x3FF00000
  28 +DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
  29 +DATA 4, CCM_CCGR5, 0x0F0000C3
  30 +DATA 4, CCM_CCGR6, 0x000003FF
  31 +
  32 +/* enable AXI cache for VDOA/VPU/IPU */
  33 +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
  34 +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  35 +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
  36 +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
  37 +
  38 +/*
  39 + * Setup CCM_CCOSR register as follows:
  40 + *
  41 + * cko1_en = 1 --> CKO1 enabled
  42 + * cko1_div = 111 --> divide by 8
  43 + * cko1_sel = 1011 --> ahb_clk_root
  44 + *
  45 + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
  46 + */
  47 +DATA 4, CCM_CCOSR, 0x000000fb
board/tqc/tqma6/tqma6.c
Diff comments   View file @ 625509a
... ... @@ -138,8 +138,10 @@
138 138 NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
139 139 };
140 140  
  141 +#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
  142 +
141 143 static unsigned const tqma6_ecspi1_cs[] = {
142   - IMX_GPIO_NR(3, 19),
  144 + TQMA6_SF_CS_GPIO,
143 145 };
144 146  
145 147 static void tqma6_iomuxc_spi(void)
... ... @@ -150,6 +152,12 @@
150 152 gpio_direction_output(tqma6_ecspi1_cs[i], 1);
151 153 imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
152 154 ARRAY_SIZE(tqma6_ecspi1_pads));
  155 +}
  156 +
  157 +int board_spi_cs_gpio(unsigned bus, unsigned cs)
  158 +{
  159 + return ((bus == CONFIG_SF_DEFAULT_BUS) &&
  160 + (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
153 161 }
154 162  
155 163 static struct i2c_pads_info tqma6_i2c3_pads = {
board/tqc/tqma6/tqma6_bb.h
Diff comments   View file @ 625509a
... ... @@ -6,7 +6,7 @@
6 6 */
7 7  
8 8 #ifndef __TQMA6_BB__
9   -#define __TQMA6_BB
  9 +#define __TQMA6_BB__
10 10  
11 11 #include <common.h>
12 12  
configs/novena_defconfig
Diff comments   View file @ 625509a
  1 +CONFIG_SPL=y
  2 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kosagi/novena/setup.cfg,MX6Q,SPL"
  3 ++S:CONFIG_ARM=y
  4 ++S:CONFIG_TARGET_KOSAGI_NOVENA=y
drivers/mtd/nand/mxs_nand.c
Diff comments   View file @ 625509a
... ... @@ -146,8 +146,13 @@
146 146 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
147 147 uint32_t page_oob_size)
148 148 {
149   - if (page_data_size == 2048)
150   - return 8;
  149 + if (page_data_size == 2048) {
  150 + if (page_oob_size == 64)
  151 + return 8;
  152 +
  153 + if (page_oob_size == 112)
  154 + return 14;
  155 + }
151 156  
152 157 if (page_data_size == 4096) {
153 158 if (page_oob_size == 128)
include/configs/aristainetos.h
Diff comments   View file @ 625509a
... ... @@ -77,7 +77,7 @@
77 77 #define CONFIG_SPI_FLASH_STMICRO
78 78 #define CONFIG_MXC_SPI
79 79 #define CONFIG_SF_DEFAULT_BUS 3
80   -#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 20)<<8))
  80 +#define CONFIG_SF_DEFAULT_CS 0
81 81 #define CONFIG_SF_DEFAULT_SPEED 20000000
82 82 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
83 83 #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
include/configs/imx6_spl.h
Diff comments   View file @ 625509a
... ... @@ -27,7 +27,7 @@
27 27 #define CONFIG_SYS_THUMB_BUILD
28 28 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
29 29 #define CONFIG_SPL_TEXT_BASE 0x00908000
30   -#define CONFIG_SPL_MAX_SIZE (64 * 1024)
  30 +#define CONFIG_SPL_MAX_SIZE 0x10000
31 31 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7"
32 32 #define CONFIG_SPL_STACK 0x0091FFB8
33 33 #define CONFIG_SPL_LIBCOMMON_SUPPORT
include/configs/m28evk.h
Diff comments   View file @ 625509a
... ... @@ -171,6 +171,7 @@
171 171 #define CONFIG_EXTRA_ENV_SETTINGS \
172 172 "consdev=ttyAMA0\0" \
173 173 "baudrate=115200\0" \
  174 + "bootscript=boot.scr\0" \
174 175 "bootdev=/dev/mmcblk0p2\0" \
175 176 "rootdev=/dev/mmcblk0p3\0" \
176 177 "netdev=eth0\0" \
include/configs/mx6_common.h
Diff comments   View file @ 625509a
... ... @@ -29,6 +29,7 @@
29 29 #endif
30 30  
31 31 #define CONFIG_MP
  32 +#define CONFIG_MXC_GPT_HCLK
32 33  
33 34 #endif
include/configs/mx6qsabreauto.h
Diff comments   View file @ 625509a
... ... @@ -32,6 +32,9 @@
32 32 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
33 33 #define CONFIG_MXC_USB_FLAGS 0
34 34  
  35 +#define CONFIG_PCA953X
  36 +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
  37 +
35 38 #include "mx6sabre_common.h"
36 39  
37 40 #define CONFIG_SYS_FSL_USDHC_NUM 2
include/configs/mx6slevk.h
Diff comments   View file @ 625509a
... ... @@ -190,7 +190,6 @@
190 190 #define CONFIG_ENV_OFFSET (6 * SZ_64K)
191 191 #define CONFIG_ENV_SIZE SZ_8K
192 192 #define CONFIG_ENV_IS_IN_MMC
193   -#define CONFIG_SYS_MMC_ENV_DEV 0
194 193  
195 194 #define CONFIG_OF_LIBFDT
196 195 #define CONFIG_CMD_BOOTZ
... ... @@ -208,6 +207,11 @@
208 207 #define CONFIG_SF_DEFAULT_CS 0
209 208 #define CONFIG_SF_DEFAULT_SPEED 20000000
210 209 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  210 +#endif
  211 +
  212 +#define CONFIG_SYS_FSL_USDHC_NUM 3
  213 +#if defined(CONFIG_ENV_IS_IN_MMC)
  214 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/
211 215 #endif
212 216  
213 217 #endif /* __CONFIG_H */
include/configs/novena.h
Diff comments   View file @ 625509a
  1 +/*
  2 + * Configuration settings for the Novena U-boot.
  3 + *
  4 + * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __CONFIG_H
  10 +#define __CONFIG_H
  11 +
  12 +/* System configurations */
  13 +#define CONFIG_MX6
  14 +#define CONFIG_BOARD_EARLY_INIT_F
  15 +#define CONFIG_MISC_INIT_R
  16 +#define CONFIG_DISPLAY_BOARDINFO
  17 +#define CONFIG_DISPLAY_CPUINFO
  18 +#define CONFIG_DOS_PARTITION
  19 +#define CONFIG_FAT_WRITE
  20 +#define CONFIG_FIT
  21 +#define CONFIG_KEYBOARD
  22 +#define CONFIG_MXC_GPIO
  23 +#define CONFIG_OF_LIBFDT
  24 +#define CONFIG_REGEX
  25 +#define CONFIG_SYS_GENERIC_BOARD
  26 +#define CONFIG_SYS_NO_FLASH
  27 +
  28 +#include "configs/mx6_common.h"
  29 +#include <asm/arch/imx-regs.h>
  30 +#include <asm/imx-common/gpio.h>
  31 +#include <config_cmd_default.h>
  32 +
  33 +/* U-Boot Commands */
  34 +#define CONFIG_CMD_ASKENV
  35 +#define CONFIG_CMD_BMODE
  36 +#define CONFIG_CMD_BOOTZ
  37 +#define CONFIG_CMD_CACHE
  38 +#define CONFIG_CMD_DHCP
  39 +#define CONFIG_CMD_EEPROM
  40 +#define CONFIG_CMD_EXT4
  41 +#define CONFIG_CMD_EXT4_WRITE
  42 +#define CONFIG_CMD_FAT
  43 +#define CONFIG_CMD_FS_GENERIC
  44 +#define CONFIG_CMD_I2C
  45 +#define CONFIG_CMD_FUSE
  46 +#define CONFIG_CMD_MII
  47 +#define CONFIG_CMD_MMC
  48 +#define CONFIG_CMD_NET
  49 +#define CONFIG_CMD_PCI
  50 +#define CONFIG_CMD_PING
  51 +#define CONFIG_CMD_SATA
  52 +#define CONFIG_CMD_SETEXPR
  53 +#define CONFIG_CMD_TIME
  54 +#define CONFIG_CMD_USB
  55 +#define CONFIG_VIDEO
  56 +
  57 +/* U-Boot general configurations */
  58 +#define CONFIG_SYS_LONGHELP
  59 +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
  60 +#define CONFIG_SYS_PBSIZE \
  61 + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  62 + /* Print buffer size */
  63 +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
  64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  65 + /* Boot argument buffer size */
  66 +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
  67 +#define CONFIG_AUTO_COMPLETE /* Command auto complete */
  68 +#define CONFIG_CMDLINE_EDITING /* Command history etc */
  69 +#define CONFIG_SYS_HUSH_PARSER
  70 +
  71 +/* U-Boot environment */
  72 +#define CONFIG_ENV_OVERWRITE
  73 +#define CONFIG_ENV_SIZE (16 * 1024)
  74 +/*
  75 + * Environment is on MMC, starting at offset 512KiB from start of the card.
  76 + * Please place first partition at offset 1MiB from the start of the card
  77 + * as recommended by GNU/fdisk. See below for details:
  78 + * http://homepage.ntlworld.com./jonathan.deboynepollard/FGA/disc-partition-alignment.html
  79 + */
  80 +#ifdef CONFIG_CMD_MMC
  81 +#define CONFIG_ENV_IS_IN_MMC
  82 +#define CONFIG_SYS_MMC_ENV_DEV 0
  83 +#define CONFIG_ENV_OFFSET (512 * 1024)
  84 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  85 +#define CONFIG_ENV_OFFSET_REDUND \
  86 + (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
  87 +#else
  88 +#define CONFIG_ENV_IS_NOWHERE
  89 +#endif
  90 +
  91 +/* Booting Linux */
  92 +#define CONFIG_BOOTDELAY 5
  93 +#define CONFIG_BOOTFILE "fitImage"
  94 +#define CONFIG_BOOTARGS "console=ttymxc1,115200 "
  95 +#define CONFIG_BOOTCOMMAND "run net_nfs"
  96 +#define CONFIG_LOADADDR 0x18000000
  97 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  98 +#define CONFIG_HOSTNAME novena
  99 +
  100 +/* Physical Memory Map */
  101 +#define CONFIG_NR_DRAM_BANKS 1
  102 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
  103 +#define PHYS_SDRAM_SIZE 0xF0000000
  104 +
  105 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
  106 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
  107 +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
  108 +
  109 +#define CONFIG_SYS_INIT_SP_OFFSET \
  110 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  111 +#define CONFIG_SYS_INIT_SP_ADDR \
  112 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  113 +
  114 +#define CONFIG_SYS_MEMTEST_START 0x10000000
  115 +#define CONFIG_SYS_MEMTEST_END 0x20000000
  116 +
  117 +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
  118 +
  119 +/* SPL */
  120 +#define CONFIG_SPL_FAT_SUPPORT
  121 +#define CONFIG_SPL_MMC_SUPPORT
  122 +#include "imx6_spl.h" /* common IMX6 SPL configuration */
  123 +
  124 +#define CONFIG_CMDLINE_TAG
  125 +#define CONFIG_SETUP_MEMORY_TAGS
  126 +#define CONFIG_INITRD_TAG
  127 +#define CONFIG_REVISION_TAG
  128 +
  129 +/* Ethernet Configuration */
  130 +#ifdef CONFIG_CMD_NET
  131 +#define CONFIG_FEC_MXC
  132 +#define CONFIG_MII
  133 +#define IMX_FEC_BASE ENET_BASE_ADDR
  134 +#define CONFIG_FEC_XCV_TYPE RGMII
  135 +#define CONFIG_ETHPRIME "FEC"
  136 +#define CONFIG_FEC_MXC_PHYADDR 0x7
  137 +#define CONFIG_PHYLIB
  138 +#define CONFIG_PHY_MICREL
  139 +#define CONFIG_PHY_MICREL_KSZ9021
  140 +#define CONFIG_ARP_TIMEOUT 200UL
  141 +#endif
  142 +
  143 +/* I2C */
  144 +#define CONFIG_SYS_I2C
  145 +#define CONFIG_SYS_I2C_MXC
  146 +#define CONFIG_I2C_MULTI_BUS
  147 +#define CONFIG_I2C_MXC
  148 +#define CONFIG_SYS_I2C_SPEED 100000
  149 +
  150 +/* I2C EEPROM */
  151 +#ifdef CONFIG_CMD_EEPROM
  152 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  153 +#define CONFIG_SYS_SPD_BUS_NUM 2
  154 +#endif
  155 +
  156 +/* MMC Configs */
  157 +#ifdef CONFIG_CMD_MMC
  158 +#define CONFIG_MMC
  159 +#define CONFIG_GENERIC_MMC
  160 +#define CONFIG_BOUNCE_BUFFER
  161 +#define CONFIG_FSL_ESDHC
  162 +#define CONFIG_FSL_USDHC
  163 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  164 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  165 +#endif
  166 +
  167 +/* OCOTP Configs */
  168 +#ifdef CONFIG_CMD_FUSE
  169 +#define CONFIG_MXC_OCOTP
  170 +#endif
  171 +
  172 +/* PCI express */
  173 +#ifdef CONFIG_CMD_PCI
  174 +#define CONFIG_PCI
  175 +#define CONFIG_PCI_PNP
  176 +#define CONFIG_PCI_SCAN_SHOW
  177 +#define CONFIG_PCIE_IMX
  178 +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29)
  179 +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12)
  180 +#endif
  181 +
  182 +/* PMIC */
  183 +#define CONFIG_POWER
  184 +#define CONFIG_POWER_I2C
  185 +#define CONFIG_POWER_PFUZE100
  186 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
  187 +
  188 +/* SATA Configs */
  189 +#ifdef CONFIG_CMD_SATA
  190 +#define CONFIG_DWC_AHSATA
  191 +#define CONFIG_SYS_SATA_MAX_DEVICE 1
  192 +#define CONFIG_DWC_AHSATA_PORT_ID 0
  193 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
  194 +#define CONFIG_LBA48
  195 +#define CONFIG_LIBATA
  196 +#endif
  197 +
  198 +/* UART */
  199 +#define CONFIG_MXC_UART
  200 +#define CONFIG_MXC_UART_BASE UART2_BASE
  201 +#define CONFIG_BAUDRATE 115200
  202 +#define CONFIG_CONS_INDEX 1
  203 +
  204 +/* USB Configs */
  205 +#ifdef CONFIG_CMD_USB
  206 +#define CONFIG_USB_EHCI
  207 +#define CONFIG_USB_EHCI_MX6
  208 +#define CONFIG_USB_STORAGE
  209 +#define CONFIG_USB_KEYBOARD
  210 +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
  211 +#define CONFIG_USB_HOST_ETHER
  212 +#define CONFIG_USB_ETHER_ASIX
  213 +#define CONFIG_USB_ETHER_SMSC95XX
  214 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  215 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  216 +#define CONFIG_MXC_USB_FLAGS 0
  217 +/* Gadget part */
  218 +#define CONFIG_CI_UDC
  219 +#define CONFIG_USBD_HS
  220 +#define CONFIG_USB_GADGET_DUALSPEED
  221 +#define CONFIG_USB_ETHER
  222 +#define CONFIG_USB_ETH_CDC
  223 +#define CONFIG_NETCONSOLE
  224 +#endif
  225 +
  226 +/* Video output */
  227 +#ifdef CONFIG_VIDEO
  228 +#define CONFIG_VIDEO
  229 +#define CONFIG_VIDEO_IPUV3
  230 +#define CONFIG_CFB_CONSOLE
  231 +#define CONFIG_VGA_AS_SINGLE_DEVICE
  232 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  233 +#define CONFIG_VIDEO_BMP_RLE8
  234 +#define CONFIG_SPLASH_SCREEN
  235 +#define CONFIG_BMP_16BPP
  236 +#define CONFIG_VIDEO_LOGO
  237 +#define CONFIG_IPUV3_CLK 260000000
  238 +#define CONFIG_CMD_HDMIDETECT
  239 +#define CONFIG_CONSOLE_MUX
  240 +#define CONFIG_IMX_HDMI
  241 +#define CONFIG_IMX_VIDEO_SKIP
  242 +#endif
  243 +
  244 +/* Extra U-Boot environment. */
  245 +#define CONFIG_EXTRA_ENV_SETTINGS \
  246 + "fdt_high=0xffffffff\0" \
  247 + "initrd_high=0xffffffff\0" \
  248 + "consdev=ttymxc1\0" \
  249 + "baudrate=115200\0" \
  250 + "bootdev=/dev/mmcblk0p1\0" \
  251 + "rootdev=/dev/mmcblk0p2\0" \
  252 + "netdev=eth0\0" \
  253 + "kernel_addr_r=0x18000000\0" \
  254 + "addcons=" \
  255 + "setenv bootargs ${bootargs} " \
  256 + "console=${consdev},${baudrate}\0" \
  257 + "addip=" \
  258 + "setenv bootargs ${bootargs} " \
  259 + "ip=${ipaddr}:${serverip}:${gatewayip}:" \
  260 + "${netmask}:${hostname}:${netdev}:off\0" \
  261 + "addmisc=" \
  262 + "setenv bootargs ${bootargs} ${miscargs}\0" \
  263 + "addargs=run addcons addmisc\0" \
  264 + "mmcload=" \
  265 + "mmc rescan ; " \
  266 + "ext4load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \
  267 + "netload=" \
  268 + "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
  269 + "miscargs=nohlt panic=1\0" \
  270 + "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
  271 + "nfsargs=" \
  272 + "setenv bootargs root=/dev/nfs rw " \
  273 + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
  274 + "mmc_mmc=" \
  275 + "run mmcload mmcargs addargs ; " \
  276 + "bootm ${kernel_addr_r}\0" \
  277 + "mmc_nfs=" \
  278 + "run mmcload nfsargs addip addargs ; " \
  279 + "bootm ${kernel_addr_r}\0" \
  280 + "net_mmc=" \
  281 + "run netload mmcargs addargs ; " \
  282 + "bootm ${kernel_addr_r}\0" \
  283 + "net_nfs=" \
  284 + "run netload nfsargs addip addargs ; " \
  285 + "bootm ${kernel_addr_r}\0" \
  286 + "update_sd_spl_filename=SPL\0" \
  287 + "update_sd_uboot_filename=u-boot.img\0" \
  288 + "update_sd_firmware=" /* Update the SD firmware partition */ \
  289 + "if mmc rescan ; then " \
  290 + "if dhcp ${update_sd_spl_filename} ; then " \
  291 + "mmc write ${loadaddr} 2 0x200 ; " \
  292 + "fi ; " \
  293 + "if dhcp ${update_sd_uboot_filename} ; then " \
  294 + "fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\
  295 + "fi ; " \
  296 + "fi\0" \
  297 +
  298 +#endif /* __CONFIG_H */
include/configs/tqma6.h
Diff comments   View file @ 625509a
... ... @@ -9,13 +9,26 @@
9 9 #ifndef __CONFIG_H
10 10 #define __CONFIG_H
11 11  
  12 +#define CONFIG_MX6
  13 +
  14 +/* SPL */
  15 +/* #if defined(CONFIG_SPL_BUILD) */
  16 +
  17 +#define CONFIG_SPL_MMC_SUPPORT
  18 +#define CONFIG_SPL_SPI_SUPPORT
  19 +#define CONFIG_SPL_FAT_SUPPORT
  20 +#define CONFIG_SPL_EXT_SUPPORT
  21 +
  22 +/* common IMX6 SPL configuration */
  23 +#include "imx6_spl.h"
  24 +
  25 +/* #endif */
  26 +
12 27 #include "mx6_common.h"
13 28 #include <asm/arch/imx-regs.h>
14 29 #include <asm/imx-common/gpio.h>
15 30 #include <linux/sizes.h>
16 31  
17   -#define CONFIG_MX6
18   -
19 32 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
20 33 #define PHYS_SDRAM_SIZE (512u * SZ_1M)
21 34 #elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
... ... @@ -57,7 +70,7 @@
57 70  
58 71 #define CONFIG_CMD_SF
59 72 #define CONFIG_SF_DEFAULT_BUS 0
60   -#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(3, 19) << 8))
  73 +#define CONFIG_SF_DEFAULT_CS 0
61 74 #define CONFIG_SF_DEFAULT_SPEED 50000000
62 75 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
63 76  
include/configs/wandboard.h
Diff comments   View file @ 625509a
... ... @@ -78,6 +78,15 @@
78 78 #define CONFIG_CMD_FAT
79 79 #define CONFIG_DOS_PARTITION
80 80  
  81 +/* USB Configs */
  82 +#define CONFIG_CMD_USB
  83 +#define CONFIG_USB_EHCI
  84 +#define CONFIG_USB_EHCI_MX6
  85 +#define CONFIG_USB_STORAGE
  86 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  87 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  88 +#define CONFIG_MXC_USB_FLAGS 0
  89 +
81 90 /* Ethernet Configuration */
82 91 #define CONFIG_CMD_PING
83 92 #define CONFIG_CMD_DHCP
... ... @@ -587,7 +587,7 @@
587 587 *
588 588 * The remaining fraction of a block bytes would not be loaded!
589 589 */
590   - *header_size_ptr = ROUND(sbuf->st_size, 4096);
  590 + *header_size_ptr = ROUND((sbuf->st_size + imximage_ivt_offset), 4096);
591 591  
592 592 if (csf_ptr && imximage_csf_size) {
593 593 *csf_ptr = params->ep - imximage_init_loadsize +