powerpc/mpc85xx: Add T2080/T2081 SoC support

Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>

powerpc/mpc85xx: Add T2080/T2081 SoC support
Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
Shengzhou Liu · York Sun
1 parent 82a55c1ef8
Showing 10 changed files with 512 additions and 1 deletions Side-by-side Diff
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/cpu/mpc85xx/t2080_ids.c
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
arch/powerpc/cpu/mpc8xxx/cpu.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/processor.h
drivers/net/fm/Makefile
drivers/net/fm/t2080.c
@@ -50,6 +50,8 @@
 obj-$(CONFIG_PPC_T1042)	+= t1040_ids.o
 obj-$(CONFIG_PPC_T1020)	+= t1040_ids.o
 obj-$(CONFIG_PPC_T1022)	+= t1040_ids.o
+obj-$(CONFIG_PPC_T2080) += t2080_ids.o
+obj-$(CONFIG_PPC_T2081) += t2080_ids.o
  
  
 obj-$(CONFIG_QE)	+= qe_io.o
@@ -93,6 +95,8 @@
 obj-$(CONFIG_PPC_T1042)	+= t1040_serdes.o
 obj-$(CONFIG_PPC_T1020)	+= t1040_serdes.o
 obj-$(CONFIG_PPC_T1022)	+= t1040_serdes.o
+obj-$(CONFIG_PPC_T2080) += t2080_serdes.o
+obj-$(CONFIG_PPC_T2081) += t2080_serdes.o
  
 obj-y	+= cpu.o
 obj-y	+= cpu_init.o
@@ -122,7 +122,7 @@
 		sys_info->freq_processor[cpu] =
 			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
-#ifdef CONFIG_PPC_B4860
+#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080)
 #define FM1_CLK_SEL	0xe0000000
 #define FM1_CLK_SHIFT	29
 #else
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	/* dqrr liodn, frame data liodn, liodn off, sdest */
+	SET_QP_INFO(1, 27, 1, 0),
+	SET_QP_INFO(2, 28, 1, 0),
+	SET_QP_INFO(3, 29, 1, 1),
+	SET_QP_INFO(4, 30, 1, 1),
+	SET_QP_INFO(5, 31, 1, 2),
+	SET_QP_INFO(6, 32, 1, 2),
+	SET_QP_INFO(7, 33, 1, 3),
+	SET_QP_INFO(8, 34, 1, 3),
+	SET_QP_INFO(9, 35, 1, 0),
+	SET_QP_INFO(10, 36, 1, 0),
+	SET_QP_INFO(11, 37, 1, 1),
+	SET_QP_INFO(12, 38, 1, 1),
+	SET_QP_INFO(13, 39, 1, 2),
+	SET_QP_INFO(14, 40, 1, 2),
+	SET_QP_INFO(15, 41, 1, 3),
+	SET_QP_INFO(16, 42, 1, 3),
+	SET_QP_INFO(17, 43, 1, 0),
+	SET_QP_INFO(18, 44, 1, 0),
+};
+#endif
+
+#ifdef CONFIG_SYS_SRIO
+struct srio_liodn_id_table srio_liodn_tbl[] = {
+	SET_SRIO_LIODN_BASE(1, 307),
+	SET_SRIO_LIODN_BASE(2, 387),
+};
+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	SET_QMAN_LIODN(62),
+	SET_BMAN_LIODN(63),
+#endif
+
+	SET_SDHC_LIODN(1, 552),
+
+	SET_PME_LIODN(117),
+
+	SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+	SET_USB_LIODN(2, "fsl-usb2-dr", 554),
+
+	SET_SATA_LIODN(1, 555),
+	SET_SATA_LIODN(2, 556),
+
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
+
+	SET_DMA_LIODN(1, 147),
+	SET_DMA_LIODN(2, 227),
+	SET_DMA_LIODN(3, 226),
+
+	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+
+#ifdef CONFIG_SYS_PMAN
+	SET_PMAN_LIODN(1, 513),
+	SET_PMAN_LIODN(2, 514),
+	SET_PMAN_LIODN(3, 515),
+#endif
+
+	/* SET_NEXUS_LIODN(557), -- not yet implemented */
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(1, 0, 88),
+	SET_FMAN_RX_1G_LIODN(1, 1, 89),
+	SET_FMAN_RX_1G_LIODN(1, 2, 90),
+	SET_FMAN_RX_1G_LIODN(1, 3, 91),
+	SET_FMAN_RX_1G_LIODN(1, 4, 92),
+	SET_FMAN_RX_1G_LIODN(1, 5, 93),
+	SET_FMAN_RX_10G_LIODN(1, 0, 94),
+	SET_FMAN_RX_10G_LIODN(1, 1, 95),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+	SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+	SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+	SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+	SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+	SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+	SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
+	SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
+	SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
+	SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
+	SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
+	SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct liodn_id_table rman_liodn_tbl[] = {
+	/* Set RMan block 0-3 liodn offset */
+	SET_RMAN_LIODN(0, 6),
+	SET_RMAN_LIODN(1, 7),
+	SET_RMAN_LIODN(2, 8),
+	SET_RMAN_LIODN(3, 9),
+};
+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+#ifdef CONFIG_SYS_DPAA_DCE
+	[FSL_HW_PORTAL_DCE]  = SET_LIODN_BASE_2(618, 694),
+#endif
+	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+	[FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(770, 846),
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+	[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
+#endif
+};
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include "fsl_corenet2_serdes.h"
+
+struct serdes_config {
+	u32 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+};
+
+static const struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, PCIE4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, PCIE4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xDE, {PCIE3, PCIE3, PCIE3, PCIE3,
+		PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
+	{0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4,
+		PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
+	{0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
+	{0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, PCIE1,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+#if defined(CONFIG_PPC_T2080)
+	{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM1_MAC1, XFI_FM1_MAC2,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
+		SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
+		PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
+		PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
+		PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM1_MAC1, XFI_FM1_MAC2,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0xAB, {PCIE3, PCIE3, PCIE3, PCIE3,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0xDA, {PCIE3, PCIE3, PCIE3, PCIE3,
+		PCIE3, PCIE3, PCIE3, PCIE3} },
+	{0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM1_MAC1, XFI_FM1_MAC2,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+
+#elif defined(CONFIG_PPC_T2081)
+	{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+#endif
+	{}
+};
+
+#ifndef CONFIG_PPC_T2081
+static const struct serdes_config serdes2_cfg_tbl[] = {
+	/* SerDes 2 */
+	{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
+	{0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
+	{0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+	{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
+	{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
+	{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
+	{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
+	{0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+	{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
+	{}
+};
+#endif
+
+static const struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+#ifndef CONFIG_PPC_T2081
+	serdes2_cfg_tbl,
+#endif
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	const struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	const struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
@@ -75,6 +75,8 @@
 	CPU_TYPE_ENTRY(T1020, T1020, 0),
 	CPU_TYPE_ENTRY(T1021, T1021, 0),
 	CPU_TYPE_ENTRY(T1022, T1022, 0),
+	CPU_TYPE_ENTRY(T2080, T2080, 0),
+	CPU_TYPE_ENTRY(T2081, T2081, 0),
 	CPU_TYPE_ENTRY(BSC9130, 9130, 1),
 	CPU_TYPE_ENTRY(BSC9131, 9131, 1),
 	CPU_TYPE_ENTRY(BSC9132, 9132, 2),
@@ -718,6 +718,50 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
  
+#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#define CONFIG_E6500
+#define CONFIG_SYS_PPC64		/* 64-bit core */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	2
+#define CONFIG_SYS_FSL_QMAN_V3
+#define CONFIG_MAX_CPUS			4
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCI_VER_3_X
+#if defined(CONFIG_PPC_T2080)
+#define CONFIG_SYS_NUM_FM1_DTSEC	8
+#define CONFIG_SYS_NUM_FM1_10GEC	4
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_FSL_SRIO_LIODN
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#elif defined(CONFIG_PPC_T2081)
+#define CONFIG_SYS_NUM_FM1_DTSEC	6
+#define CONFIG_SYS_NUM_FM1_10GEC	2
+#endif
+#define CONFIG_SYS_FSL_NUM_USB_CTRLS	2
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_PME_PLAT_CLK_DIV		1
+#define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
+#define CONFIG_SYS_FM1_CLK		0
+#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v3.0"
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+#define CONFIG_SYS_FSL_ISBC_VER		2
+
 #elif defined(CONFIG_PPC_C29X)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_FSL_SDHC_V2_3
@@ -1759,6 +1759,12 @@
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00fe0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	17
+#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xff000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00ff0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	16
+#define FSL_CORENET_RCWSR6_BOOT_LOC		0x0f800000
 #endif
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1	0x00800000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2	0x00400000
@@ -1822,6 +1828,15 @@
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII	0x08000000
 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO		0x10000000
 #endif
+#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC1_GPIO		0x40000000
+#define FSL_CORENET_RCWSR13_EC2			0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII	0x08000000
+#define FSL_CORENET_RCWSR13_EC2_GPIO		0x10000000
+#endif
 	u8	res18[192];
 	u32	scratchrw[4];	/* Scratch Read/Write */
 	u8	res19[240];
@@ -2818,6 +2833,7 @@
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET		0x100000
 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET		0x101000
+#define CONFIG_SYS_MPC85xx_DMA3_OFFSET		0x102000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET		CONFIG_SYS_MPC85xx_DMA1_OFFSET
 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x110000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x114000
@@ -1127,6 +1127,8 @@
 #define SVR_T1020	0x852100
 #define SVR_T1021	0x852101
 #define SVR_T1022	0x852102
+#define SVR_T2080	0x853000
+#define SVR_T2081	0x853100
  
 #define SVR_8610	0x80A000
 #define SVR_8641	0x809000
@@ -28,6 +28,8 @@
 obj-$(CONFIG_PPC_T1042)	+= t1040.o
 obj-$(CONFIG_PPC_T1020)	+= t1040.o
 obj-$(CONFIG_PPC_T1022)	+= t1040.o
+obj-$(CONFIG_PPC_T2080) += t2080.o
+obj-$(CONFIG_PPC_T2081) += t2080.o
 obj-$(CONFIG_PPC_T4240) += t4240.o
 obj-$(CONFIG_PPC_T4160) += t4240.o
 obj-$(CONFIG_PPC_B4420) += b4860.o
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+u32 port_to_devdisr[] = {
+	[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
+	[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
+	[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
+	[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
+	[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
+	[FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
+	[FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
+	[FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
+	[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
+	[FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
+	[FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3,
+	[FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 devdisr2 = in_be32(&gur->devdisr2);
+
+	return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+	if (is_device_disabled(port))
+		return PHY_INTERFACE_MODE_NONE;
+
+	if ((port == FM1_10GEC1 || port == FM1_10GEC2 ||
+	     port == FM1_10GEC3 || port == FM1_10GEC4) &&
+	    ((is_serdes_configured(XAUI_FM1_MAC9))	||
+	     (is_serdes_configured(XFI_FM1_MAC1))	||
+	     (is_serdes_configured(XFI_FM1_MAC2))	||
+	     (is_serdes_configured(XFI_FM1_MAC9))	||
+	     (is_serdes_configured(XFI_FM1_MAC10))))
+		return PHY_INTERFACE_MODE_XGMII;
+
+	if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+		FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII))
+		return PHY_INTERFACE_MODE_RGMII;
+
+	if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+		FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII))
+		return PHY_INTERFACE_MODE_RGMII;
+
+	if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+		FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII))
+		return PHY_INTERFACE_MODE_RGMII;
+
+	switch (port) {
+	case FM1_DTSEC1:
+	case FM1_DTSEC2:
+	case FM1_DTSEC3:
+	case FM1_DTSEC4:
+	case FM1_DTSEC5:
+	case FM1_DTSEC6:
+	case FM1_DTSEC9:
+	case FM1_DTSEC10:
+		if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+			return PHY_INTERFACE_MODE_SGMII;
+		break;
+	default:
+		return PHY_INTERFACE_MODE_NONE;
+	}
+
+	return PHY_INTERFACE_MODE_NONE;
+}
...	...	@@ -50,6 +50,8 @@
50	50	obj-$(CONFIG_PPC_T1042) += t1040_ids.o
51	51	obj-$(CONFIG_PPC_T1020) += t1040_ids.o
52	52	obj-$(CONFIG_PPC_T1022) += t1040_ids.o
	53	+obj-$(CONFIG_PPC_T2080) += t2080_ids.o
	54	+obj-$(CONFIG_PPC_T2081) += t2080_ids.o
53	55
54	56
55	57	obj-$(CONFIG_QE) += qe_io.o
...	...	@@ -93,6 +95,8 @@
93	95	obj-$(CONFIG_PPC_T1042) += t1040_serdes.o
94	96	obj-$(CONFIG_PPC_T1020) += t1040_serdes.o
95	97	obj-$(CONFIG_PPC_T1022) += t1040_serdes.o
	98	+obj-$(CONFIG_PPC_T2080) += t2080_serdes.o
	99	+obj-$(CONFIG_PPC_T2081) += t2080_serdes.o
96	100
97	101	obj-y += cpu.o
98	102	obj-y += cpu_init.o
...	...	@@ -122,7 +122,7 @@
122	122	sys_info->freq_processor[cpu] =
123	123	freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
124	124	}
125		-#ifdef CONFIG_PPC_B4860
	125	+#if defined(CONFIG_PPC_B4860) \|\| defined(CONFIG_PPC_T2080)
126	126	#define FM1_CLK_SEL 0xe0000000
127	127	#define FM1_CLK_SHIFT 29
128	128	#else
	1	+/*
	2	+ * Copyright 2013 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <common.h>
	8	+#include <asm/fsl_portals.h>
	9	+#include <asm/fsl_liodn.h>
	10	+
	11	+#ifdef CONFIG_SYS_DPAA_QBMAN
	12	+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
	13	+ /* dqrr liodn, frame data liodn, liodn off, sdest */
	14	+ SET_QP_INFO(1, 27, 1, 0),
	15	+ SET_QP_INFO(2, 28, 1, 0),
	16	+ SET_QP_INFO(3, 29, 1, 1),
	17	+ SET_QP_INFO(4, 30, 1, 1),
	18	+ SET_QP_INFO(5, 31, 1, 2),
	19	+ SET_QP_INFO(6, 32, 1, 2),
	20	+ SET_QP_INFO(7, 33, 1, 3),
	21	+ SET_QP_INFO(8, 34, 1, 3),
	22	+ SET_QP_INFO(9, 35, 1, 0),
	23	+ SET_QP_INFO(10, 36, 1, 0),
	24	+ SET_QP_INFO(11, 37, 1, 1),
	25	+ SET_QP_INFO(12, 38, 1, 1),
	26	+ SET_QP_INFO(13, 39, 1, 2),
	27	+ SET_QP_INFO(14, 40, 1, 2),
	28	+ SET_QP_INFO(15, 41, 1, 3),
	29	+ SET_QP_INFO(16, 42, 1, 3),
	30	+ SET_QP_INFO(17, 43, 1, 0),
	31	+ SET_QP_INFO(18, 44, 1, 0),
	32	+};
	33	+#endif
	34	+
	35	+#ifdef CONFIG_SYS_SRIO
	36	+struct srio_liodn_id_table srio_liodn_tbl[] = {
	37	+ SET_SRIO_LIODN_BASE(1, 307),
	38	+ SET_SRIO_LIODN_BASE(2, 387),
	39	+};
	40	+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
	41	+#endif
	42	+
	43	+struct liodn_id_table liodn_tbl[] = {
	44	+#ifdef CONFIG_SYS_DPAA_QBMAN
	45	+ SET_QMAN_LIODN(62),
	46	+ SET_BMAN_LIODN(63),
	47	+#endif
	48	+
	49	+ SET_SDHC_LIODN(1, 552),
	50	+
	51	+ SET_PME_LIODN(117),
	52	+
	53	+ SET_USB_LIODN(1, "fsl-usb2-mph", 553),
	54	+ SET_USB_LIODN(2, "fsl-usb2-dr", 554),
	55	+
	56	+ SET_SATA_LIODN(1, 555),
	57	+ SET_SATA_LIODN(2, 556),
	58	+
	59	+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
	60	+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
	61	+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
	62	+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
	63	+
	64	+ SET_DMA_LIODN(1, 147),
	65	+ SET_DMA_LIODN(2, 227),
	66	+ SET_DMA_LIODN(3, 226),
	67	+
	68	+ SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
	69	+ SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
	70	+ SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
	71	+ SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
	72	+
	73	+#ifdef CONFIG_SYS_PMAN
	74	+ SET_PMAN_LIODN(1, 513),
	75	+ SET_PMAN_LIODN(2, 514),
	76	+ SET_PMAN_LIODN(3, 515),
	77	+#endif
	78	+
	79	+ /* SET_NEXUS_LIODN(557), -- not yet implemented */
	80	+};
	81	+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
	82	+
	83	+#ifdef CONFIG_SYS_DPAA_FMAN
	84	+struct liodn_id_table fman1_liodn_tbl[] = {
	85	+ SET_FMAN_RX_1G_LIODN(1, 0, 88),
	86	+ SET_FMAN_RX_1G_LIODN(1, 1, 89),
	87	+ SET_FMAN_RX_1G_LIODN(1, 2, 90),
	88	+ SET_FMAN_RX_1G_LIODN(1, 3, 91),
	89	+ SET_FMAN_RX_1G_LIODN(1, 4, 92),
	90	+ SET_FMAN_RX_1G_LIODN(1, 5, 93),
	91	+ SET_FMAN_RX_10G_LIODN(1, 0, 94),
	92	+ SET_FMAN_RX_10G_LIODN(1, 1, 95),
	93	+};
	94	+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
	95	+#endif
	96	+
	97	+struct liodn_id_table sec_liodn_tbl[] = {
	98	+ SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
	99	+ SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
	100	+ SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
	101	+ SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
	102	+ SET_SEC_RTIC_LIODN_ENTRY(a, 453),
	103	+ SET_SEC_RTIC_LIODN_ENTRY(b, 549),
	104	+ SET_SEC_RTIC_LIODN_ENTRY(c, 550),
	105	+ SET_SEC_RTIC_LIODN_ENTRY(d, 551),
	106	+ SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
	107	+ SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
	108	+ SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
	109	+ SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
	110	+ SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
	111	+ SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
	112	+ SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
	113	+ SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
	114	+};
	115	+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
	116	+
	117	+#ifdef CONFIG_SYS_DPAA_RMAN
	118	+struct liodn_id_table rman_liodn_tbl[] = {
	119	+ /* Set RMan block 0-3 liodn offset */
	120	+ SET_RMAN_LIODN(0, 6),
	121	+ SET_RMAN_LIODN(1, 7),
	122	+ SET_RMAN_LIODN(2, 8),
	123	+ SET_RMAN_LIODN(3, 9),
	124	+};
	125	+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
	126	+#endif
	127	+
	128	+struct liodn_id_table liodn_bases[] = {
	129	+#ifdef CONFIG_SYS_DPAA_DCE
	130	+ [FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694),
	131	+#endif
	132	+ [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
	133	+#ifdef CONFIG_SYS_DPAA_FMAN
	134	+ [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
	135	+#endif
	136	+#ifdef CONFIG_SYS_DPAA_PME
	137	+ [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846),
	138	+#endif
	139	+#ifdef CONFIG_SYS_DPAA_RMAN
	140	+ [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
	141	+#endif
	142	+};
	1	+/*
	2	+ * Copyright 2013 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#include <common.h>
	10	+#include <asm/fsl_serdes.h>
	11	+#include <asm/processor.h>
	12	+#include "fsl_corenet2_serdes.h"
	13	+
	14	+struct serdes_config {
	15	+ u32 protocol;
	16	+ u8 lanes[SRDS_MAX_LANES];
	17	+};
	18	+
	19	+static const struct serdes_config serdes1_cfg_tbl[] = {
	20	+ /* SerDes 1 */
	21	+ {0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10,
	22	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
	23	+ PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	24	+ {0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1,
	25	+ SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} },
	26	+ {0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
	27	+ SGMII_FM1_DTSEC2, PCIE4, PCIE4,
	28	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	29	+ {0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
	30	+ SGMII_FM1_DTSEC2, PCIE4, PCIE4,
	31	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	32	+ {0xDE, {PCIE3, PCIE3, PCIE3, PCIE3,
	33	+ PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
	34	+ {0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4,
	35	+ PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	36	+ {0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
	37	+ SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
	38	+ {0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
	39	+ SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
	40	+ {0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
	41	+ SGMII_FM1_DTSEC2, PCIE4, PCIE1,
	42	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	43	+ {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
	44	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
	45	+ PCIE4, PCIE4, PCIE4, PCIE4} },
	46	+#if defined(CONFIG_PPC_T2080)
	47	+ {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
	48	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
	49	+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
	50	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	51	+ {0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
	52	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
	53	+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
	54	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	55	+ {0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
	56	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
	57	+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
	58	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	59	+ {0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
	60	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
	61	+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
	62	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	63	+ {0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
	64	+ XAUI_FM1_MAC9, XAUI_FM1_MAC9,
	65	+ PCIE4, SGMII_FM1_DTSEC4,
	66	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	67	+ {0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
	68	+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
	69	+ PCIE4, SGMII_FM1_DTSEC4,
	70	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	71	+ {0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
	72	+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
	73	+ PCIE4, SGMII_FM1_DTSEC4,
	74	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	75	+ {0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
	76	+ XFI_FM1_MAC1, XFI_FM1_MAC2,
	77	+ PCIE4, SGMII_FM1_DTSEC4,
	78	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	79	+ {0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10,
	80	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
	81	+ PCIE4, PCIE4, PCIE4, PCIE4} },
	82	+ {0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10,
	83	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
	84	+ SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	85	+ {0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
	86	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
	87	+ PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	88	+ {0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
	89	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
	90	+ PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	91	+ {0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
	92	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
	93	+ PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	94	+ {0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
	95	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
	96	+ PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	97	+ {0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
	98	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
	99	+ PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	100	+ {0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
	101	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
	102	+ PCIE4, PCIE4, PCIE4, PCIE4} },
	103	+ {0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
	104	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
	105	+ PCIE4, PCIE4, PCIE4, PCIE4} },
	106	+ {0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
	107	+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
	108	+ PCIE4, PCIE4, PCIE4, PCIE4} },
	109	+ {0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10,
	110	+ XFI_FM1_MAC1, XFI_FM1_MAC2,
	111	+ PCIE4, PCIE4, PCIE4, PCIE4} },
	112	+ {0xAB, {PCIE3, PCIE3, PCIE3, PCIE3,
	113	+ PCIE4, PCIE4, PCIE4, PCIE4} },
	114	+ {0xDA, {PCIE3, PCIE3, PCIE3, PCIE3,
	115	+ PCIE3, PCIE3, PCIE3, PCIE3} },
	116	+ {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
	117	+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
	118	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	119	+ {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
	120	+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
	121	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	122	+ {0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
	123	+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
	124	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	125	+ {0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
	126	+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
	127	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	128	+ {0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
	129	+ XFI_FM1_MAC1, XFI_FM1_MAC2,
	130	+ PCIE4, PCIE4, PCIE4, PCIE4} },
	131	+
	132	+#elif defined(CONFIG_PPC_T2081)
	133	+ {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
	134	+ PCIE4, PCIE4, PCIE4, PCIE4} },
	135	+ {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
	136	+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
	137	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	138	+ {0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
	139	+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
	140	+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
	141	+#endif
	142	+ {}
	143	+};
	144	+
	145	+#ifndef CONFIG_PPC_T2081
	146	+static const struct serdes_config serdes2_cfg_tbl[] = {
	147	+ /* SerDes 2 */
	148	+ {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
	149	+ {0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
	150	+ {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
	151	+ {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
	152	+ {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
	153	+ {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
	154	+ {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
	155	+ {0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
	156	+ {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
	157	+ {}
	158	+};
	159	+#endif
	160	+
	161	+static const struct serdes_config *serdes_cfg_tbl[] = {
	162	+ serdes1_cfg_tbl,
	163	+#ifndef CONFIG_PPC_T2081
	164	+ serdes2_cfg_tbl,
	165	+#endif
	166	+};
	167	+
	168	+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
	169	+{
	170	+ const struct serdes_config *ptr;
	171	+
	172	+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
	173	+ return 0;
	174	+
	175	+ ptr = serdes_cfg_tbl[serdes];
	176	+ while (ptr->protocol) {
	177	+ if (ptr->protocol == cfg)
	178	+ return ptr->lanes[lane];
	179	+ ptr++;
	180	+ }
	181	+ return 0;
	182	+}
	183	+
	184	+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
	185	+{
	186	+ int i;
	187	+ const struct serdes_config *ptr;
	188	+
	189	+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
	190	+ return 0;
	191	+
	192	+ ptr = serdes_cfg_tbl[serdes];
	193	+ while (ptr->protocol) {
	194	+ if (ptr->protocol == prtcl)
	195	+ break;
	196	+ ptr++;
	197	+ }
	198	+
	199	+ if (!ptr->protocol)
	200	+ return 0;
	201	+
	202	+ for (i = 0; i < SRDS_MAX_LANES; i++) {
	203	+ if (ptr->lanes[i] != NONE)
	204	+ return 1;
	205	+ }
	206	+
	207	+ return 0;
	208	+}
...	...	@@ -75,6 +75,8 @@
75	75	CPU_TYPE_ENTRY(T1020, T1020, 0),
76	76	CPU_TYPE_ENTRY(T1021, T1021, 0),
77	77	CPU_TYPE_ENTRY(T1022, T1022, 0),
	78	+ CPU_TYPE_ENTRY(T2080, T2080, 0),
	79	+ CPU_TYPE_ENTRY(T2081, T2081, 0),
78	80	CPU_TYPE_ENTRY(BSC9130, 9130, 1),
79	81	CPU_TYPE_ENTRY(BSC9131, 9131, 1),
80	82	CPU_TYPE_ENTRY(BSC9132, 9132, 2),
...	...	@@ -718,6 +718,50 @@
718	718	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
719	719	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
720	720
	721	+#elif defined(CONFIG_PPC_T2080) \|\| defined(CONFIG_PPC_T2081)
	722	+#define CONFIG_E6500
	723	+#define CONFIG_SYS_PPC64 /* 64-bit core */
	724	+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
	725	+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
	726	+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
	727	+#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
	728	+#define CONFIG_SYS_FSL_QMAN_V3
	729	+#define CONFIG_MAX_CPUS 4
	730	+#define CONFIG_SYS_FSL_NUM_LAWS 32
	731	+#define CONFIG_SYS_FSL_SEC_COMPAT 4
	732	+#define CONFIG_SYS_NUM_FMAN 1
	733	+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
	734	+#define CONFIG_SYS_FSL_SRDS_1
	735	+#define CONFIG_SYS_FSL_PCI_VER_3_X
	736	+#if defined(CONFIG_PPC_T2080)
	737	+#define CONFIG_SYS_NUM_FM1_DTSEC 8
	738	+#define CONFIG_SYS_NUM_FM1_10GEC 4
	739	+#define CONFIG_SYS_FSL_SRDS_2
	740	+#define CONFIG_SYS_FSL_SRIO_LIODN
	741	+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
	742	+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
	743	+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
	744	+#elif defined(CONFIG_PPC_T2081)
	745	+#define CONFIG_SYS_NUM_FM1_DTSEC 6
	746	+#define CONFIG_SYS_NUM_FM1_10GEC 2
	747	+#endif
	748	+#define CONFIG_SYS_FSL_NUM_USB_CTRLS 2
	749	+#define CONFIG_NUM_DDR_CONTROLLERS 1
	750	+#define CONFIG_PME_PLAT_CLK_DIV 1
	751	+#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
	752	+#define CONFIG_SYS_FM1_CLK 0
	753	+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
	754	+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
	755	+#define CONFIG_SYS_FMAN_V3
	756	+#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
	757	+#define CONFIG_SYS_FSL_TBCLK_DIV 16
	758	+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
	759	+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
	760	+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
	761	+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
	762	+#define CONFIG_SYS_FSL_SFP_VER_3_0
	763	+#define CONFIG_SYS_FSL_ISBC_VER 2
	764	+
721	765	#elif defined(CONFIG_PPC_C29X)
722	766	#define CONFIG_MAX_CPUS 1
723	767	#define CONFIG_FSL_SDHC_V2_3
...	...	@@ -1759,6 +1759,12 @@
1759	1759	#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1760	1760	#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1761	1761	#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
	1762	+#elif defined(CONFIG_PPC_T2080) \|\| defined(CONFIG_PPC_T2081)
	1763	+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
	1764	+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
	1765	+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
	1766	+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
	1767	+#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1762	1768	#endif
1763	1769	#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
1764	1770	#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
...	...	@@ -1822,6 +1828,15 @@
1822	1828	#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
1823	1829	#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1824	1830	#endif
	1831	+#if defined(CONFIG_PPC_T2080) \|\| defined(CONFIG_PPC_T2081)
	1832	+#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
	1833	+#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
	1834	+#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
	1835	+#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
	1836	+#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
	1837	+#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
	1838	+#define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
	1839	+#endif
1825	1840	u8 res18[192];
1826	1841	u32 scratchrw[4]; /* Scratch Read/Write */
1827	1842	u8 res19[240];
...	...	@@ -2818,6 +2833,7 @@
2818	2833	#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
2819	2834	#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2820	2835	#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
	2836	+#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
2821	2837	#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
2822	2838	#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2823	2839	#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
...	...	@@ -1127,6 +1127,8 @@
1127	1127	#define SVR_T1020 0x852100
1128	1128	#define SVR_T1021 0x852101
1129	1129	#define SVR_T1022 0x852102
	1130	+#define SVR_T2080 0x853000
	1131	+#define SVR_T2081 0x853100
1130	1132
1131	1133	#define SVR_8610 0x80A000
1132	1134	#define SVR_8641 0x809000
...	...	@@ -28,6 +28,8 @@
28	28	obj-$(CONFIG_PPC_T1042) += t1040.o
29	29	obj-$(CONFIG_PPC_T1020) += t1040.o
30	30	obj-$(CONFIG_PPC_T1022) += t1040.o
	31	+obj-$(CONFIG_PPC_T2080) += t2080.o
	32	+obj-$(CONFIG_PPC_T2081) += t2080.o
31	33	obj-$(CONFIG_PPC_T4240) += t4240.o
32	34	obj-$(CONFIG_PPC_T4160) += t4240.o
33	35	obj-$(CONFIG_PPC_B4420) += b4860.o
	1	+/*
	2	+ * Copyright 2012 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#include <common.h>
	10	+#include <phy.h>
	11	+#include <fm_eth.h>
	12	+#include <asm/immap_85xx.h>
	13	+#include <asm/fsl_serdes.h>
	14	+
	15	+u32 port_to_devdisr[] = {
	16	+ [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
	17	+ [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
	18	+ [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
	19	+ [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
	20	+ [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
	21	+ [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
	22	+ [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
	23	+ [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
	24	+ [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
	25	+ [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
	26	+ [FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3,
	27	+ [FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4,
	28	+};
	29	+
	30	+static int is_device_disabled(enum fm_port port)
	31	+{
	32	+ ccsr_gur_t gur = (void __iomem )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	33	+ u32 devdisr2 = in_be32(&gur->devdisr2);
	34	+
	35	+ return port_to_devdisr[port] & devdisr2;
	36	+}
	37	+
	38	+void fman_disable_port(enum fm_port port)
	39	+{
	40	+ ccsr_gur_t gur = (void __iomem )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	41	+
	42	+ setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
	43	+}
	44	+
	45	+phy_interface_t fman_port_enet_if(enum fm_port port)
	46	+{
	47	+ ccsr_gur_t gur = (void __iomem )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	48	+ u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
	49	+
	50	+ if (is_device_disabled(port))
	51	+ return PHY_INTERFACE_MODE_NONE;
	52	+
	53	+ if ((port == FM1_10GEC1 \|\| port == FM1_10GEC2 \|\|
	54	+ port == FM1_10GEC3 \|\| port == FM1_10GEC4) &&
	55	+ ((is_serdes_configured(XAUI_FM1_MAC9)) \|\|
	56	+ (is_serdes_configured(XFI_FM1_MAC1)) \|\|
	57	+ (is_serdes_configured(XFI_FM1_MAC2)) \|\|
	58	+ (is_serdes_configured(XFI_FM1_MAC9)) \|\|
	59	+ (is_serdes_configured(XFI_FM1_MAC10))))
	60	+ return PHY_INTERFACE_MODE_XGMII;
	61	+
	62	+ if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
	63	+ FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII))
	64	+ return PHY_INTERFACE_MODE_RGMII;
	65	+
	66	+ if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
	67	+ FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII))
	68	+ return PHY_INTERFACE_MODE_RGMII;
	69	+
	70	+ if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
	71	+ FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII))
	72	+ return PHY_INTERFACE_MODE_RGMII;
	73	+
	74	+ switch (port) {
	75	+ case FM1_DTSEC1:
	76	+ case FM1_DTSEC2:
	77	+ case FM1_DTSEC3:
	78	+ case FM1_DTSEC4:
	79	+ case FM1_DTSEC5:
	80	+ case FM1_DTSEC6:
	81	+ case FM1_DTSEC9:
	82	+ case FM1_DTSEC10:
	83	+ if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
	84	+ return PHY_INTERFACE_MODE_SGMII;
	85	+ break;
	86	+ default:
	87	+ return PHY_INTERFACE_MODE_NONE;
	88	+ }
	89	+
	90	+ return PHY_INTERFACE_MODE_NONE;
	91	+}