Eric Lee / smarc-uboot | Embedian Git Server

Commit 62af7615eb8e05bb29ecc44210f24317a51fcd94

Authored by Shengzhou Liu 2013-10-11 23:02:38 +0800

Committed by York Sun 2013-11-14 03:12:48 +0800

Exists in master and in 50 other branches

powerpc/p1010rdb: update readme for p1010rdb-pa and p1010rdb-pb

- Remove duplicate doc/README.p1010rdb
- Rename README to README.P1010RDB-PA
- Add new README.P1010RDB-PB

P1010RDB-PB is a variation of previous P1010RDB-PA board.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>

Showing 4 changed files with 396 additions and 406 deletions Side-by-side Diff

board/freescale/p1010rdb/README
board/freescale/p1010rdb/README.P1010RDB-PA
board/freescale/p1010rdb/README.P1010RDB-PB
doc/README.p1010rdb

board/freescale/p1010rdb/README

View file @ 62af761

1		-Overview
2		-=========
3		-The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
4		-
5		-The P1010 is a cost-effective, low-power, highly integrated host processor
6		-based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
7		-that addresses the requirements of several routing, gateways, storage, consumer,
8		-and industrial applications. Applications of interest include the main CPUs and
9		-I/O processors in network attached storage (NAS), the voice over IP (VoIP)
10		-router/gateway, and wireless LAN (WLAN) and industrial controllers.
11		-
12		-The P1010RDB board features are as follows:
13		-Memory subsystem:
14		- - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
15		- - 32 Mbyte NOR flash single-chip memory
16		- - 32 Mbyte NAND flash memory
17		- - 256 Kbit M24256 I2C EEPROM
18		- - 16 Mbyte SPI memory
19		- - I2C Board EEPROM 128x8 bit memory
20		- - SD/MMC connector to interface with the SD memory card
21		-Interfaces:
22		- - PCIe:
23		- - Lane0: x1 mini-PCIe slot
24		- - Lane1: x1 PCIe standard slot
25		- - SATA:
26		- - 1 internal SATA connector to 2.5” 160G SATA2 HDD
27		- - 1 eSATA connector to rear panel
28		- - 10/100/1000 BaseT Ethernet ports:
29		- - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
30		- - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
31		- - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
32		- - USB 2.0 port:
33		- - x1 USB2.0 port via an external ULPI PHY to micro-AB connector
34		- - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector
35		- - FlexCAN ports:
36		- - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
37		- interface;
38		- - DUART interface:
39		- - DUART interface: supports two UARTs up to 115200 bps for
40		- console display
41		- - RJ45 connectors are used for these 2 UART ports.
42		- - TDM
43		- - 2 FXS ports connected via an external SLIC to the TDM interface.
44		- SLIC is controllled via SPI.
45		- - 1 FXO port connected via a relay to FXS for switchover to POTS
46		-Board connectors:
47		- - Mini-ITX power supply connector
48		- - JTAG/COP for debugging
49		-IEEE Std. 1588 signals for test and measurement
50		-Real-time clock on I2C bus
51		-POR
52		- - support critical POR setting changed via switch on board
53		-PCB
54		- - 6-layer routing (4-layer signals, 2-layer power and ground)
55		-
56		-
57		-Physical Memory Map on P1010RDB
58		-===============================
59		-Address Start Address End Memory type Attributes
60		-0x0000_0000 0x3fff_ffff DDR 1G Cacheable
61		-0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
62		-0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
63		-0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
64		-0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
65		-0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
66		-0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
67		-0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
68		-
69		-
70		-Serial Port Configuration on P1010RDB
71		-=====================================
72		-Configure the serial port of the attached computer with the following values:
73		- -Data rate: 115200 bps
74		- -Number of data bits: 8
75		- -Parity: None
76		- -Number of Stop bits: 1
77		- -Flow Control: Hardware/None
78		-
79		-
80		-Settings of DIP-switch
81		-======================
82		- SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
83		- SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
84		- SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
85		-Note: 1 stands for 'on', 0 stands for 'off'
86		-
87		-
88		-Setting of hwconfig
89		-===================
90		-If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
91		-"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
92		-setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
93		-By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
94		-is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
95		-instead of to CAN/UART1.
96		-
97		-
98		-Build and burn u-boot to NOR flash
99		-==================================
100		-1. Build u-boot.bin image
101		- export ARCH=powerpc
102		- export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
103		- make P1010RDB_NOR
104		-
105		-2. Burn u-boot.bin into NOR flash
106		- => tftp $loadaddr $uboot
107		- => protect off eff80000 +$filesize
108		- => erase eff80000 +$filesize
109		- => cp.b $loadaddr eff80000 $filesize
110		-
111		-3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
112		-
113		-
114		-Alternate NOR bank
115		-==================
116		-1. Burn u-boot.bin into alternate NOR bank
117		- => tftp $loadaddr $uboot
118		- => protect off eef80000 +$filesize
119		- => erase eef80000 +$filesize
120		- => cp.b $loadaddr eef80000 $filesize
121		-
122		-2. Switch to alternate NOR bank
123		- => mw.b ffb00009 1
124		- => reset
125		- or set SW1[8]= ON
126		-
127		-SW1[8]= OFF: Upper bank used for booting start
128		-SW1[8]= ON: Lower bank used for booting start
129		-CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
130		-0 - boot from upper 4 sectors
131		-1 - boot from lower 4 sectors
132		-
133		-
134		-Build and burn u-boot to NAND flash
135		-===================================
136		-1. Build u-boot.bin image
137		- export ARCH=powerpc
138		- export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
139		- make P1010RDB_NAND
140		-
141		-2. Burn u-boot-nand.bin into NAND flash
142		- => tftp $loadaddr $uboot-nand
143		- => nand erase 0 $filesize
144		- => nand write $loadaddr 0 $filesize
145		-
146		-3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
147		-
148		-
149		-Build and burn u-boot to SPI flash
150		-==================================
151		-1. Build u-boot-spi.bin image
152		- make P1010RDB_SPIFLASH_config; make
153		- Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
154		- Download u-boot.bin to linux and you can find some config files
155		- under /usr/share such as config_xx.dat. Do below command:
156		- boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
157		- u-boot-spi.bin
158		- to generate u-boot-spi.bin.
159		-
160		-2. Burn u-boot-spi.bin into SPI flash
161		- => tftp $loadaddr $uboot-spi
162		- => sf erase 0 100000
163		- => sf write $loadaddr 0 $filesize
164		-
165		-3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
166		-
167		-
168		-CPLD POR setting registers
169		-==========================
170		-1. Set POR switch selection register (addr 0xFFB00011) to 0.
171		-2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
172		- proper values.
173		- If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
174		- switch command by I2C.
175		-3. Send reset command.
176		- After reset, the new POR setting will be implemented.
177		-
178		-Two examples are given in below:
179		-Switch from NOR to NAND boot with default frequency:
180		- => i2c dev 0
181		- => i2c mw 18 1 f9
182		- => i2c mw 18 3 f0
183		- => mw.b ffb00011 0
184		- => mw.b ffb00017 1
185		- => reset
186		-Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
187		- => i2c dev 0
188		- => i2c mw 18 1 f1
189		- => i2c mw 18 3 f0
190		- => mw.b ffb00011 0
191		- => mw.b ffb00014 2
192		- => mw.b ffb00015 5
193		- => mw.b ffb00016 3
194		- => mw.b ffb00017 f
195		- => reset
196		-
197		-
198		-Boot Linux from network using TFTP on P1010RDB
199		-==============================================
200		-Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
201		- => tftp 1000000 uImage
202		- => tftp 2000000 p1010rdb.dtb
203		- => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
204		- => bootm 1000000 3000000 2000000
205		-
206		-
207		-Please contact your local field applications engineer or sales representative
208		-to obtain related documents, such as P1010-RDB User Guide for details.

board/freescale/p1010rdb/README.P1010RDB-PA

Diff comments View file @ 62af761

	1	+Overview
	2	+=========
	3	+The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
	4	+
	5	+The P1010 is a cost-effective, low-power, highly integrated host processor
	6	+based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
	7	+that addresses the requirements of several routing, gateways, storage, consumer,
	8	+and industrial applications. Applications of interest include the main CPUs and
	9	+I/O processors in network attached storage (NAS), the voice over IP (VoIP)
	10	+router/gateway, and wireless LAN (WLAN) and industrial controllers.
	11	+
	12	+The P1010RDB board features are as follows:
	13	+Memory subsystem:
	14	+ - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
	15	+ - 32 Mbyte NOR flash single-chip memory
	16	+ - 32 Mbyte NAND flash memory
	17	+ - 256 Kbit M24256 I2C EEPROM
	18	+ - 16 Mbyte SPI memory
	19	+ - I2C Board EEPROM 128x8 bit memory
	20	+ - SD/MMC connector to interface with the SD memory card
	21	+Interfaces:
	22	+ - PCIe:
	23	+ - Lane0: x1 mini-PCIe slot
	24	+ - Lane1: x1 PCIe standard slot
	25	+ - SATA:
	26	+ - 1 internal SATA connector to 2.5” 160G SATA2 HDD
	27	+ - 1 eSATA connector to rear panel
	28	+ - 10/100/1000 BaseT Ethernet ports:
	29	+ - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
	30	+ - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
	31	+ - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
	32	+ - USB 2.0 port:
	33	+ - x1 USB2.0 port via an external ULPI PHY to micro-AB connector
	34	+ - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector
	35	+ - FlexCAN ports:
	36	+ - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
	37	+ interface;
	38	+ - DUART interface:
	39	+ - DUART interface: supports two UARTs up to 115200 bps for
	40	+ console display
	41	+ - RJ45 connectors are used for these 2 UART ports.
	42	+ - TDM
	43	+ - 2 FXS ports connected via an external SLIC to the TDM interface.
	44	+ SLIC is controllled via SPI.
	45	+ - 1 FXO port connected via a relay to FXS for switchover to POTS
	46	+Board connectors:
	47	+ - Mini-ITX power supply connector
	48	+ - JTAG/COP for debugging
	49	+IEEE Std. 1588 signals for test and measurement
	50	+Real-time clock on I2C bus
	51	+POR
	52	+ - support critical POR setting changed via switch on board
	53	+PCB
	54	+ - 6-layer routing (4-layer signals, 2-layer power and ground)
	55	+
	56	+
	57	+Physical Memory Map on P1010RDB
	58	+===============================
	59	+Address Start Address End Memory type Attributes
	60	+0x0000_0000 0x3fff_ffff DDR 1G Cacheable
	61	+0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
	62	+0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
	63	+0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
	64	+0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
	65	+0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
	66	+0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
	67	+0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
	68	+
	69	+
	70	+Serial Port Configuration on P1010RDB
	71	+=====================================
	72	+Configure the serial port of the attached computer with the following values:
	73	+ -Data rate: 115200 bps
	74	+ -Number of data bits: 8
	75	+ -Parity: None
	76	+ -Number of Stop bits: 1
	77	+ -Flow Control: Hardware/None
	78	+
	79	+
	80	+Settings of DIP-switch
	81	+======================
	82	+ SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
	83	+ SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
	84	+ SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
	85	+Note: 1 stands for 'on', 0 stands for 'off'
	86	+
	87	+
	88	+Setting of hwconfig
	89	+===================
	90	+If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
	91	+"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
	92	+setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
	93	+By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
	94	+is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
	95	+instead of to CAN/UART1.
	96	+
	97	+
	98	+Build and burn u-boot to NOR flash
	99	+==================================
	100	+1. Build u-boot.bin image
	101	+ export ARCH=powerpc
	102	+ export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
	103	+ make P1010RDB_NOR
	104	+
	105	+2. Burn u-boot.bin into NOR flash
	106	+ => tftp $loadaddr $uboot
	107	+ => protect off eff80000 +$filesize
	108	+ => erase eff80000 +$filesize
	109	+ => cp.b $loadaddr eff80000 $filesize
	110	+
	111	+3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
	112	+
	113	+
	114	+Alternate NOR bank
	115	+==================
	116	+1. Burn u-boot.bin into alternate NOR bank
	117	+ => tftp $loadaddr $uboot
	118	+ => protect off eef80000 +$filesize
	119	+ => erase eef80000 +$filesize
	120	+ => cp.b $loadaddr eef80000 $filesize
	121	+
	122	+2. Switch to alternate NOR bank
	123	+ => mw.b ffb00009 1
	124	+ => reset
	125	+ or set SW1[8]= ON
	126	+
	127	+SW1[8]= OFF: Upper bank used for booting start
	128	+SW1[8]= ON: Lower bank used for booting start
	129	+CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
	130	+0 - boot from upper 4 sectors
	131	+1 - boot from lower 4 sectors
	132	+
	133	+
	134	+Build and burn u-boot to NAND flash
	135	+===================================
	136	+1. Build u-boot.bin image
	137	+ export ARCH=powerpc
	138	+ export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
	139	+ make P1010RDB_NAND
	140	+
	141	+2. Burn u-boot-nand.bin into NAND flash
	142	+ => tftp $loadaddr $uboot-nand
	143	+ => nand erase 0 $filesize
	144	+ => nand write $loadaddr 0 $filesize
	145	+
	146	+3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
	147	+
	148	+
	149	+Build and burn u-boot to SPI flash
	150	+==================================
	151	+1. Build u-boot-spi.bin image
	152	+ make P1010RDB_SPIFLASH_config; make
	153	+ Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
	154	+ Download u-boot.bin to linux and you can find some config files
	155	+ under /usr/share such as config_xx.dat. Do below command:
	156	+ boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
	157	+ u-boot-spi.bin
	158	+ to generate u-boot-spi.bin.
	159	+
	160	+2. Burn u-boot-spi.bin into SPI flash
	161	+ => tftp $loadaddr $uboot-spi
	162	+ => sf erase 0 100000
	163	+ => sf write $loadaddr 0 $filesize
	164	+
	165	+3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
	166	+
	167	+
	168	+CPLD POR setting registers
	169	+==========================
	170	+1. Set POR switch selection register (addr 0xFFB00011) to 0.
	171	+2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
	172	+ proper values.
	173	+ If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
	174	+ switch command by I2C.
	175	+3. Send reset command.
	176	+ After reset, the new POR setting will be implemented.
	177	+
	178	+Two examples are given in below:
	179	+Switch from NOR to NAND boot with default frequency:
	180	+ => i2c dev 0
	181	+ => i2c mw 18 1 f9
	182	+ => i2c mw 18 3 f0
	183	+ => mw.b ffb00011 0
	184	+ => mw.b ffb00017 1
	185	+ => reset
	186	+Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
	187	+ => i2c dev 0
	188	+ => i2c mw 18 1 f1
	189	+ => i2c mw 18 3 f0
	190	+ => mw.b ffb00011 0
	191	+ => mw.b ffb00014 2
	192	+ => mw.b ffb00015 5
	193	+ => mw.b ffb00016 3
	194	+ => mw.b ffb00017 f
	195	+ => reset
	196	+
	197	+
	198	+Boot Linux from network using TFTP on P1010RDB
	199	+==============================================
	200	+Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
	201	+ => tftp 1000000 uImage
	202	+ => tftp 2000000 p1010rdb.dtb
	203	+ => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
	204	+ => bootm 1000000 3000000 2000000
	205	+
	206	+
	207	+For more details, please refer to P1010RDB User Guide and access website
	208	+www.freescale.com

board/freescale/p1010rdb/README.P1010RDB-PB

Diff comments View file @ 62af761

	1	+Overview
	2	+=========
	3	+The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
	4	+P1010RDB-PB is a variation of previous P1010RDB-PA board.
	5	+
	6	+The P1010 is a cost-effective, low-power, highly integrated host processor
	7	+based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that
	8	+addresses the requirements of several routing, gateways, storage, consumer,
	9	+and industrial applications. Applications of interest include the main CPUs and
	10	+I/O processors in network attached storage (NAS), the voice over IP (VoIP)
	11	+router/gateway, and wireless LAN (WLAN) and industrial controllers.
	12	+
	13	+The P1010RDB-PB board features are as following:
	14	+Memory subsystem:
	15	+ - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
	16	+ - 32M bytes NOR flash single-chip memory
	17	+ - 2G bytes NAND flash memory
	18	+ - 16M bytes SPI memory
	19	+ - 256K bit M24256 I2C EEPROM
	20	+ - I2C Board EEPROM 128x8 bit memory
	21	+ - SD/MMC connector to interface with the SD memory card
	22	+Interfaces:
	23	+ - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII)
	24	+ - PCIe 2.0: two x1 mini-PCIe slots
	25	+ - SATA 2.0: two SATA interfaces
	26	+ - USB 2.0: one USB interface
	27	+ - FlexCAN: two FlexCAN interfaces (revision 2.0B)
	28	+ - UART: one USB-to-Serial interface
	29	+ - TDM: 2 FXS ports connected via an external SLIC to the TDM interface.
	30	+ 1 FXO port connected via a relay to FXS for switchover to POTS
	31	+
	32	+Board connectors:
	33	+ - Mini-ITX power supply connector
	34	+ - JTAG/COP for debugging
	35	+
	36	+POR: support critical POR setting changed via switch on board
	37	+PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
	38	+
	39	+Physical Memory Map on P1010RDB
	40	+===============================
	41	+Address Start Address End Memory type Attributes
	42	+0x0000_0000 0x3fff_ffff DDR 1G Cacheable
	43	+0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
	44	+0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
	45	+0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
	46	+0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
	47	+0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
	48	+0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
	49	+0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
	50	+
	51	+
	52	+Serial Port Configuration on P1010RDB
	53	+=====================================
	54	+Configure the serial port of the attached computer with the following values:
	55	+ -Data rate: 115200 bps
	56	+ -Number of data bits: 8
	57	+ -Parity: None
	58	+ -Number of Stop bits: 1
	59	+ -Flow Control: Hardware/None
	60	+
	61	+
	62	+P1010RDB-PB default DIP-switch settings
	63	+=======================================
	64	+SW1[1:8]= 10101010
	65	+SW2[1:8]= 11011000
	66	+SW3[1:8]= 10010000
	67	+SW4[1:4]= 1010
	68	+SW5[1:8]= 11111010
	69	+
	70	+
	71	+P1010RDB-PB boot mode settings via DIP-switch
	72	+=============================================
	73	+SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
	74	+SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
	75	+SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
	76	+SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
	77	+Note: 1 stands for 'on', 0 stands for 'off'
	78	+
	79	+
	80	+Switch P1010RDB-PB boot mode via software without setting DIP-switch
	81	+====================================================================
	82	+=> run boot_bank0 (boot from NOR bank0)
	83	+=> run boot_bank1 (boot from NOR bank1)
	84	+=> run boot_nand (boot from NAND flash)
	85	+=> run boot_spi (boot from SPI flash)
	86	+=> run boot_sd (boot from SD card)
	87	+
	88	+
	89	+Frequency combination support on P1010RDB-PB
	90	+=============================================
	91	+SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s)
	92	+0101 1 1010 0 800 400 800
	93	+1001 1 1010 0 800 400 667
	94	+1010 1 1100 0 667 333 667
	95	+1000 0 1010 0 533 266 667
	96	+0101 1 1010 1 1000 400 800
	97	+1001 1 1010 1 1000 400 667
	98	+
	99	+
	100	+Setting of pin mux
	101	+==================
	102	+Since pins multiplexing, TDM and CAN are muxed with SPI flash.
	103	+SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
	104	+
	105	+To enable TDM:
	106	+=> setenv hwconfig fsl_p1010mux:tdm_can=tdm
	107	+=> save;reset
	108	+
	109	+To enable FlexCAN:
	110	+=> setenv hwconfig fsl_p1010mux:tdm_can=can
	111	+=> save;reset
	112	+
	113	+To enable SDHC in case of NOR/NAND/SPI boot
	114	+ a) For temporary use case in runtime without reboot system
	115	+ run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC.
	116	+
	117	+ b) For long-term use case
	118	+ set 'esdhc' in hwconfig and save it.
	119	+
	120	+To enable IFC in case of SD boot
	121	+ a) For temporary use case in runtime without reboot system
	122	+ run 'mux ifc' in u-boot to validate IFC with invalidating SDHC.
	123	+
	124	+ b) For long-term use case
	125	+ set 'ifc' in hwconfig and save it.
	126	+
	127	+
	128	+Build images for different boot mode
	129	+====================================
	130	+First setup cross compile environment on build host
	131	+ $ export ARCH=powerpc
	132	+ $ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu-
	133	+
	134	+1. For NOR boot
	135	+ $ make P1010RDB-PB_NOR
	136	+
	137	+2. For NAND boot
	138	+ $ make P1010RDB-PB_NAND
	139	+
	140	+3. For SPI boot
	141	+ $ make P1010RDB-PB_SPIFLASH
	142	+
	143	+4. For SD boot
	144	+ $ make P1010RDB-PB_SDCARD
	145	+
	146	+
	147	+Steps to program images to flash for different boot mode
	148	+========================================================
	149	+1. NOR boot
	150	+ => tftp 1000000 u-boot.bin
	151	+ For bank0
	152	+ => pro off all;era eff80000 efffffff;cp.b 1000000 eff80000 $filesize
	153	+ set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
	154	+
	155	+ For bank1
	156	+ => pro off all;era eef80000 eeffffff;cp.b 1000000 eef80000 $filesize
	157	+ set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
	158	+
	159	+2. NAND boot
	160	+ => tftp 1000000 u-boot-nand.bin
	161	+ => nand erase 0 $filesize; nand write $loadaddr 0 $filesize
	162	+ Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
	163	+
	164	+3. SPI boot
	165	+ 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin
	166	+ 2) => tftp 1000000 u-boot-spi-combined.bin
	167	+ 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000
	168	+ set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
	169	+
	170	+4. SD boot
	171	+ 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin
	172	+ 2) => tftp 1000000 u-boot-sd-combined.bin
	173	+ 3) => mux sdhc
	174	+ 4) => mmc write 1000000 0 1050
	175	+ set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
	176	+
	177	+
	178	+Boot Linux from network using TFTP on P1010RDB-PB
	179	+=================================================
	180	+Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path.
	181	+ => tftp 1000000 uImage
	182	+ => tftp 2000000 p1010rdb.dtb
	183	+ => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
	184	+ => bootm 1000000 3000000 2000000
	185	+
	186	+
	187	+For more details, please refer to P1010RDB-PB User Guide and access website
	188	+www.freescale.com and Freescale QorIQ SDK Infocenter document.

doc/README.p1010rdb

View file @ 62af761

1		-Overview
2		-=========
3		-The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
4		-
5		-The P1010 is a cost-effective, low-power, highly integrated host processor
6		-based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
7		-that addresses the requirements of several routing, gateways, storage, consumer,
8		-and industrial applications. Applications of interest include the main CPUs and
9		-I/O processors in network attached storage (NAS), the voice over IP (VoIP)
10		-router/gateway, and wireless LAN (WLAN) and industrial controllers.
11		-
12		-The P1010RDB board features are as follows:
13		-Memory subsystem:
14		- - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
15		- - 32 Mbyte NOR flash single-chip memory
16		- - 32 Mbyte NAND flash memory
17		- - 256 Kbit M24256 I2C EEPROM
18		- - 16 Mbyte SPI memory
19		- - I2C Board EEPROM 128x8 bit memory
20		- - SD/MMC connector to interface with the SD memory card
21		-Interfaces:
22		- - PCIe:
23		- - Lane0: x1 mini-PCIe slot
24		- - Lane1: x1 PCIe standard slot
25		- - SATA:
26		- - 1 internal SATA connector to 2.5" 160G SATA2 HDD
27		- - 1 eSATA connector to rear panel
28		- - 10/100/1000 BaseT Ethernet ports:
29		- - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
30		- - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
31		- - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
32		- - USB 2.0 port:
33		- - x1 USB2.0 port: via an ULPI PHY to micro-AB connector
34		- - x1 USB2.0 poort via an internal PHY to micro-AB connector
35		- - FlexCAN ports:
36		- - x2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
37		- interface;
38		- - DUART interface:
39		- - DUART interface: supports two UARTs up to 115200 bps for
40		- console display
41		- - J45 connectors are used for these 2 UART ports.
42		- - TDM
43		- - 2 FXS ports connected via an external SLIC to the TDM
44		- interface. SLIC is controllled via SPI.
45		- - 1 FXO port connected via a relay to FXS for switchover to
46		- POTS
47		-Board connectors:
48		- - Mini-ITX power supply connector
49		- - JTAG/COP for debugging
50		-IEEE Std. 1588 signals for test and measurement
51		-Real-time clock on I2C bus
52		-POR
53		- - support critical POR setting changed via switch on board
54		-PCB
55		- - 6-layer routing (4-layer signals, 2-layer power and ground)
56		-
57		-
58		-Serial Port Configuration on P1010RDB
59		-=====================================
60		-Configure the serial port of the attached computer with the following values:
61		- -Data rate: 115200 bps
62		- -Number of data bits: 8
63		- -Parity: None
64		- -Number of Stop bits: 1
65		- -Flow Control: Hardware/None
66		-
67		-
68		-Settings of DIP-switch
69		-======================
70		- SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
71		- SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
72		- SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
73		-Note: 1 stands for 'on', 0 stands for 'off'
74		-
75		-
76		-Setting of hwconfig
77		-===================
78		-If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
79		-"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
80		-setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
81		-By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
82		-is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
83		-instead of to CAN/UART1.
84		-
85		-
86		-Build and burn u-boot to NOR flash
87		-==================================
88		-1. Build u-boot.bin image
89		- export ARCH=powerpc
90		- export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
91		- make P1010RDB_NOR
92		-
93		-2. Burn u-boot.bin into NOR flash
94		- => tftp $loadaddr $uboot
95		- => protect off eff80000 +$filesize
96		- => erase eff80000 +$filesize
97		- => cp.b $loadaddr eff80000 $filesize
98		-
99		-3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
100		-
101		-
102		-Alternate NOR bank
103		-============================
104		-1. Burn u-boot.bin into alternate NOR bank
105		- => tftp $loadaddr $uboot
106		- => protect off eef80000 +$filesize
107		- => erase eef80000 +$filesize
108		- => cp.b $loadaddr eef80000 $filesize
109		-
110		-2. Switch to alternate NOR bank
111		- => mw.b ffb00009 1
112		- => reset
113		- or set SW1[8]= ON
114		-
115		-SW1[8]= OFF: Upper bank used for booting start
116		-SW1[8]= ON: Lower bank used for booting start
117		-CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
118		-0 - boot from upper 4 sectors
119		-1 - boot from lower 4 sectors
120		-
121		-
122		-Build and burn u-boot to NAND flash
123		-===================================
124		-1. Build u-boot.bin image
125		- export ARCH=powerpc
126		- export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
127		- make P1010RDB_NAND
128		-
129		-2. Burn u-boot-nand.bin into NAND flash
130		- => tftp $loadaddr $uboot-nand
131		- => nand erase 0 $filesize
132		- => nand write $loadaddr 0 $filesize
133		-
134		-3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
135		-
136		-
137		-
138		-Build and burn u-boot to SPI flash
139		-==================================
140		-1. Build u-boot-spi.bin image
141		- make P1010RDB_SPIFLASH_config; make
142		- Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
143		- Download u-boot.bin to linux and you can find some config files
144		- under /usr/share such as config_xx.dat. Do below command:
145		- boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
146		- u-boot-spi.bin
147		- to generate u-boot-spi.bin.
148		-
149		-2. Burn u-boot-spi.bin into SPI flash
150		- => tftp $loadaddr $uboot-spi
151		- => sf erase 0 100000
152		- => sf write $loadaddr 0 $filesize
153		-
154		-3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
155		-
156		-
157		-
158		-CPLD POR setting registers
159		-==========================
160		-1. Set POR switch selection register (addr 0xFFB00011) to 0.
161		-2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
162		- proper values.
163		- If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
164		- switch command by I2C.
165		-3. Send reset command.
166		- After reset, the new POR setting will be implemented.
167		-
168		-Two examples are given in below:
169		-Switch from NOR to NAND boot with default frequency:
170		- => i2c dev 0
171		- => i2c mw 18 1 f9
172		- => i2c mw 18 3 f0
173		- => mw.b ffb00011 0
174		- => mw.b ffb00017 1
175		- => reset
176		-Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
177		- => i2c dev 0
178		- => i2c mw 18 1 f1
179		- => i2c mw 18 3 f0
180		- => mw.b ffb00011 0
181		- => mw.b ffb00014 2
182		- => mw.b ffb00015 5
183		- => mw.b ffb00016 3
184		- => mw.b ffb00017 f
185		- => reset
186		-
187		-
188		-Boot Linux from network using TFTP on P1010RDB
189		-==============================================
190		-Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
191		- => tftp 1000000 uImage
192		- => tftp 2000000 p1010rdb.dtb
193		- => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
194		- => bootm 1000000 3000000 2000000
195		-
196		-
197		-Please contact your local field applications engineer or sales representative
198		-to obtain related documents, such as P1010-RDB User Guide for details.