Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 62cbddc493e5f4c6c1e1ba62bdf36f3df4708a16

Authored by Nobuhiro Iwamatsu
1 parent 55e8250bd3
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

net: sh-eth: Add support R7S72100 of rmobile 

The R7S72100 of ARM SoC that Renesas manufactured has one Ether port.
This has the same IP SH-Ether. This patch adds support of the R7S72100
in SH-Ether.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Showing 2 changed files with 77 additions and 14 deletions Side-by-side Diff

drivers/net/sh_eth.c
Diff comments   View file @ 62cbddc
... ... @@ -148,7 +148,7 @@
148 148  
149 149 static int sh_eth_reset(struct sh_eth_dev *eth)
150 150 {
151   -#if defined(SH_ETH_TYPE_GETHER)
  151 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
152 152 int ret = 0, i;
153 153  
154 154 /* Start e-dmac transmitter and receiver */
... ... @@ -218,7 +218,7 @@
218 218 /* Point the controller to the tx descriptor list. Must use physical
219 219 addresses */
220 220 sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
221   -#if defined(SH_ETH_TYPE_GETHER)
  221 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
222 222 sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
223 223 sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
224 224 sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
... ... @@ -288,7 +288,7 @@
288 288  
289 289 /* Point the controller to the rx descriptor list */
290 290 sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
291   -#if defined(SH_ETH_TYPE_GETHER)
  291 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
292 292 sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
293 293 sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
294 294 sh_eth_write(eth, RDFFR_RDLF, RDFFR);
... ... @@ -384,7 +384,7 @@
384 384 sh_eth_write(eth, 0, TFTR);
385 385 sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
386 386 sh_eth_write(eth, RMCR_RST, RMCR);
387   -#if defined(SH_ETH_TYPE_GETHER)
  387 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
388 388 sh_eth_write(eth, 0, RPADIR);
389 389 #endif
390 390 sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
... ... @@ -403,6 +403,8 @@
403 403 sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
404 404 #if defined(SH_ETH_TYPE_GETHER)
405 405 sh_eth_write(eth, 0, PIPR);
  406 +#endif
  407 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
406 408 sh_eth_write(eth, APR_AP, APR);
407 409 sh_eth_write(eth, MPR_MP, MPR);
408 410 sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
drivers/net/sh_eth.h
Diff comments   View file @ 62cbddc
... ... @@ -230,6 +230,61 @@
230 230 [RMII_MII] = 0x0790,
231 231 };
232 232  
  233 +#if defined(SH_ETH_TYPE_RZ)
  234 +static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
  235 + [EDSR] = 0x0000,
  236 + [EDMR] = 0x0400,
  237 + [EDTRR] = 0x0408,
  238 + [EDRRR] = 0x0410,
  239 + [EESR] = 0x0428,
  240 + [EESIPR] = 0x0430,
  241 + [TDLAR] = 0x0010,
  242 + [TDFAR] = 0x0014,
  243 + [TDFXR] = 0x0018,
  244 + [TDFFR] = 0x001c,
  245 + [RDLAR] = 0x0030,
  246 + [RDFAR] = 0x0034,
  247 + [RDFXR] = 0x0038,
  248 + [RDFFR] = 0x003c,
  249 + [TRSCER] = 0x0438,
  250 + [RMFCR] = 0x0440,
  251 + [TFTR] = 0x0448,
  252 + [FDR] = 0x0450,
  253 + [RMCR] = 0x0458,
  254 + [RPADIR] = 0x0460,
  255 + [FCFTR] = 0x0468,
  256 + [CSMR] = 0x04E4,
  257 +
  258 + [ECMR] = 0x0500,
  259 + [ECSR] = 0x0510,
  260 + [ECSIPR] = 0x0518,
  261 + [PSR] = 0x0528,
  262 + [PIPR] = 0x052c,
  263 + [RFLR] = 0x0508,
  264 + [APR] = 0x0554,
  265 + [MPR] = 0x0558,
  266 + [PFTCR] = 0x055c,
  267 + [PFRCR] = 0x0560,
  268 + [TPAUSER] = 0x0564,
  269 + [GECMR] = 0x05b0,
  270 + [BCULR] = 0x05b4,
  271 + [MAHR] = 0x05c0,
  272 + [MALR] = 0x05c8,
  273 + [TROCR] = 0x0700,
  274 + [CDCR] = 0x0708,
  275 + [LCCR] = 0x0710,
  276 + [CEFCR] = 0x0740,
  277 + [FRECR] = 0x0748,
  278 + [TSFRCR] = 0x0750,
  279 + [TLFRCR] = 0x0758,
  280 + [RFCR] = 0x0760,
  281 + [CERCR] = 0x0768,
  282 + [CEECR] = 0x0770,
  283 + [MAFCR] = 0x0778,
  284 + [RMII_MII] = 0x0790,
  285 +};
  286 +#endif
  287 +
233 288 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
234 289 [ECMR] = 0x0100,
235 290 [RFLR] = 0x0108,
236 291  
... ... @@ -306,13 +361,16 @@
306 361 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
307 362 #define SH_ETH_TYPE_ETHER
308 363 #define BASE_IO_ADDR 0xEE700200
  364 +#elif defined(CONFIG_R7S72100)
  365 +#define SH_ETH_TYPE_RZ
  366 +#define BASE_IO_ADDR 0xE8203000
309 367 #endif
310 368  
311 369 /*
312 370 * Register's bits
313 371 * Copy from Linux driver source code
314 372 */
315   -#if defined(SH_ETH_TYPE_GETHER)
  373 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
316 374 /* EDSR */
317 375 enum EDSR_BIT {
318 376 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
... ... @@ -323,7 +381,7 @@
323 381 /* EDMR */
324 382 enum DMAC_M_BIT {
325 383 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
326   -#if defined(SH_ETH_TYPE_GETHER)
  384 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
327 385 EDMR_SRST = 0x03, /* Receive/Send reset */
328 386 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
329 387 EDMR_EL = 0x40, /* Litte endian */
... ... @@ -349,7 +407,7 @@
349 407  
350 408 /* EDTRR */
351 409 enum DMAC_T_BIT {
352   -#if defined(SH_ETH_TYPE_GETHER)
  410 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
353 411 EDTRR_TRNS = 0x03,
354 412 #else
355 413 EDTRR_TRNS = 0x01,
... ... @@ -424,7 +482,7 @@
424 482 };
425 483  
426 484  
427   -#if defined(SH_ETH_TYPE_GETHER)
  485 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
428 486 # define TX_CHECK (EESR_TC1 | EESR_FTC)
429 487 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
430 488 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
... ... @@ -484,7 +542,8 @@
484 542  
485 543 /* Transfer descriptor bit */
486 544 enum TD_STS_BIT {
487   -#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER)
  545 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
  546 + defined(SH_ETH_TYPE_RZ)
488 547 TD_TACT = 0x80000000,
489 548 #else
490 549 TD_TACT = 0x7fffffff,
... ... @@ -500,7 +559,7 @@
500 559 enum RECV_RST_BIT { RMCR_RST = 0x01, };
501 560 /* ECMR */
502 561 enum FELIC_MODE_BIT {
503   -#if defined(SH_ETH_TYPE_GETHER)
  562 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
504 563 ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
505 564 ECMR_RZPF = 0x00100000,
506 565 #endif
... ... @@ -517,7 +576,7 @@
517 576  
518 577 };
519 578  
520   -#if defined(SH_ETH_TYPE_GETHER)
  579 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
521 580 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
522 581 ECMR_TXF | ECMR_MCT)
523 582 #elif defined(SH_ETH_TYPE_ETHER)
... ... @@ -535,7 +594,7 @@
535 594 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
536 595 };
537 596  
538   -#if defined(SH_ETH_TYPE_GETHER)
  597 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
539 598 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
540 599 #else
541 600 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
... ... @@ -556,7 +615,7 @@
556 615 ECSIPR_ICDIP = 0x01,
557 616 };
558 617  
559   -#if defined(SH_ETH_TYPE_GETHER)
  618 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
560 619 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
561 620 #else
562 621 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
... ... @@ -587,7 +646,7 @@
587 646 RPADIR_PADR = 0x0003f,
588 647 };
589 648  
590   -#if defined(SH_ETH_TYPE_GETHER)
  649 +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
591 650 # define RPADIR_INIT (0x00)
592 651 #else
593 652 # define RPADIR_INIT (RPADIR_PADS1)
... ... @@ -605,6 +664,8 @@
605 664 const u16 *reg_offset = sh_eth_offset_gigabit;
606 665 #elif defined(SH_ETH_TYPE_ETHER)
607 666 const u16 *reg_offset = sh_eth_offset_fast_sh4;
  667 +#elif defined(SH_ETH_TYPE_RZ)
  668 + const u16 *reg_offset = sh_eth_offset_rz;
608 669 #else
609 670 #error
610 671 #endif