mpc52xx: Add SPI driver.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>

mpc52xx: Add SPI driver.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Grzegorz Bernacki · Wolfgang Denk
1 parent 5ec5529b82
Showing 3 changed files with 128 additions and 0 deletions Side-by-side Diff
drivers/spi/Makefile
drivers/spi/mpc52xx_spi.c
include/mpc5xxx.h
@@ -28,6 +28,7 @@
 COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
+COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
 COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
 COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
 COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
+/*
+ * (C) Copyright 2009
+ * Frank Bodammer <frank.bodammer@gcd-solutions.de>
+ * (C) Copyright 2009 Semihalf, Grzegorz Bernacki
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <spi.h>
+#include <mpc5xxx.h>
+
+void spi_init(void)
+{
+	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi *)MPC5XXX_SPI;
+	/*
+	 * Its important to use the correct order when initializing the
+	 * registers
+	 */
+	out_8(&spi->ddr, 0x0F);	/* set all SPI pins as output */
+	out_8(&spi->pdr, 0x00);	/* set SS low */
+	/* SPI is master, SS is general purpose output */
+	out_8(&spi->cr1, SPI_CR_MSTR | SPI_CR_SPE);
+	out_8(&spi->cr2, 0x00);	/* normal operation */
+	out_8(&spi->brr, 0x77);	/* baud rate: IPB clock / 2048 */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int mode)
+{
+	struct spi_slave *slave;
+
+	slave = malloc(sizeof(struct spi_slave));
+	if (!slave)
+		return NULL;
+
+	slave->bus = bus;
+	slave->cs = cs;
+
+	return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	return;
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+	     void *din, unsigned long flags)
+{
+	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi *)MPC5XXX_SPI;
+	int i, iter = bitlen >> 3;
+	const uchar *txp = dout;
+	uchar *rxp = din;
+
+	debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
+	      slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen);
+
+	if (flags & SPI_XFER_BEGIN)
+		setbits_8(&spi->pdr, SPI_PDR_SS);
+
+	for (i = 0; i < iter; i++) {
+		udelay(1000);
+		debug("spi_xfer: sending %x\n", txp[i]);
+		out_8(&spi->dr, txp[i]);
+		while (!(in_8(&spi->sr) & SPI_SR_SPIF)) {
+			udelay(1000);
+			if (in_8(&spi->sr) & SPI_SR_WCOL) {
+				rxp[i] = in_8(&spi->dr);
+				puts("spi_xfer: write collision\n");
+				return -1;
+			}
+		}
+		rxp[i] = in_8(&spi->dr);
+		debug("spi_xfer: received %x\n", rxp[i]);
+	}
+	if (flags & SPI_XFER_END)
+		clrbits_8(&spi->pdr, SPI_PDR_SS);
+
+	return 0;
+}
@@ -392,6 +392,24 @@
 #define I2C_IF		0x02
 #define I2C_RXAK	0x01
  
+/* SPI control register 1 bits */
+#define SPI_CR_LSBFE	0x01
+#define SPI_CR_SSOE	0x02
+#define SPI_CR_CPHA	0x04
+#define SPI_CR_CPOL	0x08
+#define SPI_CR_MSTR	0x10
+#define SPI_CR_SWOM	0x20
+#define SPI_CR_SPE	0x40
+#define SPI_CR_SPIE	0x80
+
+/* SPI status register bits */
+#define SPI_SR_MODF	0x10
+#define SPI_SR_WCOL	0x40
+#define SPI_SR_SPIF	0x80
+
+/* SPI port data register bits */
+#define SPI_PDR_SS	0x08
+
 /* Programmable Serial Controller (PSC) status register bits */
 #define PSC_SR_CDE		0x0080
 #define PSC_SR_RXRDY		0x0100
...	...	@@ -28,6 +28,7 @@
28	28	COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
29	29	COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
30	30	COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
	31	+COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
31	32	COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
32	33	COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
33	34	COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
	1	+/*
	2	+ * (C) Copyright 2009
	3	+ * Frank Bodammer <frank.bodammer@gcd-solutions.de>
	4	+ * (C) Copyright 2009 Semihalf, Grzegorz Bernacki
	5	+ *
	6	+ * See file CREDITS for list of people who contributed to this
	7	+ * project.
	8	+ *
	9	+ * This program is free software; you can redistribute it and/or
	10	+ * modify it under the terms of the GNU General Public License as
	11	+ * published by the Free Software Foundation; either version 2 of
	12	+ * the License, or (at your option) any later version.
	13	+ *
	14	+ * This program is distributed in the hope that it will be useful,
	15	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+ * GNU General Public License for more details.
	18	+ *
	19	+ * You should have received a copy of the GNU General Public License
	20	+ * along with this program; if not, write to the Free Software
	21	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	+ * MA 02111-1307 USA
	23	+ */
	24	+
	25	+#include <common.h>
	26	+#include <asm/io.h>
	27	+#include <malloc.h>
	28	+#include <spi.h>
	29	+#include <mpc5xxx.h>
	30	+
	31	+void spi_init(void)
	32	+{
	33	+ struct mpc5xxx_spi spi = (struct mpc5xxx_spi )MPC5XXX_SPI;
	34	+ /*
	35	+ * Its important to use the correct order when initializing the
	36	+ * registers
	37	+ */
	38	+ out_8(&spi->ddr, 0x0F); /* set all SPI pins as output */
	39	+ out_8(&spi->pdr, 0x00); /* set SS low */
	40	+ /* SPI is master, SS is general purpose output */
	41	+ out_8(&spi->cr1, SPI_CR_MSTR \| SPI_CR_SPE);
	42	+ out_8(&spi->cr2, 0x00); /* normal operation */
	43	+ out_8(&spi->brr, 0x77); /* baud rate: IPB clock / 2048 */
	44	+}
	45	+
	46	+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
	47	+ unsigned int max_hz, unsigned int mode)
	48	+{
	49	+ struct spi_slave *slave;
	50	+
	51	+ slave = malloc(sizeof(struct spi_slave));
	52	+ if (!slave)
	53	+ return NULL;
	54	+
	55	+ slave->bus = bus;
	56	+ slave->cs = cs;
	57	+
	58	+ return slave;
	59	+}
	60	+
	61	+void spi_free_slave(struct spi_slave *slave)
	62	+{
	63	+ free(slave);
	64	+}
	65	+
	66	+int spi_claim_bus(struct spi_slave *slave)
	67	+{
	68	+ return 0;
	69	+}
	70	+
	71	+void spi_release_bus(struct spi_slave *slave)
	72	+{
	73	+ return;
	74	+}
	75	+
	76	+int spi_xfer(struct spi_slave slave, unsigned int bitlen, const void dout,
	77	+ void *din, unsigned long flags)
	78	+{
	79	+ struct mpc5xxx_spi spi = (struct mpc5xxx_spi )MPC5XXX_SPI;
	80	+ int i, iter = bitlen >> 3;
	81	+ const uchar *txp = dout;
	82	+ uchar *rxp = din;
	83	+
	84	+ debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
	85	+ slave->bus, slave->cs, (uint ) dout, (uint ) din, bitlen);
	86	+
	87	+ if (flags & SPI_XFER_BEGIN)
	88	+ setbits_8(&spi->pdr, SPI_PDR_SS);
	89	+
	90	+ for (i = 0; i < iter; i++) {
	91	+ udelay(1000);
	92	+ debug("spi_xfer: sending %x\n", txp[i]);
	93	+ out_8(&spi->dr, txp[i]);
	94	+ while (!(in_8(&spi->sr) & SPI_SR_SPIF)) {
	95	+ udelay(1000);
	96	+ if (in_8(&spi->sr) & SPI_SR_WCOL) {
	97	+ rxp[i] = in_8(&spi->dr);
	98	+ puts("spi_xfer: write collision\n");
	99	+ return -1;
	100	+ }
	101	+ }
	102	+ rxp[i] = in_8(&spi->dr);
	103	+ debug("spi_xfer: received %x\n", rxp[i]);
	104	+ }
	105	+ if (flags & SPI_XFER_END)
	106	+ clrbits_8(&spi->pdr, SPI_PDR_SS);
	107	+
	108	+ return 0;
	109	+}
...	...	@@ -392,6 +392,24 @@
392	392	#define I2C_IF 0x02
393	393	#define I2C_RXAK 0x01
394	394
	395	+/* SPI control register 1 bits */
	396	+#define SPI_CR_LSBFE 0x01
	397	+#define SPI_CR_SSOE 0x02
	398	+#define SPI_CR_CPHA 0x04
	399	+#define SPI_CR_CPOL 0x08
	400	+#define SPI_CR_MSTR 0x10
	401	+#define SPI_CR_SWOM 0x20
	402	+#define SPI_CR_SPE 0x40
	403	+#define SPI_CR_SPIE 0x80
	404	+
	405	+/* SPI status register bits */
	406	+#define SPI_SR_MODF 0x10
	407	+#define SPI_SR_WCOL 0x40
	408	+#define SPI_SR_SPIF 0x80
	409	+
	410	+/* SPI port data register bits */
	411	+#define SPI_PDR_SS 0x08
	412	+
395	413	/* Programmable Serial Controller (PSC) status register bits */
396	414	#define PSC_SR_CDE 0x0080
397	415	#define PSC_SR_RXRDY 0x0100