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Commit 63b2316c5c4ba0e47d1f69ef1372db4fd89b6bf5

Authored by Ashish Kumar
Committed by York Sun
1 parent 584f316f11
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

fsl-layerscape: Consolidate registers space defination for CCI-400 bus 

CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.

This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 15 changed files with 110 additions and 109 deletions Side-by-side Diff

... ... @@ -312,6 +312,15 @@
312 312 kernel configuration options. The intention is to make it easier to
313 313 build a config tool - later.
314 314  
  315 +- ARM Platform Bus Type(CCI):
  316 + CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
  317 + provides full cache coherency between two clusters of multi-core
  318 + CPUs and I/O coherency for devices and I/O masters
  319 +
  320 + CONFIG_SYS_FSL_HAS_CCI400
  321 +
  322 + Defined For SoC that has cache coherent interconnect
  323 + CCN-400
315 324  
316 325 The following options need to be configured:
317 326  
arch/arm/cpu/armv7/ls102xa/Kconfig
Diff comments   View file @ 63b2316
... ... @@ -5,6 +5,7 @@
5 5 select SYS_FSL_ERRATUM_A009663
6 6 select SYS_FSL_ERRATUM_A009942
7 7 select SYS_FSL_ERRATUM_A010315
  8 + select SYS_FSL_HAS_CCI400
8 9 select SYS_FSL_SRDS_1
9 10 select SYS_HAS_SERDES
10 11 select SYS_FSL_DDR_BE if SYS_FSL_DDR
11 12  
... ... @@ -49,8 +50,19 @@
49 50 Enable Freescale Secure Boot feature. Normally selected
50 51 by defconfig. If unsure, do not change.
51 52  
  53 +config SYS_CCI400_OFFSET
  54 + hex "Offset for CCI400 base"
  55 + depends on SYS_FSL_HAS_CCI400
  56 + default 0x180000
  57 + help
  58 + Offset for CCI400 base.
  59 + CCI400 base addr = CCSRBAR + CCI400_OFFSET
  60 +
52 61 config SYS_FSL_ERRATUM_A010315
53 62 bool "Workaround for PCIe erratum A010315"
  63 +
  64 +config SYS_FSL_HAS_CCI400
  65 + bool
54 66  
55 67 config SYS_FSL_SRDS_1
56 68 bool
arch/arm/cpu/armv7/ls102xa/soc.c
Diff comments   View file @ 63b2316
... ... @@ -80,7 +80,8 @@
80 80 int arch_soc_init(void)
81 81 {
82 82 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
83   - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
  83 + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  84 + CONFIG_SYS_CCI400_OFFSET);
84 85 unsigned int major;
85 86  
86 87 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
Diff comments   View file @ 63b2316
... ... @@ -85,6 +85,7 @@
85 85  
86 86 config FSL_LSCH2
87 87 bool
  88 + select SYS_FSL_HAS_CCI400
88 89 select SYS_FSL_HAS_SEC
89 90 select SYS_FSL_SEC_COMPAT_5
90 91 select SYS_FSL_SEC_BE
91 92  
... ... @@ -248,12 +249,24 @@
248 249 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
249 250 bus for those flashes to support the full QSPI flash size.
250 251  
  252 +config SYS_CCI400_OFFSET
  253 + hex "Offset for CCI400 base"
  254 + depends on SYS_FSL_HAS_CCI400
  255 + default 0x3090000 if ARCH_LS1088A
  256 + default 0x180000 if FSL_LSCH2
  257 + help
  258 + Offset for CCI400 base
  259 + CCI400 base addr = CCSRBAR + CCI400_OFFSET
  260 +
251 261 config SYS_FSL_IFC_BANK_COUNT
252 262 int "Maximum banks of Integrated flash controller"
253 263 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
254 264 default 4 if ARCH_LS1043A
255 265 default 4 if ARCH_LS1046A
256 266 default 8 if ARCH_LS2080A
  267 +
  268 +config SYS_FSL_HAS_CCI400
  269 + bool
257 270  
258 271 config SYS_FSL_HAS_DP_DDR
259 272 bool
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
Diff comments   View file @ 63b2316
... ... @@ -16,6 +16,7 @@
16 16 #include <asm/arch/soc.h>
17 17 #include <asm/arch/cpu.h>
18 18 #include <asm/arch/speed.h>
  19 +#include <fsl_immap.h>
19 20 #include <asm/arch/mp.h>
20 21 #include <efi_loader.h>
21 22 #include <fm_eth.h>
arch/arm/cpu/armv8/fsl-layerscape/soc.c
Diff comments   View file @ 63b2316
... ... @@ -5,6 +5,7 @@
5 5 */
6 6  
7 7 #include <common.h>
  8 +#include <fsl_immap.h>
8 9 #include <fsl_ifc.h>
9 10 #include <ahci.h>
10 11 #include <scsi.h>
... ... @@ -285,7 +286,8 @@
285 286 {
286 287 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
287 288 /* part 1 of 2 */
288   - struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
  289 + struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  290 + CONFIG_SYS_CCI400_OFFSET);
289 291 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
290 292  
291 293 /* Skip if running at lower exception level */
... ... @@ -304,7 +306,8 @@
304 306 {
305 307 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
306 308 /* part 2 of 2 */
307   - struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
  309 + struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  310 + CONFIG_SYS_CCI400_OFFSET);
308 311 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
309 312 u32 tmp;
310 313  
... ... @@ -439,7 +442,8 @@
439 442  
440 443 void fsl_lsch2_early_init_f(void)
441 444 {
442   - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
  445 + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  446 + CONFIG_SYS_CCI400_OFFSET);
443 447 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
444 448  
445 449 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
Diff comments   View file @ 63b2316
... ... @@ -15,7 +15,6 @@
15 15 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
16 16  
17 17 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
18   -#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
19 18 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
20 19 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
21 20 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
... ... @@ -542,54 +541,6 @@
542 541 u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */
543 542 } xfi[2]; /* Lane A, B */
544 543 u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
545   -};
546   -
547   -#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
548   -#define CCI400_CTRLORD_EN_BARRIER 0
549   -#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
550   -#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
551   -#define CCI400_SNOOP_REQ_EN 0x00000001
552   -
553   -/* CCI-400 registers */
554   -struct ccsr_cci400 {
555   - u32 ctrl_ord; /* Control Override */
556   - u32 spec_ctrl; /* Speculation Control */
557   - u32 secure_access; /* Secure Access */
558   - u32 status; /* Status */
559   - u32 impr_err; /* Imprecise Error */
560   - u8 res_14[0x100 - 0x14];
561   - u32 pmcr; /* Performance Monitor Control */
562   - u8 res_104[0xfd0 - 0x104];
563   - u32 pid[8]; /* Peripheral ID */
564   - u32 cid[4]; /* Component ID */
565   - struct {
566   - u32 snoop_ctrl; /* Snoop Control */
567   - u32 sha_ord; /* Shareable Override */
568   - u8 res_1008[0x1100 - 0x1008];
569   - u32 rc_qos_ord; /* read channel QoS Value Override */
570   - u32 wc_qos_ord; /* read channel QoS Value Override */
571   - u8 res_1108[0x110c - 0x1108];
572   - u32 qos_ctrl; /* QoS Control */
573   - u32 max_ot; /* Max OT */
574   - u8 res_1114[0x1130 - 0x1114];
575   - u32 target_lat; /* Target Latency */
576   - u32 latency_regu; /* Latency Regulation */
577   - u32 qos_range; /* QoS Range */
578   - u8 res_113c[0x2000 - 0x113c];
579   - } slave[5]; /* Slave Interface */
580   - u8 res_6000[0x9004 - 0x6000];
581   - u32 cycle_counter; /* Cycle counter */
582   - u32 count_ctrl; /* Count Control */
583   - u32 overflow_status; /* Overflow Flag Status */
584   - u8 res_9010[0xa000 - 0x9010];
585   - struct {
586   - u32 event_select; /* Event Select */
587   - u32 event_count; /* Event Count */
588   - u32 counter_ctrl; /* Counter Control */
589   - u32 overflow_status; /* Overflow Flag Status */
590   - u8 res_a010[0xb000 - 0xa010];
591   - } pcounter[4]; /* Performance Counter */
592   - u8 res_e004[0x10000 - 0xe004];
593 544 };
594 545  
595 546 /* MMU 500 */
arch/arm/include/asm/arch-ls102xa/config.h
Diff comments   View file @ 63b2316
... ... @@ -20,7 +20,6 @@
20 20  
21 21 #define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
22 22 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
23   -#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
24 23 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
25 24 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
26 25 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
Diff comments   View file @ 63b2316
... ... @@ -6,6 +6,7 @@
6 6  
7 7 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_
8 8 #define __ASM_ARCH_LS102XA_IMMAP_H_
  9 +#include <fsl_immap.h>
9 10  
10 11 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
11 12 #define SVR_MIN(svr) (((svr) >> 0) & 0xf)
12 13  
... ... @@ -374,53 +375,7 @@
374 375 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
375 376 };
376 377  
377   -#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
378   -#define CCI400_CTRLORD_EN_BARRIER 0
379   -#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
380   -#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
381   -#define CCI400_SNOOP_REQ_EN 0x00000001
382 378  
383   -/* CCI-400 registers */
384   -struct ccsr_cci400 {
385   - u32 ctrl_ord; /* Control Override */
386   - u32 spec_ctrl; /* Speculation Control */
387   - u32 secure_access; /* Secure Access */
388   - u32 status; /* Status */
389   - u32 impr_err; /* Imprecise Error */
390   - u8 res_14[0x100 - 0x14];
391   - u32 pmcr; /* Performance Monitor Control */
392   - u8 res_104[0xfd0 - 0x104];
393   - u32 pid[8]; /* Peripheral ID */
394   - u32 cid[4]; /* Component ID */
395   - struct {
396   - u32 snoop_ctrl; /* Snoop Control */
397   - u32 sha_ord; /* Shareable Override */
398   - u8 res_1008[0x1100 - 0x1008];
399   - u32 rc_qos_ord; /* read channel QoS Value Override */
400   - u32 wc_qos_ord; /* read channel QoS Value Override */
401   - u8 res_1108[0x110c - 0x1108];
402   - u32 qos_ctrl; /* QoS Control */
403   - u32 max_ot; /* Max OT */
404   - u8 res_1114[0x1130 - 0x1114];
405   - u32 target_lat; /* Target Latency */
406   - u32 latency_regu; /* Latency Regulation */
407   - u32 qos_range; /* QoS Range */
408   - u8 res_113c[0x2000 - 0x113c];
409   - } slave[5]; /* Slave Interface */
410   - u8 res_6000[0x9004 - 0x6000];
411   - u32 cycle_counter; /* Cycle counter */
412   - u32 count_ctrl; /* Count Control */
413   - u32 overflow_status; /* Overflow Flag Status */
414   - u8 res_9010[0xa000 - 0x9010];
415   - struct {
416   - u32 event_select; /* Event Select */
417   - u32 event_count; /* Event Count */
418   - u32 counter_ctrl; /* Counter Control */
419   - u32 overflow_status; /* Overflow Flag Status */
420   - u8 res_a010[0xb000 - 0xa010];
421   - } pcounter[4]; /* Performance Counter */
422   - u8 res_e004[0x10000 - 0xe004];
423   -};
424 379  
425 380 /* AHCI (sata) register map */
426 381 struct ccsr_ahci {
board/freescale/ls1012afrdm/ls1012afrdm.c
Diff comments   View file @ 63b2316
... ... @@ -71,7 +71,9 @@
71 71  
72 72 int board_init(void)
73 73 {
74   - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
  74 + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  75 + CONFIG_SYS_CCI400_OFFSET);
  76 +
75 77 /*
76 78 * Set CCI-400 control override register to enable barrier
77 79 * transaction
board/freescale/ls1012aqds/ls1012aqds.c
Diff comments   View file @ 63b2316
... ... @@ -106,8 +106,8 @@
106 106  
107 107 int board_init(void)
108 108 {
109   - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
110   - CONFIG_SYS_CCI400_ADDR;
  109 + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  110 + CONFIG_SYS_CCI400_OFFSET);
111 111  
112 112 /* Set CCI-400 control override register to enable barrier
113 113 * transaction */
board/freescale/ls1012ardb/ls1012ardb.c
Diff comments   View file @ 63b2316
... ... @@ -104,7 +104,8 @@
104 104  
105 105 int board_init(void)
106 106 {
107   - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
  107 + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  108 + CONFIG_SYS_CCI400_OFFSET);
108 109 /*
109 110 * Set CCI-400 control override register to enable barrier
110 111 * transaction
board/freescale/ls1021aqds/ls1021aqds.c
Diff comments   View file @ 63b2316
... ... @@ -204,7 +204,8 @@
204 204 #ifdef CONFIG_SPL_BUILD
205 205 void board_init_f(ulong dummy)
206 206 {
207   - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
  207 + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  208 + CONFIG_SYS_CCI400_OFFSET);
208 209 unsigned int major;
209 210  
210 211 #ifdef CONFIG_NAND_BOOT
... ... @@ -425,7 +426,8 @@
425 426  
426 427 int board_init(void)
427 428 {
428   - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
  429 + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  430 + CONFIG_SYS_CCI400_OFFSET);
429 431 unsigned int major;
430 432  
431 433 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
... ... @@ -460,7 +462,8 @@
460 462 #if defined(CONFIG_DEEP_SLEEP)
461 463 void board_sleep_prepare(void)
462 464 {
463   - struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
  465 + struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  466 + CONFIG_SYS_CCI400_OFFSET);
464 467 unsigned int major;
465 468  
466 469 major = get_soc_major_rev();
... ... @@ -133,5 +133,56 @@
133 133 u8 res_e5c[164];
134 134 u32 debug[64]; /* debug_1 to debug_64 */
135 135 };
  136 +
  137 +#ifdef CONFIG_SYS_FSL_HAS_CCI400
  138 +#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
  139 +#define CCI400_CTRLORD_EN_BARRIER 0
  140 +#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
  141 +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
  142 +#define CCI400_SNOOP_REQ_EN 0x00000001
  143 +
  144 +/* CCI-400 registers */
  145 +struct ccsr_cci400 {
  146 + u32 ctrl_ord; /* Control Override */
  147 + u32 spec_ctrl; /* Speculation Control */
  148 + u32 secure_access; /* Secure Access */
  149 + u32 status; /* Status */
  150 + u32 impr_err; /* Imprecise Error */
  151 + u8 res_14[0x100 - 0x14];
  152 + u32 pmcr; /* Performance Monitor Control */
  153 + u8 res_104[0xfd0 - 0x104];
  154 + u32 pid[8]; /* Peripheral ID */
  155 + u32 cid[4]; /* Component ID */
  156 + struct {
  157 + u32 snoop_ctrl; /* Snoop Control */
  158 + u32 sha_ord; /* Shareable Override */
  159 + u8 res_1008[0x1100 - 0x1008];
  160 + u32 rc_qos_ord; /* read channel QoS Value Override */
  161 + u32 wc_qos_ord; /* read channel QoS Value Override */
  162 + u8 res_1108[0x110c - 0x1108];
  163 + u32 qos_ctrl; /* QoS Control */
  164 + u32 max_ot; /* Max OT */
  165 + u8 res_1114[0x1130 - 0x1114];
  166 + u32 target_lat; /* Target Latency */
  167 + u32 latency_regu; /* Latency Regulation */
  168 + u32 qos_range; /* QoS Range */
  169 + u8 res_113c[0x2000 - 0x113c];
  170 + } slave[5]; /* Slave Interface */
  171 + u8 res_6000[0x9004 - 0x6000];
  172 + u32 cycle_counter; /* Cycle counter */
  173 + u32 count_ctrl; /* Count Control */
  174 + u32 overflow_status; /* Overflow Flag Status */
  175 + u8 res_9010[0xa000 - 0x9010];
  176 + struct {
  177 + u32 event_select; /* Event Select */
  178 + u32 event_count; /* Event Count */
  179 + u32 counter_ctrl; /* Counter Control */
  180 + u32 overflow_status; /* Overflow Flag Status */
  181 + u8 res_a010[0xb000 - 0xa010];
  182 + } pcounter[4]; /* Performance Counter */
  183 + u8 res_e004[0x10000 - 0xe004];
  184 +};
  185 +#endif
  186 +
136 187 #endif /* __FSL_IMMAP_H */
scripts/config_whitelist.txt
Diff comments   View file @ 63b2316
... ... @@ -2435,7 +2435,6 @@
2435 2435 CONFIG_SYS_CADMUS_BASE_REG
2436 2436 CONFIG_SYS_CBSIZE
2437 2437 CONFIG_SYS_CCCR
2438   -CONFIG_SYS_CCI400_ADDR
2439 2438 CONFIG_SYS_CCSRBAR
2440 2439 CONFIG_SYS_CCSRBAR_PHYS
2441 2440 CONFIG_SYS_CCSRBAR_PHYS_HIGH