Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 63dbfc00b947a0495c2714bddace233b21e42364

Authored by Ji Luo
1 parent 589b813043
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 4 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MA-14129 Update ddr training code for imx8mq_aiy 

Update the ddr training code to work with the atf 2.0.

Test: Build and boot on imx8mq aiy 3G board.

Change-Id: I8546c34cfa4aeeed819f7797f8362676e420b41f
Signed-off-by: Ji Luo <ji.luo@nxp.com>

Showing 12 changed files with 1742 additions and 2864 deletions Side-by-side Diff

arch/arm/mach-imx/imx8m/Kconfig
Diff comments   View file @ 63dbfc0
... ... @@ -42,6 +42,7 @@
42 42 bool "imx8mq_aiy"
43 43 select IMX8MQ
44 44 select SUPPORT_SPL
  45 + select IMX8M_LPDDR4
45 46  
46 47 config TARGET_IMX8MM_DDR4_VAL
47 48 bool "imx8mm DDR4 validation board"
board/freescale/imx8mq_aiy/Makefile
Diff comments   View file @ 63dbfc0
... ... @@ -8,6 +8,6 @@
8 8  
9 9 ifdef CONFIG_SPL_BUILD
10 10 obj-y += spl.o
11   -obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o
  11 +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_3g.o
12 12 endif
board/freescale/imx8mq_aiy/ddr/ddr.h
View file @ 63dbfc0
1   -/*
2   - * Copyright 2017 NXP
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -enum fw_type {
8   - FW_1D_IMAGE,
9   - FW_2D_IMAGE,
10   -};
11   -
12   -void ddr_init(void);
13   -void ddr_load_train_code(enum fw_type type);
14   -void lpddr4_800M_cfg_phy(void);
15   -
16   -static inline void reg32_write(unsigned long addr, u32 val)
17   -{
18   - writel(val, addr);
19   -}
20   -
21   -static inline uint32_t reg32_read(unsigned long addr)
22   -{
23   - return readl(addr);
24   -}
25   -
26   -static void inline dwc_ddrphy_apb_wr(unsigned long addr, u32 val)
27   -{
28   - writel(val, addr);
29   -}
30   -
31   -static inline void reg32setbit(unsigned long addr, u32 bit)
32   -{
33   - setbits_le32(addr, (1 << bit));
34   -}
board/freescale/imx8mq_aiy/ddr/ddr_init.c
View file @ 63dbfc0
1   -/*
2   - * Copyright 2017 NXP
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <common.h>
8   -#include <errno.h>
9   -#include <asm/io.h>
10   -#include <asm/arch/ddr.h>
11   -#include <asm/arch/clock.h>
12   -#include "ddr.h"
13   -
14   -#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
15   -#define ddr_printf(args...) printf(args)
16   -#else
17   -#define ddr_printf(args...)
18   -#endif
19   -
20   -#include "wait_ddrphy_training_complete.c"
21   -#ifndef SRC_DDRC_RCR_ADDR
22   -#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000
23   -#endif
24   -#ifndef DDR_CSD1_BASE_ADDR
25   -#define DDR_CSD1_BASE_ADDR 0x40000000
26   -#endif
27   -#define SILICON_TRAIN
28   -
29   -volatile unsigned int tmp, tmp_t, i;
30   -void lpddr4_800MHz_cfg_umctl2(void)
31   -{
32   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000304, 0x00000001);
33   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000030, 0x00000001);
34   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000000, 0x83080020);
35   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000064, 0x006180e0);
36   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d0, 0xc003061B);
37   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d4, 0x009D0000);
38   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d8, 0x0000fe05);
39   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000dc, 0x00d4002d);
40   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e0, 0x00310008);
41   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e4, 0x00040009);
42   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e8, 0x0046004d);
43   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000ec, 0x0005004d);
44   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000f4, 0x00000979);
45   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000100, 0x1a203522);
46   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000104, 0x00060630);
47   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000108, 0x070e1214);
48   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000010c, 0x00b0c006);
49   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000110, 0x0f04080f);
50   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000114, 0x0d0d0c0c);
51   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000118, 0x01010007);
52   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000011c, 0x0000060a);
53   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000120, 0x01010101);
54   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000124, 0x40000008);
55   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000128, 0x00050d01);
56   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000012c, 0x01010008);
57   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000130, 0x00020000);
58   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000134, 0x18100002);
59   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000138, 0x00000dc2);
60   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000013c, 0x80000000);
61   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000144, 0x00a00050);
62   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000180, 0x53200018);
63   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000184, 0x02800070);
64   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000188, 0x00000000);
65   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000190, 0x0397820a);
66   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00002190, 0x0397820a);
67   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00003190, 0x0397820a);
68   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000194, 0x00020103);
69   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a0, 0xe0400018);
70   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a4, 0x00df00e4);
71   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a8, 0x00000000);
72   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001b0, 0x00000011);
73   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001b4, 0x0000170a);
74   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001c0, 0x00000001);
75   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001c4, 0x00000000);
76   - /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
77   - dwc_ddrphy_apb_wr(DDRC_ADDRMAP0(0), 0x00000015);
78   - dwc_ddrphy_apb_wr(DDRC_ADDRMAP4(0), 0x00001F1F);
79   - /* bank interleave */
80   - dwc_ddrphy_apb_wr(DDRC_ADDRMAP1(0), 0x00080808);
81   - dwc_ddrphy_apb_wr(DDRC_ADDRMAP5(0), 0x07070707);
82   - dwc_ddrphy_apb_wr(DDRC_ADDRMAP6(0), 0x08080707);
83   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000240, 0x020f0c54);
84   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000244, 0x00000000);
85   - dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000490, 0x00000001);
86   -
87   - /* performance setting */
88   - dwc_ddrphy_apb_wr(DDRC_ODTCFG(0), 0x0b060908);
89   - dwc_ddrphy_apb_wr(DDRC_ODTMAP(0), 0x00000000);
90   - dwc_ddrphy_apb_wr(DDRC_SCHED(0), 0x29511505);
91   - dwc_ddrphy_apb_wr(DDRC_SCHED1(0), 0x0000002c);
92   - dwc_ddrphy_apb_wr(DDRC_PERFHPR1(0), 0x5900575b);
93   - dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x00000009);
94   - dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x02005574);
95   - dwc_ddrphy_apb_wr(DDRC_DBG0(0), 0x00000016);
96   - dwc_ddrphy_apb_wr(DDRC_DBG1(0), 0x00000000);
97   - dwc_ddrphy_apb_wr(DDRC_DBGCMD(0), 0x00000000);
98   - dwc_ddrphy_apb_wr(DDRC_SWCTL(0), 0x00000001);
99   - dwc_ddrphy_apb_wr(DDRC_POISONCFG(0), 0x00000011);
100   - dwc_ddrphy_apb_wr(DDRC_PCCFG(0), 0x00000111);
101   - dwc_ddrphy_apb_wr(DDRC_PCFGR_0(0), 0x000010f3);
102   - dwc_ddrphy_apb_wr(DDRC_PCFGW_0(0), 0x000072ff);
103   - dwc_ddrphy_apb_wr(DDRC_PCTRL_0(0), 0x00000001);
104   - dwc_ddrphy_apb_wr(DDRC_PCFGQOS0_0(0), 0x01110d00);
105   - dwc_ddrphy_apb_wr(DDRC_PCFGQOS1_0(0), 0x00620790);
106   - dwc_ddrphy_apb_wr(DDRC_PCFGWQOS0_0(0), 0x00100001);
107   - dwc_ddrphy_apb_wr(DDRC_PCFGWQOS1_0(0), 0x0000041f);
108   - dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEEN(0), 0x00000202);
109   - dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5);
110   - dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHCTL0(0), 0x00618040);
111   - dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHTMG(0), 0x00610090);
112   -}
113   -
114   -void lpddr4_100MHz_cfg_umctl2(void)
115   -{
116   - reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c);
117   - reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x00030410);
118   - reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x0305090c);
119   - reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x00505006);
120   - reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x05040305);
121   - reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504);
122   - reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x0a060004);
123   - reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x0000090e);
124   - reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x00000032);
125   - reg32_write(DDRC_FREQ1_DRAMTMG15(0), 0x00000000);
126   - reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x0036001b);
127   - reg32_write(DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1);
128   - reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0020d040);
129   - reg32_write(DDRC_FREQ1_DFITMG0(0), 0x03818200);
130   - reg32_write(DDRC_FREQ1_ODTCFG(0), 0x0a1a096c);
131   - reg32_write(DDRC_FREQ1_DFITMG2(0), 0x00000000);
132   - reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x00038014);
133   - reg32_write(DDRC_FREQ1_INIT3(0), 0x00840000);
134   - reg32_write(DDRC_FREQ1_INIT6(0), 0x0000004d);
135   - reg32_write(DDRC_FREQ1_INIT7(0), 0x0000004d);
136   - reg32_write(DDRC_FREQ1_INIT4(0), 0x00310000);
137   -}
138   -
139   -void lpddr4_25MHz_cfg_umctl2(void)
140   -{
141   - reg32_write(DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c);
142   - reg32_write(DDRC_FREQ2_DRAMTMG1(0), 0x00030410);
143   - reg32_write(DDRC_FREQ2_DRAMTMG2(0), 0x0305090c);
144   - reg32_write(DDRC_FREQ2_DRAMTMG3(0), 0x00505006);
145   - reg32_write(DDRC_FREQ2_DRAMTMG4(0), 0x05040305);
146   - reg32_write(DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504);
147   - reg32_write(DDRC_FREQ2_DRAMTMG6(0), 0x0a060004);
148   - reg32_write(DDRC_FREQ2_DRAMTMG7(0), 0x0000090e);
149   - reg32_write(DDRC_FREQ2_DRAMTMG14(0), 0x00000032);
150   - reg32_write(DDRC_FREQ2_DRAMTMG15(0), 0x00000000);
151   - reg32_write(DDRC_FREQ2_DRAMTMG17(0), 0x0036001b);
152   - reg32_write(DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1);
153   - reg32_write(DDRC_FREQ2_RFSHCTL0(0), 0x0020d040);
154   - reg32_write(DDRC_FREQ2_DFITMG0(0), 0x03818200);
155   - reg32_write(DDRC_FREQ2_ODTCFG(0), 0x0a1a096c);
156   - reg32_write(DDRC_FREQ2_DFITMG2(0), 0x00000000);
157   - reg32_write(DDRC_FREQ2_RFSHTMG(0), 0x0003800c);
158   - reg32_write(DDRC_FREQ2_INIT3(0), 0x00840000);
159   - reg32_write(DDRC_FREQ2_INIT6(0), 0x0000004d);
160   - reg32_write(DDRC_FREQ2_INIT7(0), 0x0000004d);
161   - reg32_write(DDRC_FREQ2_INIT4(0), 0x00310000);
162   -}
163   -
164   -int get_imx8m_baseboard_id(void);
165   -void ddr_cfg_phy(void);
166   -void ddr_init(void)
167   -{
168   - int board_id = 0;
169   -
170   - board_id = get_imx8m_baseboard_id();
171   - if ((board_id == ENTERPRISE_MICRON_1G) ||
172   - (board_id == ENTERPRISE_HYNIX_1G)) {
173   - /** Initialize DDR clock and DDRC registers **/
174   - reg32_write(0x3038a088,0x7070000);
175   - reg32_write(0x3038a084,0x4030000);
176   - reg32_write(0x303a00ec,0xffff);
177   - tmp=reg32_read(0x303a00f8);
178   - tmp |= 0x20;
179   - reg32_write(0x303a00f8,tmp);
180   - reg32_write(0x30391000,0x8f000000);
181   - reg32_write(0x30391004,0x8f000000);
182   - reg32_write(0x30360068,0xece580);
183   - tmp=reg32_read(0x30360060);
184   - tmp &= ~0x80;
185   - reg32_write(0x30360060,tmp);
186   - tmp=reg32_read(0x30360060);
187   - tmp |= 0x200;
188   - reg32_write(0x30360060,tmp);
189   - tmp=reg32_read(0x30360060);
190   - tmp &= ~0x20;
191   - reg32_write(0x30360060,tmp);
192   - tmp=reg32_read(0x30360060);
193   - tmp &= ~0x10;
194   - reg32_write(0x30360060,tmp);
195   - do{
196   - tmp=reg32_read(0x30360060);
197   - if(tmp&0x80000000) break;
198   - }while(1);
199   - reg32_write(0x30391000,0x8f000006);
200   - reg32_write(0x3d400304,0x1);
201   - reg32_write(0x3d400030,0x1);
202   - reg32_write(0x3d400000,0xa1080020);
203   - reg32_write(0x3d400028,0x0);
204   - reg32_write(0x3d400020,0x203);
205   - reg32_write(0x3d400024,0x186a000);
206   - reg32_write(0x3d400064,0x610090);
207   - reg32_write(0x3d4000d0,0xc003061c);
208   - reg32_write(0x3d4000d4,0x9e0000);
209   - reg32_write(0x3d4000dc,0xd4002d);
210   - reg32_write(0x3d4000e0,0x310008);
211   - reg32_write(0x3d4000e8,0x66004a);
212   - reg32_write(0x3d4000ec,0x16004a);
213   - reg32_write(0x3d400100,0x1a201b22);
214   - reg32_write(0x3d400104,0x60633);
215   - reg32_write(0x3d40010c,0xc0c000);
216   - reg32_write(0x3d400110,0xf04080f);
217   - reg32_write(0x3d400114,0x2040c0c);
218   - reg32_write(0x3d400118,0x1010007);
219   - reg32_write(0x3d40011c,0x401);
220   - reg32_write(0x3d400130,0x20600);
221   - reg32_write(0x3d400134,0xc100002);
222   - reg32_write(0x3d400138,0x96);
223   - reg32_write(0x3d400144,0xa00050);
224   - reg32_write(0x3d400180,0x3200018);
225   - reg32_write(0x3d400184,0x28061a8);
226   - reg32_write(0x3d400188,0x0);
227   - reg32_write(0x3d400190,0x497820a);
228   - reg32_write(0x3d400194,0x80303);
229   - reg32_write(0x3d4001a0,0xe0400018);
230   - reg32_write(0x3d4001a4,0xdf00e4);
231   - reg32_write(0x3d4001a8,0x80000000);
232   - reg32_write(0x3d4001b0,0x11);
233   - reg32_write(0x3d4001b4,0x170a);
234   - reg32_write(0x3d4001c0,0x1);
235   - reg32_write(0x3d4001c4,0x1);
236   - reg32_write(0x3d4000f4,0x639);
237   - reg32_write(0x3d400108,0x70e1214);
238   - reg32_write(0x3d400200,0x1f);
239   - reg32_write(0x3d40020c,0x0);
240   - reg32_write(0x3d400210,0x1f1f);
241   - reg32_write(0x3d400204,0x80808);
242   - reg32_write(0x3d400214,0x7070707);
243   - reg32_write(0x3d400218,0xf070707);
244   - reg32_write(0x3d402020,0x1);
245   - reg32_write(0x3d402024,0x518b00);
246   - reg32_write(0x3d402050,0x20d040);
247   - reg32_write(0x3d402064,0x14001f);
248   - reg32_write(0x3d4020dc,0x940009);
249   - reg32_write(0x3d4020e0,0x310000);
250   - reg32_write(0x3d4020e8,0x66004a);
251   - reg32_write(0x3d4020ec,0x16004a);
252   - reg32_write(0x3d402100,0xb070508);
253   - reg32_write(0x3d402104,0x3040b);
254   - reg32_write(0x3d402108,0x305090c);
255   - reg32_write(0x3d40210c,0x505000);
256   - reg32_write(0x3d402110,0x4040204);
257   - reg32_write(0x3d402114,0x2030303);
258   - reg32_write(0x3d402118,0x1010004);
259   - reg32_write(0x3d40211c,0x301);
260   - reg32_write(0x3d402130,0x20300);
261   - reg32_write(0x3d402134,0xa100002);
262   - reg32_write(0x3d402138,0x20);
263   - reg32_write(0x3d402144,0x220011);
264   - reg32_write(0x3d402180,0xa70006);
265   - reg32_write(0x3d402190,0x3858202);
266   - reg32_write(0x3d402194,0x80303);
267   - reg32_write(0x3d4021b4,0x502);
268   - reg32_write(0x3d400244,0x0);
269   - reg32_write(0x3d400250,0x29001505);
270   - reg32_write(0x3d400254,0x2c);
271   - reg32_write(0x3d40025c,0x5900575b);
272   - reg32_write(0x3d400264,0x9);
273   - reg32_write(0x3d40026c,0x2005574);
274   - reg32_write(0x3d400300,0x16);
275   - reg32_write(0x3d400304,0x0);
276   - reg32_write(0x3d40030c,0x0);
277   - reg32_write(0x3d400320,0x1);
278   - reg32_write(0x3d40036c,0x11);
279   - reg32_write(0x3d400400,0x111);
280   - reg32_write(0x3d400404,0x10f3);
281   - reg32_write(0x3d400408,0x72ff);
282   - reg32_write(0x3d400490,0x1);
283   - reg32_write(0x3d400494,0x1110d00);
284   - reg32_write(0x3d400498,0x620790);
285   - reg32_write(0x3d40049c,0x100001);
286   - reg32_write(0x3d4004a0,0x41f);
287   - reg32_write(0x30391000,0x8f000004);
288   - reg32_write(0x30391000,0x8f000000);
289   - reg32_write(0x3d400030,0xa8);
290   - do{
291   - tmp=reg32_read(0x3d400004);
292   - if(tmp&0x223) break;
293   - }while(1);
294   - reg32_write(0x3d400320,0x0);
295   - reg32_write(0x3d000000,0x1);
296   - reg32_write(0x3d4001b0,0x10);
297   - reg32_write(0x3c040280,0x0);
298   - reg32_write(0x3c040284,0x1);
299   - reg32_write(0x3c040288,0x2);
300   - reg32_write(0x3c04028c,0x3);
301   - reg32_write(0x3c040290,0x4);
302   - reg32_write(0x3c040294,0x5);
303   - reg32_write(0x3c040298,0x6);
304   - reg32_write(0x3c04029c,0x7);
305   - reg32_write(0x3c044280,0x0);
306   - reg32_write(0x3c044284,0x1);
307   - reg32_write(0x3c044288,0x2);
308   - reg32_write(0x3c04428c,0x3);
309   - reg32_write(0x3c044290,0x4);
310   - reg32_write(0x3c044294,0x5);
311   - reg32_write(0x3c044298,0x6);
312   - reg32_write(0x3c04429c,0x7);
313   - reg32_write(0x3c048280,0x0);
314   - reg32_write(0x3c048284,0x1);
315   - reg32_write(0x3c048288,0x2);
316   - reg32_write(0x3c04828c,0x3);
317   - reg32_write(0x3c048290,0x4);
318   - reg32_write(0x3c048294,0x5);
319   - reg32_write(0x3c048298,0x6);
320   - reg32_write(0x3c04829c,0x7);
321   - reg32_write(0x3c04c280,0x0);
322   - reg32_write(0x3c04c284,0x1);
323   - reg32_write(0x3c04c288,0x2);
324   - reg32_write(0x3c04c28c,0x3);
325   - reg32_write(0x3c04c290,0x4);
326   - reg32_write(0x3c04c294,0x5);
327   - reg32_write(0x3c04c298,0x6);
328   - reg32_write(0x3c04c29c,0x7);
329   -
330   - /* Configure DDR PHY's registers */
331   - ddr_cfg_phy();
332   -
333   - reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
334   - reg32_write(DDRC_SWCTL(0), 0x0000);
335   - /*
336   - * ------------------- 9 -------------------
337   - * Set DFIMISC.dfi_init_start to 1
338   - * -----------------------------------------
339   - */
340   - reg32_write(DDRC_DFIMISC(0), 0x00000030);
341   - reg32_write(DDRC_SWCTL(0), 0x0001);
342   -
343   - /* wait DFISTAT.dfi_init_complete to 1 */
344   - tmp_t = 0;
345   - while(tmp_t==0){
346   - tmp = reg32_read(DDRC_DFISTAT(0));
347   - tmp_t = tmp & 0x01;
348   - tmp = reg32_read(DDRC_MRSTAT(0));
349   - }
350   -
351   - reg32_write(DDRC_SWCTL(0), 0x0000);
352   -
353   - /* clear DFIMISC.dfi_init_complete_en */
354   - reg32_write(DDRC_DFIMISC(0), 0x00000010);
355   - reg32_write(DDRC_DFIMISC(0), 0x00000011);
356   - reg32_write(DDRC_PWRCTL(0), 0x00000088);
357   -
358   - tmp = reg32_read(DDRC_CRCPARSTAT(0));
359   - /*
360   - * set SWCTL.sw_done to enable quasi-dynamic register
361   - * programming outside reset.
362   - */
363   - reg32_write(DDRC_SWCTL(0), 0x00000001);
364   -
365   - /* wait SWSTAT.sw_done_ack to 1 */
366   - while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
367   - ;
368   -
369   - /* wait STAT.operating_mode([1:0] for ddr3) to normal state */
370   - while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1)
371   - ;
372   -
373   - reg32_write(DDRC_PWRCTL(0), 0x00000088);
374   - /* reg32_write(DDRC_PWRCTL(0), 0x018a); */
375   - tmp = reg32_read(DDRC_CRCPARSTAT(0));
376   -
377   - /* enable port 0 */
378   - reg32_write(DDRC_PCTRL_0(0), 0x00000001);
379   - /* enable DDR auto-refresh mode */
380   - tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1;
381   - reg32_write(DDRC_RFSHCTL3(0), tmp);
382   - } else {
383   - /* Default use 3G DDR */
384   - /* change the clock source of dram_apb_clk_root */
385   - reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
386   - reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16));
387   -
388   - /* disable the clock gating */
389   - reg32_write(0x303A00EC,0x0000ffff);
390   - reg32setbit(0x303A00F8,5);
391   - reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
392   -
393   - dram_pll_init(SSCG_PLL_OUT_800M);
394   -
395   - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
396   -
397   - /* Configure uMCTL2's registers */
398   - lpddr4_800MHz_cfg_umctl2();
399   -
400   - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
401   - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
402   -
403   - reg32_write(DDRC_DBG1(0), 0x00000000);
404   - tmp = reg32_read(DDRC_PWRCTL(0));
405   - reg32_write(DDRC_PWRCTL(0), 0x000000a8);
406   - /* reg32_write(DDRC_PWRCTL(0), 0x0000018a); */
407   - reg32_write(DDRC_SWCTL(0), 0x00000000);
408   - reg32_write(DDRC_DDR_SS_GPR0, 0x01);
409   - reg32_write(DDRC_DFIMISC(0), 0x00000010);
410   -
411   - /* Configure LPDDR4 PHY's registers */
412   - lpddr4_800M_cfg_phy();
413   -
414   - reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
415   - reg32_write(DDRC_SWCTL(0), 0x0000);
416   - /*
417   - * ------------------- 9 -------------------
418   - * Set DFIMISC.dfi_init_start to 1
419   - * -----------------------------------------
420   - */
421   - reg32_write(DDRC_DFIMISC(0), 0x00000030);
422   - reg32_write(DDRC_SWCTL(0), 0x0001);
423   -
424   - /* wait DFISTAT.dfi_init_complete to 1 */
425   - tmp_t = 0;
426   - while(tmp_t==0){
427   - tmp = reg32_read(DDRC_DFISTAT(0));
428   - tmp_t = tmp & 0x01;
429   - tmp = reg32_read(DDRC_MRSTAT(0));
430   - }
431   -
432   - reg32_write(DDRC_SWCTL(0), 0x0000);
433   -
434   - /* clear DFIMISC.dfi_init_complete_en */
435   - reg32_write(DDRC_DFIMISC(0), 0x00000010);
436   - reg32_write(DDRC_DFIMISC(0), 0x00000011);
437   - reg32_write(DDRC_PWRCTL(0), 0x00000088);
438   -
439   - tmp = reg32_read(DDRC_CRCPARSTAT(0));
440   - /*
441   - * set SWCTL.sw_done to enable quasi-dynamic register
442   - * programming outside reset.
443   - */
444   - reg32_write(DDRC_SWCTL(0), 0x00000001);
445   -
446   - /* wait SWSTAT.sw_done_ack to 1 */
447   - while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
448   - ;
449   -
450   - /* wait STAT.operating_mode([1:0] for ddr3) to normal state */
451   - while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1)
452   - ;
453   -
454   - reg32_write(DDRC_PWRCTL(0), 0x00000088);
455   - /* reg32_write(DDRC_PWRCTL(0), 0x018a); */
456   - tmp = reg32_read(DDRC_CRCPARSTAT(0));
457   -
458   - /* enable port 0 */
459   - reg32_write(DDRC_PCTRL_0(0), 0x00000001);
460   - tmp = reg32_read(DDRC_CRCPARSTAT(0));
461   - reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
462   -
463   - reg32_write(DDRC_SWCTL(0), 0x0);
464   - lpddr4_100MHz_cfg_umctl2();
465   - lpddr4_25MHz_cfg_umctl2();
466   - reg32_write(DDRC_SWCTL(0), 0x1);
467   -
468   - /* wait SWSTAT.sw_done_ack to 1 */
469   - while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
470   - ;
471   -
472   - reg32_write(DDRC_SWCTL(0), 0x0);
473   - }
474   -}
board/freescale/imx8mq_aiy/ddr/ddrphy_train.c
View file @ 63dbfc0
Changes suppressed. Click to show
1   -/*
2   - * Copyright 2017 NXP
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <common.h>
8   -#include <asm/io.h>
9   -#include <asm/arch/clock.h>
10   -#include <asm/arch/ddr.h>
11   -#include "ddr.h"
12   -
13   -extern void wait_ddrphy_training_complete(void);
14   -void ddr_cfg_phy(void) {
15   - unsigned int tmp, tmp_t;
16   -
17   - //Init DDRPHY register...
18   - reg32_write(0x3c080440,0x2);
19   - reg32_write(0x3c080444,0x3);
20   - reg32_write(0x3c080448,0x4);
21   - reg32_write(0x3c08044c,0x5);
22   - reg32_write(0x3c080450,0x0);
23   - reg32_write(0x3c080454,0x1);
24   - reg32_write(0x3c04017c,0x1ff);
25   - reg32_write(0x3c04057c,0x1ff);
26   - reg32_write(0x3c04417c,0x1ff);
27   - reg32_write(0x3c04457c,0x1ff);
28   - reg32_write(0x3c04817c,0x1ff);
29   - reg32_write(0x3c04857c,0x1ff);
30   - reg32_write(0x3c04c17c,0x1ff);
31   - reg32_write(0x3c04c57c,0x1ff);
32   - reg32_write(0x3c44017c,0x1ff);
33   - reg32_write(0x3c44057c,0x1ff);
34   - reg32_write(0x3c44417c,0x1ff);
35   - reg32_write(0x3c44457c,0x1ff);
36   - reg32_write(0x3c44817c,0x1ff);
37   - reg32_write(0x3c44857c,0x1ff);
38   - reg32_write(0x3c44c17c,0x1ff);
39   - reg32_write(0x3c44c57c,0x1ff);
40   - reg32_write(0x3c000154,0x1ff);
41   - reg32_write(0x3c004154,0x1ff);
42   - reg32_write(0x3c008154,0x1ff);
43   - reg32_write(0x3c00c154,0x1ff);
44   - reg32_write(0x3c010154,0x1ff);
45   - reg32_write(0x3c014154,0x1ff);
46   - reg32_write(0x3c018154,0x1ff);
47   - reg32_write(0x3c01c154,0x1ff);
48   - reg32_write(0x3c020154,0x1ff);
49   - reg32_write(0x3c024154,0x1ff);
50   - reg32_write(0x3c080314,0x19);
51   - reg32_write(0x3c480314,0x7);
52   - reg32_write(0x3c0800b8,0x2);
53   - reg32_write(0x3c4800b8,0x1);
54   - reg32_write(0x3c240810,0x0);
55   - reg32_write(0x3c640810,0x0);
56   - reg32_write(0x3c080090,0xab);
57   - reg32_write(0x3c0800e8,0x0);
58   - reg32_write(0x3c480090,0xab);
59   - reg32_write(0x3c0800e8,0x0);
60   - reg32_write(0x3c080158,0x3);
61   - reg32_write(0x3c480158,0xa);
62   - reg32_write(0x3c040134,0xe00);
63   - reg32_write(0x3c040534,0xe00);
64   - reg32_write(0x3c044134,0xe00);
65   - reg32_write(0x3c044534,0xe00);
66   - reg32_write(0x3c048134,0xe00);
67   - reg32_write(0x3c048534,0xe00);
68   - reg32_write(0x3c04c134,0xe00);
69   - reg32_write(0x3c04c534,0xe00);
70   - reg32_write(0x3c440134,0xe00);
71   - reg32_write(0x3c440534,0xe00);
72   - reg32_write(0x3c444134,0xe00);
73   - reg32_write(0x3c444534,0xe00);
74   - reg32_write(0x3c448134,0xe00);
75   - reg32_write(0x3c448534,0xe00);
76   - reg32_write(0x3c44c134,0xe00);
77   - reg32_write(0x3c44c534,0xe00);
78   - reg32_write(0x3c040124,0xfbe);
79   - reg32_write(0x3c040524,0xfbe);
80   - reg32_write(0x3c044124,0xfbe);
81   - reg32_write(0x3c044524,0xfbe);
82   - reg32_write(0x3c048124,0xfbe);
83   - reg32_write(0x3c048524,0xfbe);
84   - reg32_write(0x3c04c124,0xfbe);
85   - reg32_write(0x3c04c524,0xfbe);
86   - reg32_write(0x3c440124,0xfbe);
87   - reg32_write(0x3c440524,0xfbe);
88   - reg32_write(0x3c444124,0xfbe);
89   - reg32_write(0x3c444524,0xfbe);
90   - reg32_write(0x3c448124,0xfbe);
91   - reg32_write(0x3c448524,0xfbe);
92   - reg32_write(0x3c44c124,0xfbe);
93   - reg32_write(0x3c44c524,0xfbe);
94   - reg32_write(0x3c00010c,0x63);
95   - reg32_write(0x3c00410c,0x63);
96   - reg32_write(0x3c00810c,0x63);
97   - reg32_write(0x3c00c10c,0x63);
98   - reg32_write(0x3c01010c,0x63);
99   - reg32_write(0x3c01410c,0x63);
100   - reg32_write(0x3c01810c,0x63);
101   - reg32_write(0x3c01c10c,0x63);
102   - reg32_write(0x3c02010c,0x63);
103   - reg32_write(0x3c02410c,0x63);
104   - reg32_write(0x3c080060,0x3);
105   - reg32_write(0x3c0801d4,0x4);
106   - reg32_write(0x3c080140,0x0);
107   - reg32_write(0x3c080020,0x320);
108   - reg32_write(0x3c480020,0xa7);
109   - reg32_write(0x3c080220,0x9);
110   - reg32_write(0x3c0802c8,0xdc);
111   - reg32_write(0x3c04010c,0x5a1);
112   - reg32_write(0x3c04050c,0x5a1);
113   - reg32_write(0x3c04410c,0x5a1);
114   - reg32_write(0x3c04450c,0x5a1);
115   - reg32_write(0x3c04810c,0x5a1);
116   - reg32_write(0x3c04850c,0x5a1);
117   - reg32_write(0x3c04c10c,0x5a1);
118   - reg32_write(0x3c04c50c,0x5a1);
119   - reg32_write(0x3c4802c8,0xdc);
120   - reg32_write(0x3c44010c,0x5a1);
121   - reg32_write(0x3c44050c,0x5a1);
122   - reg32_write(0x3c44410c,0x5a1);
123   - reg32_write(0x3c44450c,0x5a1);
124   - reg32_write(0x3c44810c,0x5a1);
125   - reg32_write(0x3c44850c,0x5a1);
126   - reg32_write(0x3c44c10c,0x5a1);
127   - reg32_write(0x3c44c50c,0x5a1);
128   - reg32_write(0x3c0803e8,0x1);
129   - reg32_write(0x3c4803e8,0x1);
130   - reg32_write(0x3c080064,0x1);
131   - reg32_write(0x3c480064,0x1);
132   - reg32_write(0x3c0803c0,0x0);
133   - reg32_write(0x3c0803c4,0x0);
134   - reg32_write(0x3c0803c8,0x4444);
135   - reg32_write(0x3c0803cc,0x8888);
136   - reg32_write(0x3c0803d0,0x5555);
137   - reg32_write(0x3c0803d4,0x0);
138   - reg32_write(0x3c0803d8,0x0);
139   - reg32_write(0x3c0803dc,0xf000);
140   - reg32_write(0x3c080094,0x0);
141   - reg32_write(0x3c0800b4,0x0);
142   - reg32_write(0x3c4800b4,0x0);
143   - reg32_write(0x3c080180,0x2);
144   -
145   - //enable APB bus to access DDRPHY RAM
146   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
147   - //load the 1D training image
148   - ddr_load_train_code(FW_1D_IMAGE);
149   -
150   - //configure DDRPHY-FW DMEM structure @clock0...
151   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
152   -
153   - //set the PHY input clock to the desired frequency for pstate 0
154   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80);
155   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
156   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11);
157   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x131f);
158   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
159   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
160   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100);
161   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x110);
162   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4);
163   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
164   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4a66);
165   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4a08);
166   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16);
167   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4);
168   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
169   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4a66);
170   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4a08);
171   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16);
172   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
173   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x1);
174   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400);
175   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d);
176   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600);
177   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84a);
178   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4a);
179   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600);
180   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400);
181   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d);
182   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600);
183   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84a);
184   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4a);
185   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600);
186   -
187   - //disable APB bus to access DDRPHY RAM
188   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
189   - //Reset MPU and run
190   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
191   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
192   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
193   - wait_ddrphy_training_complete();
194   -
195   - //configure DDRPHY-FW DMEM structure @clock1...
196   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
197   -
198   - //set the PHY input clock to the desired frequency for pstate 1
199   - reg32_write(0x3038a088,0x7070000);
200   - reg32_write(0x3038a084,0x4030000);
201   - reg32_write(0x303a00ec,0xffff);
202   - tmp=reg32_read(0x303a00f8);
203   - tmp |= 0x20;
204   - reg32_write(0x303a00f8,tmp);
205   - reg32_write(0x30360068,0xf5a406);
206   - tmp=reg32_read(0x30360060);
207   - tmp &= ~0x80;
208   - reg32_write(0x30360060,tmp);
209   - tmp=reg32_read(0x30360060);
210   - tmp |= 0x200;
211   - reg32_write(0x30360060,tmp);
212   - tmp=reg32_read(0x30360060);
213   - tmp &= ~0x20;
214   - reg32_write(0x30360060,tmp);
215   - tmp=reg32_read(0x30360060);
216   - tmp &= ~0x10;
217   - reg32_write(0x30360060,tmp);
218   - do{
219   - tmp=reg32_read(0x30360060);
220   - if(tmp&0x80000000) break;
221   - }while(1);
222   - reg32_write(0x30389808,0x1000000);
223   -
224   - //enable APB bus to access DDRPHY RAM
225   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
226   -
227   - reg32_write(0x3c150008,0x1);
228   - reg32_write(0x3c15000c,0x29c);
229   - reg32_write(0x3c150020,0x121f);
230   - reg32_write(0x3c150064,0x994);
231   - reg32_write(0x3c150068,0x31);
232   - reg32_write(0x3c15006c,0x4d46);
233   - reg32_write(0x3c150070,0x4d08);
234   - reg32_write(0x3c150074,0x0);
235   - reg32_write(0x3c150078,0x15);
236   - reg32_write(0x3c15007c,0x994);
237   - reg32_write(0x3c150080,0x31);
238   - reg32_write(0x3c150084,0x4d46);
239   - reg32_write(0x3c150088,0x4d08);
240   - reg32_write(0x3c15008c,0x0);
241   - reg32_write(0x3c150090,0x15);
242   - reg32_write(0x3c1500c8,0x9400);
243   - reg32_write(0x3c1500cc,0x3109);
244   - reg32_write(0x3c1500d0,0x4600);
245   - reg32_write(0x3c1500d4,0x84d);
246   - reg32_write(0x3c1500d8,0x4d);
247   - reg32_write(0x3c1500dc,0x1500);
248   - reg32_write(0x3c1500e0,0x9400);
249   - reg32_write(0x3c1500e4,0x3109);
250   - reg32_write(0x3c1500e8,0x4600);
251   - reg32_write(0x3c1500ec,0x84d);
252   - reg32_write(0x3c1500f0,0x4d);
253   - reg32_write(0x3c1500f4,0x1500);
254   - reg32_write(0x3c1500f8,0x0);
255   -
256   - //disable APB bus to access DDRPHY RAM
257   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
258   - //Reset MPU and run
259   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
260   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
261   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
262   - wait_ddrphy_training_complete();
263   -
264   - //set the PHY input clock to the desired frequency for pstate 0
265   - reg32_write(0x3038a088,0x7070000);
266   - reg32_write(0x3038a084,0x4030000);
267   - reg32_write(0x303a00ec,0xffff);
268   - tmp=reg32_read(0x303a00f8);
269   - tmp |= 0x20;
270   - reg32_write(0x303a00f8,tmp);
271   - reg32_write(0x30360068,0xece580);
272   - tmp=reg32_read(0x30360060);
273   - tmp &= ~0x80;
274   - reg32_write(0x30360060,tmp);
275   - tmp=reg32_read(0x30360060);
276   - tmp |= 0x200;
277   - reg32_write(0x30360060,tmp);
278   - tmp=reg32_read(0x30360060);
279   - tmp &= ~0x20;
280   - reg32_write(0x30360060,tmp);
281   - tmp=reg32_read(0x30360060);
282   - tmp &= ~0x10;
283   - reg32_write(0x30360060,tmp);
284   - do{
285   - tmp=reg32_read(0x30360060);
286   - if(tmp&0x80000000) break;
287   - }while(1);
288   - reg32_write(0x30389808,0x1000000);
289   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
290   -
291   -
292   - //enable APB bus to access DDRPHY RAM
293   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
294   - //load the 2D training image
295   - ddr_load_train_code(FW_2D_IMAGE);
296   -
297   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80);
298   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11);
299   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x61);
300   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
301   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
302   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x100);
303   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x1f7f);
304   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x110);
305   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4);
306   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
307   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4a66);
308   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4a08);
309   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16);
310   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4);
311   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
312   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4a66);
313   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4a08);
314   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16);
315   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
316   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x1);
317   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400);
318   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d);
319   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600);
320   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84a);
321   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4a);
322   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600);
323   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400);
324   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d);
325   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600);
326   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84a);
327   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4a);
328   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600);
329   -
330   - //disable APB bus to access DDRPHY RAM
331   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
332   - //Reset MPU and run
333   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
334   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
335   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
336   - wait_ddrphy_training_complete();
337   -
338   - //Halt MPU
339   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
340   - //enable APB bus to access DDRPHY RAM
341   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
342   -
343   - //Load firmware PIE image
344   - reg32_write(0x3c240000,0x10);
345   - reg32_write(0x3c240004,0x400);
346   - reg32_write(0x3c240008,0x10e);
347   - reg32_write(0x3c24000c,0x0);
348   - reg32_write(0x3c240010,0x0);
349   - reg32_write(0x3c240014,0x8);
350   - reg32_write(0x3c2400a4,0xb);
351   - reg32_write(0x3c2400a8,0x480);
352   - reg32_write(0x3c2400ac,0x109);
353   - reg32_write(0x3c2400b0,0x8);
354   - reg32_write(0x3c2400b4,0x448);
355   - reg32_write(0x3c2400b8,0x139);
356   - reg32_write(0x3c2400bc,0x8);
357   - reg32_write(0x3c2400c0,0x478);
358   - reg32_write(0x3c2400c4,0x109);
359   - reg32_write(0x3c2400c8,0x0);
360   - reg32_write(0x3c2400cc,0xe8);
361   - reg32_write(0x3c2400d0,0x109);
362   - reg32_write(0x3c2400d4,0x2);
363   - reg32_write(0x3c2400d8,0x10);
364   - reg32_write(0x3c2400dc,0x139);
365   - reg32_write(0x3c2400e0,0xf);
366   - reg32_write(0x3c2400e4,0x7c0);
367   - reg32_write(0x3c2400e8,0x139);
368   - reg32_write(0x3c2400ec,0x44);
369   - reg32_write(0x3c2400f0,0x630);
370   - reg32_write(0x3c2400f4,0x159);
371   - reg32_write(0x3c2400f8,0x14f);
372   - reg32_write(0x3c2400fc,0x630);
373   - reg32_write(0x3c240100,0x159);
374   - reg32_write(0x3c240104,0x47);
375   - reg32_write(0x3c240108,0x630);
376   - reg32_write(0x3c24010c,0x149);
377   - reg32_write(0x3c240110,0x4f);
378   - reg32_write(0x3c240114,0x630);
379   - reg32_write(0x3c240118,0x179);
380   - reg32_write(0x3c24011c,0x8);
381   - reg32_write(0x3c240120,0xe0);
382   - reg32_write(0x3c240124,0x109);
383   - reg32_write(0x3c240128,0x0);
384   - reg32_write(0x3c24012c,0x7c8);
385   - reg32_write(0x3c240130,0x109);
386   - reg32_write(0x3c240134,0x0);
387   - reg32_write(0x3c240138,0x1);
388   - reg32_write(0x3c24013c,0x8);
389   - reg32_write(0x3c240140,0x0);
390   - reg32_write(0x3c240144,0x45a);
391   - reg32_write(0x3c240148,0x9);
392   - reg32_write(0x3c24014c,0x0);
393   - reg32_write(0x3c240150,0x448);
394   - reg32_write(0x3c240154,0x109);
395   - reg32_write(0x3c240158,0x40);
396   - reg32_write(0x3c24015c,0x630);
397   - reg32_write(0x3c240160,0x179);
398   - reg32_write(0x3c240164,0x1);
399   - reg32_write(0x3c240168,0x618);
400   - reg32_write(0x3c24016c,0x109);
401   - reg32_write(0x3c240170,0x40c0);
402   - reg32_write(0x3c240174,0x630);
403   - reg32_write(0x3c240178,0x149);
404   - reg32_write(0x3c24017c,0x8);
405   - reg32_write(0x3c240180,0x4);
406   - reg32_write(0x3c240184,0x48);
407   - reg32_write(0x3c240188,0x4040);
408   - reg32_write(0x3c24018c,0x630);
409   - reg32_write(0x3c240190,0x149);
410   - reg32_write(0x3c240194,0x0);
411   - reg32_write(0x3c240198,0x4);
412   - reg32_write(0x3c24019c,0x48);
413   - reg32_write(0x3c2401a0,0x40);
414   - reg32_write(0x3c2401a4,0x630);
415   - reg32_write(0x3c2401a8,0x149);
416   - reg32_write(0x3c2401ac,0x10);
417   - reg32_write(0x3c2401b0,0x4);
418   - reg32_write(0x3c2401b4,0x18);
419   - reg32_write(0x3c2401b8,0x0);
420   - reg32_write(0x3c2401bc,0x4);
421   - reg32_write(0x3c2401c0,0x78);
422   - reg32_write(0x3c2401c4,0x549);
423   - reg32_write(0x3c2401c8,0x630);
424   - reg32_write(0x3c2401cc,0x159);
425   - reg32_write(0x3c2401d0,0xd49);
426   - reg32_write(0x3c2401d4,0x630);
427   - reg32_write(0x3c2401d8,0x159);
428   - reg32_write(0x3c2401dc,0x94a);
429   - reg32_write(0x3c2401e0,0x630);
430   - reg32_write(0x3c2401e4,0x159);
431   - reg32_write(0x3c2401e8,0x441);
432   - reg32_write(0x3c2401ec,0x630);
433   - reg32_write(0x3c2401f0,0x149);
434   - reg32_write(0x3c2401f4,0x42);
435   - reg32_write(0x3c2401f8,0x630);
436   - reg32_write(0x3c2401fc,0x149);
437   - reg32_write(0x3c240200,0x1);
438   - reg32_write(0x3c240204,0x630);
439   - reg32_write(0x3c240208,0x149);
440   - reg32_write(0x3c24020c,0x0);
441   - reg32_write(0x3c240210,0xe0);
442   - reg32_write(0x3c240214,0x109);
443   - reg32_write(0x3c240218,0xa);
444   - reg32_write(0x3c24021c,0x10);
445   - reg32_write(0x3c240220,0x109);
446   - reg32_write(0x3c240224,0x9);
447   - reg32_write(0x3c240228,0x3c0);
448   - reg32_write(0x3c24022c,0x149);
449   - reg32_write(0x3c240230,0x9);
450   - reg32_write(0x3c240234,0x3c0);
451   - reg32_write(0x3c240238,0x159);
452   - reg32_write(0x3c24023c,0x18);
453   - reg32_write(0x3c240240,0x10);
454   - reg32_write(0x3c240244,0x109);
455   - reg32_write(0x3c240248,0x0);
456   - reg32_write(0x3c24024c,0x3c0);
457   - reg32_write(0x3c240250,0x109);
458   - reg32_write(0x3c240254,0x18);
459   - reg32_write(0x3c240258,0x4);
460   - reg32_write(0x3c24025c,0x48);
461   - reg32_write(0x3c240260,0x18);
462   - reg32_write(0x3c240264,0x4);
463   - reg32_write(0x3c240268,0x58);
464   - reg32_write(0x3c24026c,0xa);
465   - reg32_write(0x3c240270,0x10);
466   - reg32_write(0x3c240274,0x109);
467   - reg32_write(0x3c240278,0x2);
468   - reg32_write(0x3c24027c,0x10);
469   - reg32_write(0x3c240280,0x109);
470   - reg32_write(0x3c240284,0x5);
471   - reg32_write(0x3c240288,0x7c0);
472   - reg32_write(0x3c24028c,0x109);
473   - reg32_write(0x3c240290,0x10);
474   - reg32_write(0x3c240294,0x10);
475   - reg32_write(0x3c240298,0x109);
476   - reg32_write(0x3c100000,0x811);
477   - reg32_write(0x3c100080,0x880);
478   - reg32_write(0x3c100100,0x0);
479   - reg32_write(0x3c100180,0x0);
480   - reg32_write(0x3c100004,0x4008);
481   - reg32_write(0x3c100084,0x83);
482   - reg32_write(0x3c100104,0x4f);
483   - reg32_write(0x3c100184,0x0);
484   - reg32_write(0x3c100008,0x4040);
485   - reg32_write(0x3c100088,0x83);
486   - reg32_write(0x3c100108,0x51);
487   - reg32_write(0x3c100188,0x0);
488   - reg32_write(0x3c10000c,0x811);
489   - reg32_write(0x3c10008c,0x880);
490   - reg32_write(0x3c10010c,0x0);
491   - reg32_write(0x3c10018c,0x0);
492   - reg32_write(0x3c100010,0x720);
493   - reg32_write(0x3c100090,0xf);
494   - reg32_write(0x3c100110,0x1740);
495   - reg32_write(0x3c100190,0x0);
496   - reg32_write(0x3c100014,0x16);
497   - reg32_write(0x3c100094,0x83);
498   - reg32_write(0x3c100114,0x4b);
499   - reg32_write(0x3c100194,0x0);
500   - reg32_write(0x3c100018,0x716);
501   - reg32_write(0x3c100098,0xf);
502   - reg32_write(0x3c100118,0x2001);
503   - reg32_write(0x3c100198,0x0);
504   - reg32_write(0x3c10001c,0x716);
505   - reg32_write(0x3c10009c,0xf);
506   - reg32_write(0x3c10011c,0x2800);
507   - reg32_write(0x3c10019c,0x0);
508   - reg32_write(0x3c100020,0x716);
509   - reg32_write(0x3c1000a0,0xf);
510   - reg32_write(0x3c100120,0xf00);
511   - reg32_write(0x3c1001a0,0x0);
512   - reg32_write(0x3c100024,0x720);
513   - reg32_write(0x3c1000a4,0xf);
514   - reg32_write(0x3c100124,0x1400);
515   - reg32_write(0x3c1001a4,0x0);
516   - reg32_write(0x3c100028,0xe08);
517   - reg32_write(0x3c1000a8,0xc15);
518   - reg32_write(0x3c100128,0x0);
519   - reg32_write(0x3c1001a8,0x0);
520   - reg32_write(0x3c10002c,0x623);
521   - reg32_write(0x3c1000ac,0x15);
522   - reg32_write(0x3c10012c,0x0);
523   - reg32_write(0x3c1001ac,0x0);
524   - reg32_write(0x3c100030,0x4028);
525   - reg32_write(0x3c1000b0,0x80);
526   - reg32_write(0x3c100130,0x0);
527   - reg32_write(0x3c1001b0,0x0);
528   - reg32_write(0x3c100034,0xe08);
529   - reg32_write(0x3c1000b4,0xc1a);
530   - reg32_write(0x3c100134,0x0);
531   - reg32_write(0x3c1001b4,0x0);
532   - reg32_write(0x3c100038,0x623);
533   - reg32_write(0x3c1000b8,0x1a);
534   - reg32_write(0x3c100138,0x0);
535   - reg32_write(0x3c1001b8,0x0);
536   - reg32_write(0x3c10003c,0x4040);
537   - reg32_write(0x3c1000bc,0x80);
538   - reg32_write(0x3c10013c,0x0);
539   - reg32_write(0x3c1001bc,0x0);
540   - reg32_write(0x3c100040,0x2604);
541   - reg32_write(0x3c1000c0,0x15);
542   - reg32_write(0x3c100140,0x0);
543   - reg32_write(0x3c1001c0,0x0);
544   - reg32_write(0x3c100044,0x708);
545   - reg32_write(0x3c1000c4,0x5);
546   - reg32_write(0x3c100144,0x0);
547   - reg32_write(0x3c1001c4,0x2002);
548   - reg32_write(0x3c100048,0x8);
549   - reg32_write(0x3c1000c8,0x80);
550   - reg32_write(0x3c100148,0x0);
551   - reg32_write(0x3c1001c8,0x0);
552   - reg32_write(0x3c10004c,0x2604);
553   - reg32_write(0x3c1000cc,0x1a);
554   - reg32_write(0x3c10014c,0x0);
555   - reg32_write(0x3c1001cc,0x0);
556   - reg32_write(0x3c100050,0x708);
557   - reg32_write(0x3c1000d0,0xa);
558   - reg32_write(0x3c100150,0x0);
559   - reg32_write(0x3c1001d0,0x2002);
560   - reg32_write(0x3c100054,0x4040);
561   - reg32_write(0x3c1000d4,0x80);
562   - reg32_write(0x3c100154,0x0);
563   - reg32_write(0x3c1001d4,0x0);
564   - reg32_write(0x3c100058,0x60a);
565   - reg32_write(0x3c1000d8,0x15);
566   - reg32_write(0x3c100158,0x1200);
567   - reg32_write(0x3c1001d8,0x0);
568   - reg32_write(0x3c10005c,0x61a);
569   - reg32_write(0x3c1000dc,0x15);
570   - reg32_write(0x3c10015c,0x1300);
571   - reg32_write(0x3c1001dc,0x0);
572   - reg32_write(0x3c100060,0x60a);
573   - reg32_write(0x3c1000e0,0x1a);
574   - reg32_write(0x3c100160,0x1200);
575   - reg32_write(0x3c1001e0,0x0);
576   - reg32_write(0x3c100064,0x642);
577   - reg32_write(0x3c1000e4,0x1a);
578   - reg32_write(0x3c100164,0x1300);
579   - reg32_write(0x3c1001e4,0x0);
580   - reg32_write(0x3c100068,0x4808);
581   - reg32_write(0x3c1000e8,0x880);
582   - reg32_write(0x3c100168,0x0);
583   - reg32_write(0x3c1001e8,0x0);
584   - reg32_write(0x3c24029c,0x0);
585   - reg32_write(0x3c2402a0,0x790);
586   - reg32_write(0x3c2402a4,0x11a);
587   - reg32_write(0x3c2402a8,0x8);
588   - reg32_write(0x3c2402ac,0x7aa);
589   - reg32_write(0x3c2402b0,0x2a);
590   - reg32_write(0x3c2402b4,0x10);
591   - reg32_write(0x3c2402b8,0x7b2);
592   - reg32_write(0x3c2402bc,0x2a);
593   - reg32_write(0x3c2402c0,0x0);
594   - reg32_write(0x3c2402c4,0x7c8);
595   - reg32_write(0x3c2402c8,0x109);
596   - reg32_write(0x3c2402cc,0x10);
597   - reg32_write(0x3c2402d0,0x2a8);
598   - reg32_write(0x3c2402d4,0x129);
599   - reg32_write(0x3c2402d8,0x8);
600   - reg32_write(0x3c2402dc,0x370);
601   - reg32_write(0x3c2402e0,0x129);
602   - reg32_write(0x3c2402e4,0xa);
603   - reg32_write(0x3c2402e8,0x3c8);
604   - reg32_write(0x3c2402ec,0x1a9);
605   - reg32_write(0x3c2402f0,0xc);
606   - reg32_write(0x3c2402f4,0x408);
607   - reg32_write(0x3c2402f8,0x199);
608   - reg32_write(0x3c2402fc,0x14);
609   - reg32_write(0x3c240300,0x790);
610   - reg32_write(0x3c240304,0x11a);
611   - reg32_write(0x3c240308,0x8);
612   - reg32_write(0x3c24030c,0x4);
613   - reg32_write(0x3c240310,0x18);
614   - reg32_write(0x3c240314,0xe);
615   - reg32_write(0x3c240318,0x408);
616   - reg32_write(0x3c24031c,0x199);
617   - reg32_write(0x3c240320,0x8);
618   - reg32_write(0x3c240324,0x8568);
619   - reg32_write(0x3c240328,0x108);
620   - reg32_write(0x3c24032c,0x18);
621   - reg32_write(0x3c240330,0x790);
622   - reg32_write(0x3c240334,0x16a);
623   - reg32_write(0x3c240338,0x8);
624   - reg32_write(0x3c24033c,0x1d8);
625   - reg32_write(0x3c240340,0x169);
626   - reg32_write(0x3c240344,0x10);
627   - reg32_write(0x3c240348,0x8558);
628   - reg32_write(0x3c24034c,0x168);
629   - reg32_write(0x3c240350,0x70);
630   - reg32_write(0x3c240354,0x788);
631   - reg32_write(0x3c240358,0x16a);
632   - reg32_write(0x3c24035c,0x1ff8);
633   - reg32_write(0x3c240360,0x85a8);
634   - reg32_write(0x3c240364,0x1e8);
635   - reg32_write(0x3c240368,0x50);
636   - reg32_write(0x3c24036c,0x798);
637   - reg32_write(0x3c240370,0x16a);
638   - reg32_write(0x3c240374,0x60);
639   - reg32_write(0x3c240378,0x7a0);
640   - reg32_write(0x3c24037c,0x16a);
641   - reg32_write(0x3c240380,0x8);
642   - reg32_write(0x3c240384,0x8310);
643   - reg32_write(0x3c240388,0x168);
644   - reg32_write(0x3c24038c,0x8);
645   - reg32_write(0x3c240390,0xa310);
646   - reg32_write(0x3c240394,0x168);
647   - reg32_write(0x3c240398,0xa);
648   - reg32_write(0x3c24039c,0x408);
649   - reg32_write(0x3c2403a0,0x169);
650   - reg32_write(0x3c2403a4,0x6e);
651   - reg32_write(0x3c2403a8,0x0);
652   - reg32_write(0x3c2403ac,0x68);
653   - reg32_write(0x3c2403b0,0x0);
654   - reg32_write(0x3c2403b4,0x408);
655   - reg32_write(0x3c2403b8,0x169);
656   - reg32_write(0x3c2403bc,0x0);
657   - reg32_write(0x3c2403c0,0x8310);
658   - reg32_write(0x3c2403c4,0x168);
659   - reg32_write(0x3c2403c8,0x0);
660   - reg32_write(0x3c2403cc,0xa310);
661   - reg32_write(0x3c2403d0,0x168);
662   - reg32_write(0x3c2403d4,0x1ff8);
663   - reg32_write(0x3c2403d8,0x85a8);
664   - reg32_write(0x3c2403dc,0x1e8);
665   - reg32_write(0x3c2403e0,0x68);
666   - reg32_write(0x3c2403e4,0x798);
667   - reg32_write(0x3c2403e8,0x16a);
668   - reg32_write(0x3c2403ec,0x78);
669   - reg32_write(0x3c2403f0,0x7a0);
670   - reg32_write(0x3c2403f4,0x16a);
671   - reg32_write(0x3c2403f8,0x68);
672   - reg32_write(0x3c2403fc,0x790);
673   - reg32_write(0x3c240400,0x16a);
674   - reg32_write(0x3c240404,0x8);
675   - reg32_write(0x3c240408,0x8b10);
676   - reg32_write(0x3c24040c,0x168);
677   - reg32_write(0x3c240410,0x8);
678   - reg32_write(0x3c240414,0xab10);
679   - reg32_write(0x3c240418,0x168);
680   - reg32_write(0x3c24041c,0xa);
681   - reg32_write(0x3c240420,0x408);
682   - reg32_write(0x3c240424,0x169);
683   - reg32_write(0x3c240428,0x58);
684   - reg32_write(0x3c24042c,0x0);
685   - reg32_write(0x3c240430,0x68);
686   - reg32_write(0x3c240434,0x0);
687   - reg32_write(0x3c240438,0x408);
688   - reg32_write(0x3c24043c,0x169);
689   - reg32_write(0x3c240440,0x0);
690   - reg32_write(0x3c240444,0x8b10);
691   - reg32_write(0x3c240448,0x168);
692   - reg32_write(0x3c24044c,0x0);
693   - reg32_write(0x3c240450,0xab10);
694   - reg32_write(0x3c240454,0x168);
695   - reg32_write(0x3c240458,0x0);
696   - reg32_write(0x3c24045c,0x1d8);
697   - reg32_write(0x3c240460,0x169);
698   - reg32_write(0x3c240464,0x80);
699   - reg32_write(0x3c240468,0x790);
700   - reg32_write(0x3c24046c,0x16a);
701   - reg32_write(0x3c240470,0x18);
702   - reg32_write(0x3c240474,0x7aa);
703   - reg32_write(0x3c240478,0x6a);
704   - reg32_write(0x3c24047c,0xa);
705   - reg32_write(0x3c240480,0x0);
706   - reg32_write(0x3c240484,0x1e9);
707   - reg32_write(0x3c240488,0x8);
708   - reg32_write(0x3c24048c,0x8080);
709   - reg32_write(0x3c240490,0x108);
710   - reg32_write(0x3c240494,0xf);
711   - reg32_write(0x3c240498,0x408);
712   - reg32_write(0x3c24049c,0x169);
713   - reg32_write(0x3c2404a0,0xc);
714   - reg32_write(0x3c2404a4,0x0);
715   - reg32_write(0x3c2404a8,0x68);
716   - reg32_write(0x3c2404ac,0x9);
717   - reg32_write(0x3c2404b0,0x0);
718   - reg32_write(0x3c2404b4,0x1a9);
719   - reg32_write(0x3c2404b8,0x0);
720   - reg32_write(0x3c2404bc,0x408);
721   - reg32_write(0x3c2404c0,0x169);
722   - reg32_write(0x3c2404c4,0x0);
723   - reg32_write(0x3c2404c8,0x8080);
724   - reg32_write(0x3c2404cc,0x108);
725   - reg32_write(0x3c2404d0,0x8);
726   - reg32_write(0x3c2404d4,0x7aa);
727   - reg32_write(0x3c2404d8,0x6a);
728   - reg32_write(0x3c2404dc,0x0);
729   - reg32_write(0x3c2404e0,0x8568);
730   - reg32_write(0x3c2404e4,0x108);
731   - reg32_write(0x3c2404e8,0xb7);
732   - reg32_write(0x3c2404ec,0x790);
733   - reg32_write(0x3c2404f0,0x16a);
734   - reg32_write(0x3c2404f4,0x1f);
735   - reg32_write(0x3c2404f8,0x0);
736   - reg32_write(0x3c2404fc,0x68);
737   - reg32_write(0x3c240500,0x8);
738   - reg32_write(0x3c240504,0x8558);
739   - reg32_write(0x3c240508,0x168);
740   - reg32_write(0x3c24050c,0xf);
741   - reg32_write(0x3c240510,0x408);
742   - reg32_write(0x3c240514,0x169);
743   - reg32_write(0x3c240518,0xc);
744   - reg32_write(0x3c24051c,0x0);
745   - reg32_write(0x3c240520,0x68);
746   - reg32_write(0x3c240524,0x0);
747   - reg32_write(0x3c240528,0x408);
748   - reg32_write(0x3c24052c,0x169);
749   - reg32_write(0x3c240530,0x0);
750   - reg32_write(0x3c240534,0x8558);
751   - reg32_write(0x3c240538,0x168);
752   - reg32_write(0x3c24053c,0x8);
753   - reg32_write(0x3c240540,0x3c8);
754   - reg32_write(0x3c240544,0x1a9);
755   - reg32_write(0x3c240548,0x3);
756   - reg32_write(0x3c24054c,0x370);
757   - reg32_write(0x3c240550,0x129);
758   - reg32_write(0x3c240554,0x20);
759   - reg32_write(0x3c240558,0x2aa);
760   - reg32_write(0x3c24055c,0x9);
761   - reg32_write(0x3c240560,0x0);
762   - reg32_write(0x3c240564,0x400);
763   - reg32_write(0x3c240568,0x10e);
764   - reg32_write(0x3c24056c,0x8);
765   - reg32_write(0x3c240570,0xe8);
766   - reg32_write(0x3c240574,0x109);
767   - reg32_write(0x3c240578,0x0);
768   - reg32_write(0x3c24057c,0x8140);
769   - reg32_write(0x3c240580,0x10c);
770   - reg32_write(0x3c240584,0x10);
771   - reg32_write(0x3c240588,0x8138);
772   - reg32_write(0x3c24058c,0x10c);
773   - reg32_write(0x3c240590,0x8);
774   - reg32_write(0x3c240594,0x7c8);
775   - reg32_write(0x3c240598,0x101);
776   - reg32_write(0x3c24059c,0x8);
777   - reg32_write(0x3c2405a0,0x0);
778   - reg32_write(0x3c2405a4,0x8);
779   - reg32_write(0x3c2405a8,0x8);
780   - reg32_write(0x3c2405ac,0x448);
781   - reg32_write(0x3c2405b0,0x109);
782   - reg32_write(0x3c2405b4,0xf);
783   - reg32_write(0x3c2405b8,0x7c0);
784   - reg32_write(0x3c2405bc,0x109);
785   - reg32_write(0x3c2405c0,0x0);
786   - reg32_write(0x3c2405c4,0xe8);
787   - reg32_write(0x3c2405c8,0x109);
788   - reg32_write(0x3c2405cc,0x47);
789   - reg32_write(0x3c2405d0,0x630);
790   - reg32_write(0x3c2405d4,0x109);
791   - reg32_write(0x3c2405d8,0x8);
792   - reg32_write(0x3c2405dc,0x618);
793   - reg32_write(0x3c2405e0,0x109);
794   - reg32_write(0x3c2405e4,0x8);
795   - reg32_write(0x3c2405e8,0xe0);
796   - reg32_write(0x3c2405ec,0x109);
797   - reg32_write(0x3c2405f0,0x0);
798   - reg32_write(0x3c2405f4,0x7c8);
799   - reg32_write(0x3c2405f8,0x109);
800   - reg32_write(0x3c2405fc,0x8);
801   - reg32_write(0x3c240600,0x8140);
802   - reg32_write(0x3c240604,0x10c);
803   - reg32_write(0x3c240608,0x0);
804   - reg32_write(0x3c24060c,0x1);
805   - reg32_write(0x3c240610,0x8);
806   - reg32_write(0x3c240614,0x8);
807   - reg32_write(0x3c240618,0x4);
808   - reg32_write(0x3c24061c,0x8);
809   - reg32_write(0x3c240620,0x8);
810   - reg32_write(0x3c240624,0x7c8);
811   - reg32_write(0x3c240628,0x101);
812   - reg32_write(0x3c240018,0x0);
813   - reg32_write(0x3c24001c,0x0);
814   - reg32_write(0x3c240020,0x8);
815   - reg32_write(0x3c240024,0x0);
816   - reg32_write(0x3c240028,0x0);
817   - reg32_write(0x3c24002c,0x0);
818   - reg32_write(0x3c34039c,0x400);
819   - reg32_write(0x3c24005c,0x0);
820   - reg32_write(0x3c24007c,0x2a);
821   - reg32_write(0x3c240098,0x6a);
822   - reg32_write(0x3c100340,0x0);
823   - reg32_write(0x3c100344,0x101);
824   - reg32_write(0x3c100348,0x105);
825   - reg32_write(0x3c10034c,0x107);
826   - reg32_write(0x3c100350,0x10f);
827   - reg32_write(0x3c100354,0x202);
828   - reg32_write(0x3c100358,0x20a);
829   - reg32_write(0x3c10035c,0x20b);
830   - reg32_write(0x3c0800e8,0x2);
831   - reg32_write(0x3c08002c,0x65);
832   - reg32_write(0x3c080030,0xc9);
833   - reg32_write(0x3c080034,0x7d1);
834   - reg32_write(0x3c080038,0x2c);
835   - reg32_write(0x3c48002c,0x65);
836   - reg32_write(0x3c480030,0xc9);
837   - reg32_write(0x3c480034,0x7d1);
838   - reg32_write(0x3c480038,0x2c);
839   - reg32_write(0x3c240030,0x0);
840   - reg32_write(0x3c240034,0x173);
841   - reg32_write(0x3c240038,0x60);
842   - reg32_write(0x3c24003c,0x6110);
843   - reg32_write(0x3c240040,0x2152);
844   - reg32_write(0x3c240044,0xdfbd);
845   - reg32_write(0x3c240048,0x60);
846   - reg32_write(0x3c24004c,0x6152);
847   - reg32_write(0x3c080040,0x5a);
848   - reg32_write(0x3c080044,0x3);
849   - reg32_write(0x3c480040,0x5a);
850   - reg32_write(0x3c480044,0x3);
851   - reg32_write(0x3c100200,0xe0);
852   - reg32_write(0x3c100204,0x12);
853   - reg32_write(0x3c100208,0xe0);
854   - reg32_write(0x3c10020c,0x12);
855   - reg32_write(0x3c100210,0xe0);
856   - reg32_write(0x3c100214,0x12);
857   - reg32_write(0x3c500200,0xe0);
858   - reg32_write(0x3c500204,0x12);
859   - reg32_write(0x3c500208,0xe0);
860   - reg32_write(0x3c50020c,0x12);
861   - reg32_write(0x3c500210,0xe0);
862   - reg32_write(0x3c500214,0x12);
863   - reg32_write(0x3c1003f4,0xf);
864   - reg32_write(0x3c040044,0x1);
865   - reg32_write(0x3c040048,0x1);
866   - reg32_write(0x3c04004c,0x180);
867   - reg32_write(0x3c040060,0x1);
868   - reg32_write(0x3c040008,0x6209);
869   - reg32_write(0x3c0402c8,0x1);
870   - reg32_write(0x3c0406d0,0x1);
871   - reg32_write(0x3c040ad0,0x1);
872   - reg32_write(0x3c040ed0,0x1);
873   - reg32_write(0x3c0412d0,0x1);
874   - reg32_write(0x3c0416d0,0x1);
875   - reg32_write(0x3c041ad0,0x1);
876   - reg32_write(0x3c041ed0,0x1);
877   - reg32_write(0x3c0422d0,0x1);
878   - reg32_write(0x3c044044,0x1);
879   - reg32_write(0x3c044048,0x1);
880   - reg32_write(0x3c04404c,0x180);
881   - reg32_write(0x3c044060,0x1);
882   - reg32_write(0x3c044008,0x6209);
883   - reg32_write(0x3c0442c8,0x1);
884   - reg32_write(0x3c0446d0,0x1);
885   - reg32_write(0x3c044ad0,0x1);
886   - reg32_write(0x3c044ed0,0x1);
887   - reg32_write(0x3c0452d0,0x1);
888   - reg32_write(0x3c0456d0,0x1);
889   - reg32_write(0x3c045ad0,0x1);
890   - reg32_write(0x3c045ed0,0x1);
891   - reg32_write(0x3c0462d0,0x1);
892   - reg32_write(0x3c048044,0x1);
893   - reg32_write(0x3c048048,0x1);
894   - reg32_write(0x3c04804c,0x180);
895   - reg32_write(0x3c048060,0x1);
896   - reg32_write(0x3c048008,0x6209);
897   - reg32_write(0x3c0482c8,0x1);
898   - reg32_write(0x3c0486d0,0x1);
899   - reg32_write(0x3c048ad0,0x1);
900   - reg32_write(0x3c048ed0,0x1);
901   - reg32_write(0x3c0492d0,0x1);
902   - reg32_write(0x3c0496d0,0x1);
903   - reg32_write(0x3c049ad0,0x1);
904   - reg32_write(0x3c049ed0,0x1);
905   - reg32_write(0x3c04a2d0,0x1);
906   - reg32_write(0x3c04c044,0x1);
907   - reg32_write(0x3c04c048,0x1);
908   - reg32_write(0x3c04c04c,0x180);
909   - reg32_write(0x3c04c060,0x1);
910   - reg32_write(0x3c04c008,0x6209);
911   - reg32_write(0x3c04c2c8,0x1);
912   - reg32_write(0x3c04c6d0,0x1);
913   - reg32_write(0x3c04cad0,0x1);
914   - reg32_write(0x3c04ced0,0x1);
915   - reg32_write(0x3c04d2d0,0x1);
916   - reg32_write(0x3c04d6d0,0x1);
917   - reg32_write(0x3c04dad0,0x1);
918   - reg32_write(0x3c04ded0,0x1);
919   - reg32_write(0x3c04e2d0,0x1);
920   - reg32_write(0x3c0800e8,0x2);
921   - reg32_write(0x3c300200,0x2);
922   - //customer Post Train
923   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010, 0x0000006a);
924   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d, 0x00000001);
925   - /*
926   - * CalBusy.0 =1, indicates the calibrator is actively calibrating.
927   - * Wait Calibrating done.
928   - */
929   - tmp_t = 1;
930   - while(tmp_t) {
931   - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20097);
932   - tmp_t = tmp & 0x01;
933   - }
934   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
935   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0);
936   - //disable APB bus to access DDRPHY RAM
937   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
938   -}
939   -
940   -void ddr_pll_bypass_100mts(void) {
941   - /* change the clock source of dram_alt_clk_root to source 2 --100MHz */
942   - reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0),(0x7<<24)|(0x7<<16));
943   - reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0),(0x2<<24));
944   -
945   - /* change the clock source of dram_apb_clk_root to source 2 --40MHz */
946   - reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
947   - reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x2<<24)|(0x1<<16));
948   -
949   - /* disable the clock gating */
950   - reg32_write(0x303A00EC,0x0000ffff); /* PGC_CPU_MAPPING */
951   - reg32setbit(0x303A00F8,5); /* PU_PGC_SW_PUP_REQ */
952   -
953   - /* configure pll bypass mode */
954   - reg32_write(0x30389804, 1<<24);
955   -
956   - printf("PLL bypass to 100MTS setting done \n");
957   -}
958   -
959   -void ddr_pll_bypass_400mts(void) {
960   - /* change the clock source of dram_alt_clk_root to source 2 --400MHz */
961   - reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0),(0x7<<24)|(0x7<<16));
962   - reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0),(0x5<<24));
963   -
964   - /* change the clock source of dram_apb_clk_root to source 2 --40MHz/2 */
965   - reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
966   - reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x2<<24)|(0x1<<16));
967   -
968   - /* disable the clock gating */
969   - reg32_write(0x303A00EC,0x0000ffff); /* PGC_CPU_MAPPING */
970   - reg32setbit(0x303A00F8,5); /* PU_PGC_SW_PUP_REQ */
971   -
972   - /* configure pll bypass mode */
973   - reg32_write(0x30389804, 1<<24);
974   -
975   - printf("PLL bypass to 400MTS setting done \n");
976   -}
977   -
978   -
979   -void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate)
980   -{
981   - if (pstate == 2)
982   - ddr_pll_bypass_100mts();
983   - else if (pstate == 1)
984   - ddr_pll_bypass_400mts();
985   - else {
986   - reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16));
987   - reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4 << 24) | (0x3 << 16));
988   - reg32_write(0x30389808, 1 << 24);
989   - }
990   -}
991   -
992   -void lpddr4_800M_cfg_phy(void) {
993   - unsigned int tmp, tmp_t;
994   -
995   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20110, 0x02);
996   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20111, 0x03);
997   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20112, 0x04);
998   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20113, 0x05);
999   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20114, 0x00);
1000   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20115, 0x01);
1001   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1005f, 0x1ff);
1002   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1015f, 0x1ff);
1003   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1105f, 0x1ff);
1004   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1115f, 0x1ff);
1005   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1205f, 0x1ff);
1006   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1215f, 0x1ff);
1007   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1305f, 0x1ff);
1008   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1315f, 0x1ff);
1009   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11005f, 0x1ff);
1010   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11015f, 0x1ff);
1011   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11105f, 0x1ff);
1012   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11115f, 0x1ff);
1013   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11205f, 0x1ff);
1014   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11215f, 0x1ff);
1015   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11305f, 0x1ff);
1016   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11315f, 0x1ff);
1017   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21005f, 0x1ff);
1018   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21015f, 0x1ff);
1019   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21105f, 0x1ff);
1020   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21115f, 0x1ff);
1021   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21205f, 0x1ff);
1022   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21215f, 0x1ff);
1023   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21305f, 0x1ff);
1024   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21315f, 0x1ff);
1025   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x55, 0x1ff);
1026   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1055, 0x1ff);
1027   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2055, 0x1ff);
1028   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3055, 0x1ff);
1029   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4055, 0x1ff);
1030   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5055, 0x1ff);
1031   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6055, 0x1ff);
1032   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7055, 0x1ff);
1033   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8055, 0x1ff);
1034   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9055, 0x1ff);
1035   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200c5, 0x19);
1036   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200c5, 0x7);
1037   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200c5, 0x7);
1038   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002e, 0x2);
1039   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002e, 0x2);
1040   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002e, 0x2);
1041   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90204, 0x0);
1042   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x190204, 0x0);
1043   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x290204, 0x0);
1044   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20024, 0xab);
1045   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
1046   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120024, 0xab);
1047   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
1048   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220024, 0xab);
1049   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
1050   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20056, 0x3);
1051   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120056, 0xa);
1052   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220056, 0xa);
1053   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1004d, 0xe00);
1054   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1014d, 0xe00);
1055   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1104d, 0xe00);
1056   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1114d, 0xe00);
1057   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1204d, 0xe00);
1058   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1214d, 0xe00);
1059   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1304d, 0xe00);
1060   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1314d, 0xe00);
1061   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11004d, 0xe00);
1062   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11014d, 0xe00);
1063   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11104d, 0xe00);
1064   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11114d, 0xe00);
1065   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11204d, 0xe00);
1066   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11214d, 0xe00);
1067   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11304d, 0xe00);
1068   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11314d, 0xe00);
1069   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21004d, 0xe00);
1070   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21014d, 0xe00);
1071   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21104d, 0xe00);
1072   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21114d, 0xe00);
1073   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21204d, 0xe00);
1074   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21214d, 0xe00);
1075   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21304d, 0xe00);
1076   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21314d, 0xe00);
1077   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10049, 0xe38);
1078   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10149, 0xe38);
1079   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11049, 0xe38);
1080   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11149, 0xe38);
1081   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12049, 0xe38);
1082   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12149, 0xe38);
1083   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13049, 0xe38);
1084   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13149, 0xe38);
1085   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110049, 0xe38);
1086   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110149, 0xe38);
1087   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111049, 0xe38);
1088   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111149, 0xe38);
1089   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112049, 0xe38);
1090   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112149, 0xe38);
1091   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113049, 0xe38);
1092   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113149, 0xe38);
1093   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210049, 0xe38);
1094   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210149, 0xe38);
1095   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211049, 0xe38);
1096   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211149, 0xe38);
1097   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212049, 0xe38);
1098   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212149, 0xe38);
1099   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213049, 0xe38);
1100   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213149, 0xe38);
1101   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x43, 0x21);
1102   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1043, 0x21);
1103   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2043, 0x21);
1104   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3043, 0x21);
1105   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4043, 0x21);
1106   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5043, 0x21);
1107   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6043, 0x21);
1108   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7043, 0x21);
1109   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8043, 0x21);
1110   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9043, 0x21);
1111   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20018, 0x3);
1112   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20075, 0x4);
1113   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20050, 0x0);
1114   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20008, 0x320);
1115   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120008, 0x64);
1116   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220008, 0x19);
1117   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20088, 0x9);
1118   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200b2, 0x19c);
1119   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10043, 0x5a1);
1120   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10143, 0x5a1);
1121   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11043, 0x5a1);
1122   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11143, 0x5a1);
1123   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12043, 0x5a1);
1124   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12143, 0x5a1);
1125   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13043, 0x5a1);
1126   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13143, 0x5a1);
1127   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200b2, 0x19c);
1128   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110043, 0x5a1);
1129   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110143, 0x5a1);
1130   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111043, 0x5a1);
1131   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111143, 0x5a1);
1132   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112043, 0x5a1);
1133   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112143, 0x5a1);
1134   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113043, 0x5a1);
1135   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113143, 0x5a1);
1136   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200b2, 0x19c);
1137   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210043, 0x5a1);
1138   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210143, 0x5a1);
1139   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211043, 0x5a1);
1140   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211143, 0x5a1);
1141   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212043, 0x5a1);
1142   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212143, 0x5a1);
1143   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213043, 0x5a1);
1144   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213143, 0x5a1);
1145   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200fa, 0x1);
1146   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200fa, 0x1);
1147   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200fa, 0x1);
1148   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20019, 0x1);
1149   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120019, 0x1);
1150   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220019, 0x1);
1151   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f0, 0x660);
1152   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f1, 0x0);
1153   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f2, 0x4444);
1154   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f3, 0x8888);
1155   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f4, 0x5555);
1156   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f5, 0x0);
1157   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f6, 0x0);
1158   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f7, 0xf000);
1159   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000b, 0x65);
1160   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000c, 0xc9);
1161   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000d, 0x7d1);
1162   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000e, 0x2c);
1163   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000b, 0xd);
1164   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000c, 0x1a);
1165   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000d, 0xfb);
1166   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000e, 0x10);
1167   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000b, 0x4);
1168   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000c, 0x7);
1169   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000d, 0x3f);
1170   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000e, 0x10);
1171   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20025, 0x0);
1172   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002d, 0x0);
1173   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002d, 0x0);
1174   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002d, 0x0);
1175   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20060, 0x2);
1176   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
1177   - /* load the 1D training image */
1178   - ddr_load_train_code(FW_1D_IMAGE);
1179   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
1180   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
1181   -
1182   - /* set the PHY input clock to the desired frequency for pstate 2 */
1183   - dwc_ddrphy_phyinit_userCustom_E_setDfiClk(2);
1184   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
1185   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000,0x0);
1186   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001,0x0);
1187   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x102);
1188   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x64);
1189   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
1190   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2828);
1191   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x14);
1192   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007,0x0);
1193   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f);
1194   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
1195   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a,0x0);
1196   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
1197   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c,0x0);
1198   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x0);
1199   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e,0x0);
1200   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x0);
1201   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x0);
1202   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011,0x0);
1203   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
1204   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013,0x0);
1205   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014,0x0);
1206   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015,0x0);
1207   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016,0x0);
1208   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017,0x0);
1209   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018,0x0);
1210   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x4);
1211   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
1212   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
1213   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
1214   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d,0x0);
1215   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x5);
1216   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x4);
1217   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
1218   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
1219   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
1220   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023,0x0);
1221   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x5);
1222   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025,0x0);
1223   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026,0x0);
1224   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027,0x0);
1225   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028,0x0);
1226   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029,0x0);
1227   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a,0x0);
1228   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
1229   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
1230   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d,0x0);
1231   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e,0x0);
1232   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f,0x0);
1233   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030,0x0);
1234   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031,0x0);
1235   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x400);
1236   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100);
1237   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
1238   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d);
1239   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
1240   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x500);
1241   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x400);
1242   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100);
1243   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
1244   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d);
1245   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
1246   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
1247   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
1248   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
1249   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
1250   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
1251   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
1252   -extern void wait_ddrphy_training_complete(void);
1253   - wait_ddrphy_training_complete();
1254   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
1255   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
1256   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
1257   -
1258   - /* set the PHY input clock to the desired frequency for pstate 1 */
1259   - dwc_ddrphy_phyinit_userCustom_E_setDfiClk(1);
1260   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
1261   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000,0x0);
1262   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001,0x0);
1263   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x101);
1264   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x190);
1265   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
1266   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2828);
1267   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x14);
1268   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007,0x0);
1269   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f);
1270   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
1271   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a,0x0);
1272   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
1273   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c,0x0);
1274   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x0);
1275   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e,0x0);
1276   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x0);
1277   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x0);
1278   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011,0x0);
1279   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
1280   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013,0x0);
1281   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014,0x0);
1282   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015,0x0);
1283   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016,0x0);
1284   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017,0x0);
1285   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018,0x0);
1286   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x4);
1287   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
1288   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
1289   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
1290   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d,0x0);
1291   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x5);
1292   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x4);
1293   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
1294   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
1295   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
1296   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023,0x0);
1297   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x5);
1298   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025,0x0);
1299   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026,0x0);
1300   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027,0x0);
1301   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028,0x0);
1302   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029,0x0);
1303   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a,0x0);
1304   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
1305   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
1306   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d,0x0);
1307   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e,0x0);
1308   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f,0x0);
1309   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030,0x0);
1310   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031,0x0);
1311   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x400);
1312   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100);
1313   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
1314   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d);
1315   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
1316   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x500);
1317   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x400);
1318   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100);
1319   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
1320   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d);
1321   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d);
1322   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x500);
1323   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
1324   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
1325   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
1326   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
1327   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
1328   -extern void wait_ddrphy_training_complete(void);
1329   - wait_ddrphy_training_complete();
1330   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
1331   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
1332   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
1333   -
1334   - /* set the PHY input clock to the desired frequency for pstate 0 */
1335   - dwc_ddrphy_phyinit_userCustom_E_setDfiClk(0);
1336   -
1337   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
1338   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
1339   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
1340   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0);
1341   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80);
1342   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
1343   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, 0x2828);
1344   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, 0x14);
1345   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
1346   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x131f);
1347   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0x5);
1348   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
1349   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
1350   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
1351   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, 0x0);
1352   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
1353   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0);
1354   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0);
1355   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
1356   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
1357   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
1358   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
1359   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
1360   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
1361   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
1362   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
1363   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4);
1364   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, 0x31);
1365   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, 0x4d46);
1366   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, 0x4d08);
1367   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
1368   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x5);
1369   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4);
1370   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, 0x31);
1371   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, 0x4d46);
1372   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, 0x4d08);
1373   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
1374   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5);
1375   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
1376   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
1377   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
1378   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
1379   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
1380   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
1381   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
1382   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
1383   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
1384   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
1385   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
1386   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
1387   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
1388   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400);
1389   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, 0x312d);
1390   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, 0x4600);
1391   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, 0x84d);
1392   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, 0x4d);
1393   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x500);
1394   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400);
1395   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, 0x312d);
1396   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, 0x4600);
1397   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, 0x84d);
1398   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
1399   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
1400   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
1401   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
1402   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
1403   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
1404   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
1405   -extern void wait_ddrphy_training_complete(void);
1406   -wait_ddrphy_training_complete();
1407   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
1408   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
1409   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
1410   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
1411   - /* load the 2D training image */
1412   - ddr_load_train_code(FW_2D_IMAGE);
1413   -
1414   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0);
1415   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1);
1416   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0);
1417   -
1418   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000,0x0);
1419   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001,0x0);
1420   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x0);
1421   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80);
1422   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
1423   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2828);
1424   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x14);
1425   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007,0x0);
1426   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x61);
1427   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
1428   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a,0x0);
1429   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
1430   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c,0x0);
1431   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100);
1432   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e,0x0);
1433   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x100);
1434   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x1f7f);
1435   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011,0x0);
1436   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
1437   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013,0x0);
1438   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014,0x0);
1439   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015,0x0);
1440   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016,0x0);
1441   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017,0x0);
1442   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018,0x0);
1443   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4);
1444   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
1445   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
1446   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
1447   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d,0x0);
1448   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x5);
1449   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4);
1450   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
1451   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
1452   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
1453   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023,0x0);
1454   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x5);
1455   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025,0x0);
1456   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026,0x0);
1457   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027,0x0);
1458   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028,0x0);
1459   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029,0x0);
1460   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a,0x0);
1461   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
1462   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
1463   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d,0x0);
1464   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e,0x0);
1465   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f,0x0);
1466   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030,0x0);
1467   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031,0x0);
1468   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400);
1469   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d);
1470   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
1471   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x084d);
1472   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
1473   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x500);
1474   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400);
1475   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d);
1476   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
1477   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x084d);
1478   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d);
1479   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x500);
1480   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1);
1481   - /* Execute the Training Firmware */
1482   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1);
1483   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x9);
1484   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x1);
1485   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x0);
1486   - /* wait for 2D training complete */
1487   - extern void wait_ddrphy_training_complete(void);
1488   - wait_ddrphy_training_complete();
1489   -
1490   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099,0x1);
1491   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0);
1492   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x1);
1493   -
1494   - /* (I) Load PHY Init Engine Image */
1495   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000,0x0);
1496   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90000, 0x10);
1497   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90001, 0x400);
1498   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90002, 0x10e);
1499   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90003, 0x0);
1500   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90004, 0x0);
1501   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90005, 0x8);
1502   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90029, 0xb);
1503   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002a, 0x480);
1504   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002b, 0x109);
1505   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002c, 0x8);
1506   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002d, 0x448);
1507   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002e, 0x139);
1508   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002f, 0x8);
1509   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90030, 0x478);
1510   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90031, 0x109);
1511   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90032, 0x0);
1512   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90033, 0xe8);
1513   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90034, 0x109);
1514   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90035, 0x2);
1515   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90036, 0x10);
1516   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90037, 0x139);
1517   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90038, 0xf);
1518   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90039, 0x7c0);
1519   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003a, 0x139);
1520   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003b, 0x44);
1521   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003c, 0x630);
1522   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003d, 0x159);
1523   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003e, 0x14f);
1524   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003f, 0x630);
1525   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90040, 0x159);
1526   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90041, 0x47);
1527   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90042, 0x630);
1528   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90043, 0x149);
1529   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90044, 0x4f);
1530   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90045, 0x630);
1531   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90046, 0x179);
1532   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90047, 0x8);
1533   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90048, 0xe0);
1534   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90049, 0x109);
1535   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004a, 0x0);
1536   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004b, 0x7c8);
1537   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004c, 0x109);
1538   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004d, 0x0);
1539   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004e, 0x1);
1540   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004f, 0x8);
1541   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90050, 0x0);
1542   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90051, 0x45a);
1543   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90052, 0x9);
1544   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90053, 0x0);
1545   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90054, 0x448);
1546   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90055, 0x109);
1547   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90056, 0x40);
1548   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90057, 0x630);
1549   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90058, 0x179);
1550   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90059, 0x1);
1551   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005a, 0x618);
1552   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005b, 0x109);
1553   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005c, 0x40c0);
1554   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005d, 0x630);
1555   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005e, 0x149);
1556   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005f, 0x8);
1557   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90060, 0x4);
1558   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90061, 0x48);
1559   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90062, 0x4040);
1560   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90063, 0x630);
1561   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90064, 0x149);
1562   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90065, 0x0);
1563   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90066, 0x4);
1564   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90067, 0x48);
1565   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90068, 0x40);
1566   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90069, 0x630);
1567   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006a, 0x149);
1568   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006b, 0x10);
1569   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006c, 0x4);
1570   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006d, 0x18);
1571   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006e, 0x0);
1572   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006f, 0x4);
1573   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90070, 0x78);
1574   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90071, 0x549);
1575   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90072, 0x630);
1576   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90073, 0x159);
1577   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90074, 0xd49);
1578   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90075, 0x630);
1579   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90076, 0x159);
1580   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90077, 0x94a);
1581   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90078, 0x630);
1582   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90079, 0x159);
1583   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007a, 0x441);
1584   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007b, 0x630);
1585   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007c, 0x149);
1586   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007d, 0x42);
1587   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007e, 0x630);
1588   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007f, 0x149);
1589   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90080, 0x1);
1590   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90081, 0x630);
1591   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90082, 0x149);
1592   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90083, 0x0);
1593   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90084, 0xe0);
1594   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90085, 0x109);
1595   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90086, 0xa);
1596   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90087, 0x10);
1597   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90088, 0x109);
1598   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90089, 0x9);
1599   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008a, 0x3c0);
1600   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008b, 0x149);
1601   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008c, 0x9);
1602   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008d, 0x3c0);
1603   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008e, 0x159);
1604   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008f, 0x18);
1605   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90090, 0x10);
1606   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90091, 0x109);
1607   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90092, 0x0);
1608   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90093, 0x3c0);
1609   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90094, 0x109);
1610   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90095, 0x18);
1611   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90096, 0x4);
1612   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90097, 0x48);
1613   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90098, 0x18);
1614   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90099, 0x4);
1615   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009a, 0x58);
1616   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009b, 0xa);
1617   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009c, 0x10);
1618   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009d, 0x109);
1619   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009e, 0x2);
1620   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009f, 0x10);
1621   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a0, 0x109);
1622   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a1, 0x5);
1623   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a2, 0x7c0);
1624   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a3, 0x109);
1625   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a4, 0x10);
1626   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a5, 0x10);
1627   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a6, 0x109);
1628   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40000, 0x811);
1629   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40020, 0x880);
1630   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40040, 0x0);
1631   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40060, 0x0);
1632   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40001, 0x4016);
1633   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40021, 0x83);
1634   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40041, 0x4f);
1635   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40061, 0x0);
1636   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40002, 0x4040);
1637   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40022, 0x83);
1638   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40042, 0x51);
1639   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40062, 0x0);
1640   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40003, 0x811);
1641   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40023, 0x880);
1642   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40043, 0x0);
1643   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40063, 0x0);
1644   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40004, 0x720);
1645   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40024, 0xf);
1646   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40044, 0x1740);
1647   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40064, 0x0);
1648   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40005, 0x16);
1649   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40025, 0x83);
1650   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40045, 0x4b);
1651   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40065, 0x0);
1652   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40006, 0x716);
1653   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40026, 0xf);
1654   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40046, 0x2001);
1655   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40066, 0x0);
1656   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40007, 0x716);
1657   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40027, 0xf);
1658   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40047, 0x2800);
1659   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40067, 0x0);
1660   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40008, 0x716);
1661   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40028, 0xf);
1662   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40048, 0xf00);
1663   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40068, 0x0);
1664   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40009, 0x720);
1665   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40029, 0xf);
1666   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40049, 0x1400);
1667   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40069, 0x0);
1668   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000a, 0xe08);
1669   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002a, 0xc15);
1670   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004a, 0x0);
1671   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006a, 0x0);
1672   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000b, 0x623);
1673   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002b, 0x15);
1674   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004b, 0x0);
1675   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006b, 0x0);
1676   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000c, 0x4004);
1677   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002c, 0x80);
1678   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004c, 0x0);
1679   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006c, 0x0);
1680   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000d, 0xe08);
1681   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002d, 0xc1a);
1682   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004d, 0x0);
1683   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006d, 0x0);
1684   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000e, 0x623);
1685   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002e, 0x1a);
1686   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004e, 0x0);
1687   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006e, 0x0);
1688   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000f, 0x4040);
1689   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002f, 0x80);
1690   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004f, 0x0);
1691   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006f, 0x0);
1692   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40010, 0x2604);
1693   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40030, 0x15);
1694   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40050, 0x0);
1695   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40070, 0x0);
1696   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40011, 0x708);
1697   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40031, 0x5);
1698   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40051, 0x0);
1699   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40071, 0x2002);
1700   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40012, 0x8);
1701   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40032, 0x80);
1702   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40052, 0x0);
1703   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40072, 0x0);
1704   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40013, 0x2604);
1705   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40033, 0x1a);
1706   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40053, 0x0);
1707   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40073, 0x0);
1708   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40014, 0x708);
1709   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40034, 0xa);
1710   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40054, 0x0);
1711   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40074, 0x2002);
1712   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40015, 0x4040);
1713   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40035, 0x80);
1714   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40055, 0x0);
1715   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40075, 0x0);
1716   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40016, 0x60a);
1717   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40036, 0x15);
1718   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40056, 0x1200);
1719   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40076, 0x0);
1720   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40017, 0x61a);
1721   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40037, 0x15);
1722   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40057, 0x1300);
1723   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40077, 0x0);
1724   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40018, 0x60a);
1725   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40038, 0x1a);
1726   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40058, 0x1200);
1727   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40078, 0x0);
1728   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40019, 0x642);
1729   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40039, 0x1a);
1730   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40059, 0x1300);
1731   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40079, 0x0);
1732   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4001a, 0x4808);
1733   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4003a, 0x880);
1734   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4005a, 0x0);
1735   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4007a, 0x0);
1736   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a7, 0x0);
1737   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a8, 0x790);
1738   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a9, 0x11a);
1739   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900aa, 0x8);
1740   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ab, 0x7aa);
1741   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ac, 0x2a);
1742   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ad, 0x10);
1743   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ae, 0x7b2);
1744   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900af, 0x2a);
1745   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b0, 0x0);
1746   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b1, 0x7c8);
1747   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b2, 0x109);
1748   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b3, 0x10);
1749   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b4, 0x2a8);
1750   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b5, 0x129);
1751   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b6, 0x8);
1752   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b7, 0x370);
1753   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b8, 0x129);
1754   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b9, 0xa);
1755   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ba, 0x3c8);
1756   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bb, 0x1a9);
1757   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bc, 0xc);
1758   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bd, 0x408);
1759   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900be, 0x199);
1760   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bf, 0x14);
1761   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c0, 0x790);
1762   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c1, 0x11a);
1763   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c2, 0x8);
1764   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c3, 0x4);
1765   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c4, 0x18);
1766   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c5, 0xc);
1767   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c6, 0x408);
1768   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c7, 0x199);
1769   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c8, 0x8);
1770   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c9, 0x8568);
1771   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ca, 0x108);
1772   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cb, 0x18);
1773   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cc, 0x790);
1774   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cd, 0x16a);
1775   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ce, 0x8);
1776   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cf, 0x1d8);
1777   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d0, 0x169);
1778   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d1, 0x10);
1779   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d2, 0x8558);
1780   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d3, 0x168);
1781   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d4, 0x70);
1782   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d5, 0x788);
1783   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d6, 0x16a);
1784   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d7, 0x1ff8);
1785   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d8, 0x85a8);
1786   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d9, 0x1e8);
1787   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900da, 0x50);
1788   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900db, 0x798);
1789   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dc, 0x16a);
1790   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dd, 0x60);
1791   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900de, 0x7a0);
1792   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900df, 0x16a);
1793   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e0, 0x8);
1794   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e1, 0x8310);
1795   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e2, 0x168);
1796   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e3, 0x8);
1797   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e4, 0xa310);
1798   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e5, 0x168);
1799   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e6, 0xa);
1800   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e7, 0x408);
1801   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e8, 0x169);
1802   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e9, 0x6e);
1803   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ea, 0x0);
1804   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900eb, 0x68);
1805   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ec, 0x0);
1806   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ed, 0x408);
1807   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ee, 0x169);
1808   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ef, 0x0);
1809   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f0, 0x8310);
1810   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f1, 0x168);
1811   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f2, 0x0);
1812   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f3, 0xa310);
1813   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f4, 0x168);
1814   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f5, 0x1ff8);
1815   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f6, 0x85a8);
1816   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f7, 0x1e8);
1817   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f8, 0x68);
1818   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f9, 0x798);
1819   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fa, 0x16a);
1820   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fb, 0x78);
1821   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fc, 0x7a0);
1822   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fd, 0x16a);
1823   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fe, 0x68);
1824   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ff, 0x790);
1825   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90100, 0x16a);
1826   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90101, 0x8);
1827   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90102, 0x8b10);
1828   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90103, 0x168);
1829   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90104, 0x8);
1830   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90105, 0xab10);
1831   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90106, 0x168);
1832   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90107, 0xa);
1833   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90108, 0x408);
1834   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90109, 0x169);
1835   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010a, 0x58);
1836   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010b, 0x0);
1837   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010c, 0x68);
1838   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010d, 0x0);
1839   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010e, 0x408);
1840   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010f, 0x169);
1841   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90110, 0x0);
1842   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90111, 0x8b10);
1843   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90112, 0x168);
1844   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90113, 0x0);
1845   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90114, 0xab10);
1846   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90115, 0x168);
1847   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90116, 0x0);
1848   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90117, 0x1d8);
1849   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90118, 0x169);
1850   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90119, 0x80);
1851   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011a, 0x790);
1852   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011b, 0x16a);
1853   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011c, 0x18);
1854   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011d, 0x7aa);
1855   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011e, 0x6a);
1856   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011f, 0xa);
1857   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90120, 0x0);
1858   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90121, 0x1e9);
1859   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90122, 0x8);
1860   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90123, 0x8080);
1861   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90124, 0x108);
1862   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90125, 0xf);
1863   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90126, 0x408);
1864   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90127, 0x169);
1865   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90128, 0xc);
1866   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90129, 0x0);
1867   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012a, 0x68);
1868   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012b, 0x9);
1869   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012c, 0x0);
1870   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012d, 0x1a9);
1871   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012e, 0x0);
1872   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012f, 0x408);
1873   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90130, 0x169);
1874   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90131, 0x0);
1875   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90132, 0x8080);
1876   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90133, 0x108);
1877   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90134, 0x8);
1878   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90135, 0x7aa);
1879   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90136, 0x6a);
1880   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90137, 0x0);
1881   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90138, 0x8568);
1882   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90139, 0x108);
1883   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013a, 0xb7);
1884   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013b, 0x790);
1885   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013c, 0x16a);
1886   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013d, 0x1d);
1887   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013e, 0x0);
1888   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013f, 0x68);
1889   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90140, 0x8);
1890   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90141, 0x8558);
1891   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90142, 0x168);
1892   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90143, 0xf);
1893   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90144, 0x408);
1894   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90145, 0x169);
1895   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90146, 0xc);
1896   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90147, 0x0);
1897   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90148, 0x68);
1898   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90149, 0x0);
1899   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014a, 0x408);
1900   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014b, 0x169);
1901   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014c, 0x0);
1902   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014d, 0x8558);
1903   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014e, 0x168);
1904   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014f, 0x8);
1905   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90150, 0x3c8);
1906   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90151, 0x1a9);
1907   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90152, 0x3);
1908   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90153, 0x370);
1909   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90154, 0x129);
1910   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90155, 0x20);
1911   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90156, 0x2aa);
1912   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90157, 0x9);
1913   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90158, 0x0);
1914   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90159, 0x400);
1915   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015a, 0x10e);
1916   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015b, 0x8);
1917   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015c, 0xe8);
1918   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015d, 0x109);
1919   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015e, 0x0);
1920   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015f, 0x8140);
1921   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90160, 0x10c);
1922   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90161, 0x10);
1923   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90162, 0x8138);
1924   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90163, 0x10c);
1925   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90164, 0x8);
1926   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90165, 0x7c8);
1927   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90166, 0x101);
1928   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90167, 0x8);
1929   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90168, 0x0);
1930   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90169, 0x8);
1931   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016a, 0x8);
1932   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016b, 0x448);
1933   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016c, 0x109);
1934   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016d, 0xf);
1935   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016e, 0x7c0);
1936   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016f, 0x109);
1937   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90170, 0x0);
1938   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90171, 0xe8);
1939   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90172, 0x109);
1940   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90173, 0x47);
1941   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90174, 0x630);
1942   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90175, 0x109);
1943   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90176, 0x8);
1944   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90177, 0x618);
1945   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90178, 0x109);
1946   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90179, 0x8);
1947   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017a, 0xe0);
1948   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017b, 0x109);
1949   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017c, 0x0);
1950   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017d, 0x7c8);
1951   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017e, 0x109);
1952   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017f, 0x8);
1953   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90180, 0x8140);
1954   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90181, 0x10c);
1955   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90182, 0x0);
1956   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90183, 0x1);
1957   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90184, 0x8);
1958   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90185, 0x8);
1959   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90186, 0x4);
1960   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90187, 0x8);
1961   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90188, 0x8);
1962   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90189, 0x7c8);
1963   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018a, 0x101);
1964   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90006, 0x0);
1965   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90007, 0x0);
1966   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90008, 0x8);
1967   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90009, 0x0);
1968   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000a, 0x0);
1969   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000b, 0x0);
1970   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd00e7, 0x400);
1971   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90017, 0x0);
1972   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9001f, 0x2a);
1973   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90026, 0x6a);
1974   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d0, 0x0);
1975   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d1, 0x101);
1976   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d2, 0x105);
1977   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d3, 0x107);
1978   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d4, 0x10f);
1979   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d5, 0x202);
1980   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d6, 0x20a);
1981   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d7, 0x20b);
1982   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
1983   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000c, 0x0);
1984   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000d, 0x173);
1985   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000e, 0x60);
1986   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000f, 0x6110);
1987   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90010, 0x2152);
1988   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90011, 0xdfbd);
1989   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90012, 0x60);
1990   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90013, 0x6152);
1991   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20010, 0x5a);
1992   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20011, 0x3);
1993   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40080, 0xe0);
1994   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40081, 0x12);
1995   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40082, 0xe0);
1996   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40083, 0x12);
1997   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40084, 0xe0);
1998   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40085, 0x12);
1999   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400fd, 0xf);
2000   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10011, 0x1);
2001   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10012, 0x1);
2002   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10013, 0x180);
2003   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10018, 0x1);
2004   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10002, 0x6209);
2005   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x100b2, 0x1);
2006   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x101b4, 0x1);
2007   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x102b4, 0x1);
2008   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x103b4, 0x1);
2009   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x104b4, 0x1);
2010   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x105b4, 0x1);
2011   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x106b4, 0x1);
2012   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x107b4, 0x1);
2013   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x108b4, 0x1);
2014   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11011, 0x1);
2015   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11012, 0x1);
2016   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11013, 0x180);
2017   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11018, 0x1);
2018   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11002, 0x6209);
2019   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110b2, 0x1);
2020   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111b4, 0x1);
2021   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112b4, 0x1);
2022   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113b4, 0x1);
2023   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x114b4, 0x1);
2024   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x115b4, 0x1);
2025   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x116b4, 0x1);
2026   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x117b4, 0x1);
2027   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x118b4, 0x1);
2028   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12011, 0x1);
2029   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12012, 0x1);
2030   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12013, 0x180);
2031   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12018, 0x1);
2032   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002, 0x6209);
2033   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120b2, 0x1);
2034   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x121b4, 0x1);
2035   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x122b4, 0x1);
2036   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x123b4, 0x1);
2037   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x124b4, 0x1);
2038   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x125b4, 0x1);
2039   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x126b4, 0x1);
2040   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x127b4, 0x1);
2041   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x128b4, 0x1);
2042   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13011, 0x1);
2043   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13012, 0x1);
2044   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13013, 0x180);
2045   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13018, 0x1);
2046   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13002, 0x6209);
2047   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x130b2, 0x1);
2048   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x131b4, 0x1);
2049   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x132b4, 0x1);
2050   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x133b4, 0x1);
2051   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x134b4, 0x1);
2052   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x135b4, 0x1);
2053   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x136b4, 0x1);
2054   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x137b4, 0x1);
2055   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x138b4, 0x1);
2056   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
2057   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xc0080, 0x2);
2058   - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
2059   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x000d0000, 0x00000000);
2060   - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010);
2061   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010, 0x0000006a);
2062   - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d);
2063   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d, 0x00000001);
2064   - /*
2065   - * CalBusy.0 =1, indicates the calibrator is actively calibrating.
2066   - * Wait Calibrating done.
2067   - */
2068   - tmp_t = 1;
2069   - while(tmp_t) {
2070   - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20097);
2071   - tmp_t = tmp & 0x01;
2072   - }
2073   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
2074   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0);
2075   -}
board/freescale/imx8mq_aiy/ddr/helper.c
View file @ 63dbfc0
1   -/*
2   - * Copyright 2017 NXP
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <common.h>
8   -#include <spl.h>
9   -#include <asm/io.h>
10   -#include <errno.h>
11   -#include <asm/io.h>
12   -#include <asm/arch/ddr.h>
13   -#include <asm/sections.h>
14   -
15   -#include "ddr.h"
16   -
17   -DECLARE_GLOBAL_DATA_PTR;
18   -
19   -#define IMEM_LEN 32768//23400 //byte
20   -#define DMEM_LEN 16384//1720 //byte
21   -#define IMEM_2D_OFFSET 49152
22   -
23   -#define IMEM_OFFSET_ADDR 0x00050000
24   -#define DMEM_OFFSET_ADDR 0x00054000
25   -#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
26   -
27   -/* We need PHY iMEM PHY is 32KB padded */
28   -void ddr_load_train_code(enum fw_type type)
29   -{
30   - u32 tmp32, i;
31   - u32 error = 0;
32   - unsigned long pr_to32, pr_from32;
33   - unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
34   - unsigned long imem_start = (unsigned long)&_end + fw_offset;
35   - unsigned long dmem_start = imem_start + IMEM_LEN;
36   -
37   - pr_from32 = imem_start;
38   - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
39   - for(i = 0x0; i < IMEM_LEN; ){
40   - tmp32 = readl(pr_from32);
41   - writew(tmp32 & 0x0000ffff, pr_to32);
42   - pr_to32 += 4;
43   - writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
44   - pr_to32 += 4;
45   - pr_from32 += 4;
46   - i += 4;
47   - }
48   -
49   - pr_from32 = dmem_start;
50   - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
51   - for(i = 0x0; i < DMEM_LEN;){
52   - tmp32 = readl(pr_from32);
53   - writew(tmp32 & 0x0000ffff, pr_to32);
54   - pr_to32 += 4;
55   - writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
56   - pr_to32 += 4;
57   - pr_from32 += 4;
58   - i += 4;
59   - }
60   -
61   - printf("check ddr4_pmu_train_imem code\n");
62   - pr_from32 = imem_start;
63   - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
64   - for(i = 0x0; i < IMEM_LEN;){
65   - tmp32 = (readw(pr_to32) & 0x0000ffff);
66   - pr_to32 += 4;
67   - tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
68   -
69   - if(tmp32 != readl(pr_from32)){
70   - printf("%lx %lx\n", pr_from32, pr_to32);
71   - error++;
72   - }
73   - pr_from32 += 4;
74   - pr_to32 += 4;
75   - i += 4;
76   - }
77   - if(error){
78   - printf("check ddr4_pmu_train_imem code fail=%d\n",error);
79   - }else{
80   - printf("check ddr4_pmu_train_imem code pass\n");
81   - }
82   -
83   - printf("check ddr4_pmu_train_dmem code\n");
84   - pr_from32 = dmem_start;
85   - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
86   - for(i = 0x0; i < DMEM_LEN;){
87   - tmp32 = (readw(pr_to32) & 0x0000ffff);
88   - pr_to32 += 4;
89   - tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
90   - if(tmp32 != readl(pr_from32)){
91   - printf("%lx %lx\n", pr_from32, pr_to32);
92   - error++;
93   - }
94   - pr_from32 += 4;
95   - pr_to32 += 4;
96   - i += 4;
97   - }
98   -
99   - if(error){
100   - printf("check ddr4_pmu_train_dmem code fail=%d",error);
101   - }else{
102   - printf("check ddr4_pmu_train_dmem code pass\n");
103   - }
104   -}
board/freescale/imx8mq_aiy/ddr/lpddr4_dvfs.h
View file @ 63dbfc0
1   -/*
2   - * Copyright 2018 NXP
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#ifndef __LPDDR4_DVFS_H__
8   -#define __LPDDR4_DVFS_H__
9   -#include <asm/arch/ddr.h>
10   -
11   -#define DFILP_SPT
12   -
13   -#define ANAMIX_PLL_BASE_ADDR 0x30360000
14   -#define HW_DRAM_PLL_CFG0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60)
15   -#define HW_DRAM_PLL_CFG1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64)
16   -#define HW_DRAM_PLL_CFG2_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68)
17   -
18   -#define LPDDR4_HDT_CTL_2D 0xC8 /* stage completion */
19   -#define LPDDR4_HDT_CTL_3200_1D 0xC8 /* stage completion */
20   -#define LPDDR4_HDT_CTL_400_1D 0xC8 /* stage completion */
21   -#define LPDDR4_HDT_CTL_100_1D 0xC8 /* stage completion */
22   -
23   -/* 2D share & weight */
24   -#define LPDDR4_2D_WEIGHT 0x1f7f
25   -#define LPDDR4_2D_SHARE 1
26   -#define LPDDR4_CATRAIN_3200_1d 0
27   -#define LPDDR4_CATRAIN_400 0
28   -#define LPDDR4_CATRAIN_100 0
29   -#define LPDDR4_CATRAIN_3200_2d 0
30   -
31   -#define WR_POST_EXT_3200 /* recommened to define */
32   -
33   -/* lpddr4 phy training config */
34   -/* for LPDDR4 Rtt */
35   -#define LPDDR4_RTT40 6
36   -#define LPDDR4_RTT48 5
37   -#define LPDDR4_RTT60 4
38   -#define LPDDR4_RTT80 3
39   -#define LPDDR4_RTT120 2
40   -#define LPDDR4_RTT240 1
41   -#define LPDDR4_RTT_DIS 0
42   -
43   -/* for LPDDR4 Ron */
44   -#define LPDDR4_RON34 7
45   -#define LPDDR4_RON40 6
46   -#define LPDDR4_RON48 5
47   -#define LPDDR4_RON60 4
48   -#define LPDDR4_RON80 3
49   -
50   -#define LPDDR4_PHY_ADDR_RON60 0x1
51   -#define LPDDR4_PHY_ADDR_RON40 0x3
52   -#define LPDDR4_PHY_ADDR_RON30 0x7
53   -#define LPDDR4_PHY_ADDR_RON24 0xf
54   -#define LPDDR4_PHY_ADDR_RON20 0x1f
55   -
56   -/* for read channel */
57   -#define LPDDR4_RON LPDDR4_RON40 /* MR3[5:3] */
58   -#define LPDDR4_PHY_RTT 30
59   -#define LPDDR4_PHY_VREF_VALUE 17
60   -
61   -/* for write channel */
62   -#define LPDDR4_PHY_RON 30
63   -#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40
64   -#define LPDDR4_RTT_DQ LPDDR4_RTT40 /* MR11[2:0] */
65   -#define LPDDR4_RTT_CA LPDDR4_RTT40 /* MR11[6:4] */
66   -#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 /* MR11[6:4] */
67   -#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 /* LPDDR4_RTT_DIS//MR11[6:4] */
68   -#define LPDDR4_VREF_VALUE_CA ((1<<6)|(0xd)) /*((0<<6)|(0xe)) MR12 */
69   -#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1<<6)|(0xd)) /* MR14 */
70   -#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1<<6)|(0xd)) /* MR14 */
71   -#define LPDDR4_MR22_RANK0 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */
72   -#define LPDDR4_MR22_RANK1 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */
73   -#define LPDDR4_MR3_PU_CAL 1 /* MR3[0] */
74   -
75   -#define LPDDR4_2D_WEIGHT 0x1f7f
76   -#define LPDDR4_2D_SHARE 1
77   -
78   -#endif /*__LPDDR4_DVFS_H__ */
board/freescale/imx8mq_aiy/ddr/wait_ddrphy_training_complete.c
View file @ 63dbfc0
1   -/*
2   - * Copyright 2017 NXP
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -static inline void poll_pmu_message_ready(void)
8   -{
9   - unsigned int reg;
10   -
11   - do {
12   - reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
13   - } while (reg & 0x1);
14   -}
15   -
16   -static inline void ack_pmu_message_recieve(void)
17   -{
18   - unsigned int reg;
19   -
20   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0);
21   -
22   - do {
23   - reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
24   - } while (!(reg & 0x1));
25   -
26   - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1);
27   -}
28   -
29   -static inline unsigned int get_mail(void)
30   -{
31   - unsigned int reg;
32   -
33   - poll_pmu_message_ready();
34   -
35   - reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
36   -
37   - ack_pmu_message_recieve();
38   -
39   - return reg;
40   -}
41   -
42   -static inline unsigned int get_stream_message(void)
43   -{
44   - unsigned int reg, reg2;
45   -
46   - poll_pmu_message_ready();
47   -
48   - reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
49   -
50   - reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034);
51   -
52   - reg2 = (reg2 << 16) | reg;
53   -
54   - ack_pmu_message_recieve();
55   -
56   - return reg2;
57   -}
58   -
59   -static inline void decode_major_message(unsigned int mail)
60   -{
61   - ddr_printf("[PMU Major message = 0x%08x]\n", mail);
62   -}
63   -
64   -static inline void decode_streaming_message(void)
65   -{
66   - unsigned int string_index, arg __maybe_unused;
67   - int i = 0;
68   -
69   - string_index = get_stream_message();
70   - ddr_printf(" PMU String index = 0x%08x\n", string_index);
71   - while (i < (string_index & 0xffff)){
72   - arg = get_stream_message();
73   - ddr_printf(" arg[%d] = 0x%08x\n", i, arg);
74   - i++;
75   - }
76   -
77   - ddr_printf("\n");
78   -}
79   -
80   -void wait_ddrphy_training_complete(void)
81   -{
82   - unsigned int mail;
83   - while (1) {
84   - mail = get_mail();
85   - decode_major_message(mail);
86   - if (mail == 0x08) {
87   - decode_streaming_message();
88   - } else if (mail == 0x07) {
89   - printf("Training PASS\n");
90   - break;
91   - } else if (mail == 0xff) {
92   - printf("Training FAILED\n");
93   - break;
94   - }
95   - }
96   -}
board/freescale/imx8mq_aiy/lpddr4_timing_3g.c
Diff comments   View file @ 63dbfc0
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Generated code from MX8M_DDR_tool
  7 + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
  8 + */
  9 +
  10 +#include <linux/kernel.h>
  11 +#include <asm/arch/imx8m_ddr.h>
  12 +
  13 +struct dram_cfg_param ddr_ddrc_cfg[] = {
  14 + /** Initialize DDRC registers **/
  15 + {0x3d400304,0x1},
  16 + {0x3d400030,0x1},
  17 + {0x3d400000,0xa3080020},
  18 + {0x3d400028,0x0},
  19 + {0x3d400020,0x203},
  20 + {0x3d400024,0x3e800},
  21 + {0x3d400064,0x6100e0},
  22 + {0x3d4000d0,0xc003061c},
  23 + {0x3d4000d4,0x9e0000},
  24 + {0x3d4000dc,0xd4002d},
  25 + {0x3d4000e0,0x310008},
  26 + {0x3d4000e8,0x66004a},
  27 + {0x3d4000ec,0x16004a},
  28 + {0x3d400100,0x1a201b22},
  29 + {0x3d400104,0x60633},
  30 + {0x3d40010c,0xc0c000},
  31 + {0x3d400110,0xf04080f},
  32 + {0x3d400114,0x2040c0c},
  33 + {0x3d400118,0x1010007},
  34 + {0x3d40011c,0x401},
  35 + {0x3d400130,0x20600},
  36 + {0x3d400134,0xc100002},
  37 + {0x3d400138,0xe6},
  38 + {0x3d400144,0xa00050},
  39 + {0x3d400180,0xc3200018},
  40 + {0x3d400184,0x28061a8},
  41 + {0x3d400188,0x0},
  42 + {0x3d400190,0x497820a},
  43 + {0x3d400194,0x80303},
  44 + {0x3d4001a0,0xe0400018},
  45 + {0x3d4001a4,0xdf00e4},
  46 + {0x3d4001a8,0x80000000},
  47 + {0x3d4001b0,0x11},
  48 + {0x3d4001b4,0x170a},
  49 + {0x3d4001c0,0x1},
  50 + {0x3d4001c4,0x1},
  51 + {0x3d4000f4,0x639},
  52 + {0x3d400108,0x70e1617},
  53 + {0x3d400200,0x15},
  54 + {0x3d40020c,0x0},
  55 + {0x3d400210,0x1f1f},
  56 + {0x3d400204,0x80808},
  57 + {0x3d400214,0x7070707},
  58 + {0x3d400218,0x48080707},
  59 + {0x3d402020,0x1},
  60 + {0x3d402024,0xd0c0},
  61 + {0x3d402050,0x20d040},
  62 + {0x3d402064,0x14002f},
  63 + {0x3d4020dc,0x940009},
  64 + {0x3d4020e0,0x310000},
  65 + {0x3d4020e8,0x66004a},
  66 + {0x3d4020ec,0x16004a},
  67 + {0x3d402100,0xb070508},
  68 + {0x3d402104,0x3040b},
  69 + {0x3d402108,0x305090c},
  70 + {0x3d40210c,0x505000},
  71 + {0x3d402110,0x4040204},
  72 + {0x3d402114,0x2030303},
  73 + {0x3d402118,0x1010004},
  74 + {0x3d40211c,0x301},
  75 + {0x3d402130,0x20300},
  76 + {0x3d402134,0xa100002},
  77 + {0x3d402138,0x31},
  78 + {0x3d402144,0x220011},
  79 + {0x3d402180,0xc0a70006},
  80 + {0x3d402190,0x3858202},
  81 + {0x3d402194,0x80303},
  82 + {0x3d4021b4,0x502},
  83 + {0x3d400244,0x0},
  84 + {0x3d400250,0x29001505},
  85 + {0x3d400254,0x2c},
  86 + {0x3d40025c,0x5900575b},
  87 + {0x3d400264,0x90000096},
  88 + {0x3d40026c,0x1000012c},
  89 + {0x3d400300,0x16},
  90 + {0x3d400304,0x0},
  91 + {0x3d40030c,0x0},
  92 + {0x3d400320,0x1},
  93 + {0x3d40036c,0x11},
  94 + {0x3d400400,0x111},
  95 + {0x3d400404,0x10f3},
  96 + {0x3d400408,0x72ff},
  97 + {0x3d400490,0x1},
  98 + {0x3d400494,0xe00},
  99 + {0x3d400498,0x62ffff},
  100 + {0x3d40049c,0xe00},
  101 + {0x3d4004a0,0xffff},
  102 +};
  103 +
  104 +/* PHY Initialize Configuration */
  105 +struct dram_cfg_param ddr_ddrphy_cfg[] = {
  106 + {0x100a0,0x0},
  107 + {0x100a1,0x1},
  108 + {0x100a2,0x2},
  109 + {0x100a3,0x3},
  110 + {0x100a4,0x4},
  111 + {0x100a5,0x5},
  112 + {0x100a6,0x6},
  113 + {0x100a7,0x7},
  114 + {0x110a0,0x0},
  115 + {0x110a1,0x1},
  116 + {0x110a2,0x2},
  117 + {0x110a3,0x3},
  118 + {0x110a4,0x4},
  119 + {0x110a5,0x5},
  120 + {0x110a6,0x6},
  121 + {0x110a7,0x7},
  122 + {0x120a0,0x0},
  123 + {0x120a1,0x1},
  124 + {0x120a2,0x2},
  125 + {0x120a3,0x3},
  126 + {0x120a4,0x4},
  127 + {0x120a5,0x5},
  128 + {0x120a6,0x6},
  129 + {0x120a7,0x7},
  130 + {0x130a0,0x0},
  131 + {0x130a1,0x1},
  132 + {0x130a2,0x2},
  133 + {0x130a3,0x3},
  134 + {0x130a4,0x4},
  135 + {0x130a5,0x5},
  136 + {0x130a6,0x6},
  137 + {0x130a7,0x7},
  138 + {0x20110,0x2},
  139 + {0x20111,0x3},
  140 + {0x20112,0x4},
  141 + {0x20113,0x5},
  142 + {0x20114,0x0},
  143 + {0x20115,0x1},
  144 + {0x1005f,0x1ff},
  145 + {0x1015f,0x1ff},
  146 + {0x1105f,0x1ff},
  147 + {0x1115f,0x1ff},
  148 + {0x1205f,0x1ff},
  149 + {0x1215f,0x1ff},
  150 + {0x1305f,0x1ff},
  151 + {0x1315f,0x1ff},
  152 + {0x11005f,0x1ff},
  153 + {0x11015f,0x1ff},
  154 + {0x11105f,0x1ff},
  155 + {0x11115f,0x1ff},
  156 + {0x11205f,0x1ff},
  157 + {0x11215f,0x1ff},
  158 + {0x11305f,0x1ff},
  159 + {0x11315f,0x1ff},
  160 + {0x55,0x1ff},
  161 + {0x1055,0x1ff},
  162 + {0x2055,0x1ff},
  163 + {0x3055,0x1ff},
  164 + {0x4055,0x1ff},
  165 + {0x5055,0x1ff},
  166 + {0x6055,0x1ff},
  167 + {0x7055,0x1ff},
  168 + {0x8055,0x1ff},
  169 + {0x9055,0x1ff},
  170 + {0x200c5,0x19},
  171 + {0x1200c5,0x7},
  172 + {0x2002e,0x2},
  173 + {0x12002e,0x1},
  174 + {0x90204,0x0},
  175 + {0x190204,0x0},
  176 + {0x20024,0x1ab},
  177 + {0x2003a,0x0},
  178 + {0x120024,0x1ab},
  179 + {0x2003a,0x0},
  180 + {0x20056,0x3},
  181 + {0x120056,0xa},
  182 + {0x1004d,0xe00},
  183 + {0x1014d,0xe00},
  184 + {0x1104d,0xe00},
  185 + {0x1114d,0xe00},
  186 + {0x1204d,0xe00},
  187 + {0x1214d,0xe00},
  188 + {0x1304d,0xe00},
  189 + {0x1314d,0xe00},
  190 + {0x11004d,0xe00},
  191 + {0x11014d,0xe00},
  192 + {0x11104d,0xe00},
  193 + {0x11114d,0xe00},
  194 + {0x11204d,0xe00},
  195 + {0x11214d,0xe00},
  196 + {0x11304d,0xe00},
  197 + {0x11314d,0xe00},
  198 + {0x10049,0xeba},
  199 + {0x10149,0xeba},
  200 + {0x11049,0xeba},
  201 + {0x11149,0xeba},
  202 + {0x12049,0xeba},
  203 + {0x12149,0xeba},
  204 + {0x13049,0xeba},
  205 + {0x13149,0xeba},
  206 + {0x110049,0xeba},
  207 + {0x110149,0xeba},
  208 + {0x111049,0xeba},
  209 + {0x111149,0xeba},
  210 + {0x112049,0xeba},
  211 + {0x112149,0xeba},
  212 + {0x113049,0xeba},
  213 + {0x113149,0xeba},
  214 + {0x43,0x63},
  215 + {0x1043,0x63},
  216 + {0x2043,0x63},
  217 + {0x3043,0x63},
  218 + {0x4043,0x63},
  219 + {0x5043,0x63},
  220 + {0x6043,0x63},
  221 + {0x7043,0x63},
  222 + {0x8043,0x63},
  223 + {0x9043,0x63},
  224 + {0x20018,0x3},
  225 + {0x20075,0x4},
  226 + {0x20050,0x0},
  227 + {0x20008,0x320},
  228 + {0x120008,0xa7},
  229 + {0x20088,0x9},
  230 + {0x200b2,0xdc},
  231 + {0x10043,0x5a1},
  232 + {0x10143,0x5a1},
  233 + {0x11043,0x5a1},
  234 + {0x11143,0x5a1},
  235 + {0x12043,0x5a1},
  236 + {0x12143,0x5a1},
  237 + {0x13043,0x5a1},
  238 + {0x13143,0x5a1},
  239 + {0x1200b2,0xdc},
  240 + {0x110043,0x5a1},
  241 + {0x110143,0x5a1},
  242 + {0x111043,0x5a1},
  243 + {0x111143,0x5a1},
  244 + {0x112043,0x5a1},
  245 + {0x112143,0x5a1},
  246 + {0x113043,0x5a1},
  247 + {0x113143,0x5a1},
  248 + {0x200fa,0x1},
  249 + {0x1200fa,0x1},
  250 + {0x20019,0x1},
  251 + {0x120019,0x1},
  252 + {0x200f0,0x0},
  253 + {0x200f1,0x0},
  254 + {0x200f2,0x4444},
  255 + {0x200f3,0x8888},
  256 + {0x200f4,0x5555},
  257 + {0x200f5,0x0},
  258 + {0x200f6,0x0},
  259 + {0x200f7,0xf000},
  260 + {0x20025,0x0},
  261 + {0x2002d,0x0},
  262 + {0x12002d,0x0},
  263 + {0x200c7,0x80},
  264 + {0x1200c7,0x80},
  265 + {0x200ca,0x106},
  266 + {0x1200ca,0x106},
  267 +};
  268 +
  269 +/* ddr phy trained csr */
  270 +struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
  271 + { 0x200b2, 0x0 },
  272 + { 0x1200b2, 0x0 },
  273 + { 0x2200b2, 0x0 },
  274 + { 0x200cb, 0x0 },
  275 + { 0x10043, 0x0 },
  276 + { 0x110043, 0x0 },
  277 + { 0x210043, 0x0 },
  278 + { 0x10143, 0x0 },
  279 + { 0x110143, 0x0 },
  280 + { 0x210143, 0x0 },
  281 + { 0x11043, 0x0 },
  282 + { 0x111043, 0x0 },
  283 + { 0x211043, 0x0 },
  284 + { 0x11143, 0x0 },
  285 + { 0x111143, 0x0 },
  286 + { 0x211143, 0x0 },
  287 + { 0x12043, 0x0 },
  288 + { 0x112043, 0x0 },
  289 + { 0x212043, 0x0 },
  290 + { 0x12143, 0x0 },
  291 + { 0x112143, 0x0 },
  292 + { 0x212143, 0x0 },
  293 + { 0x13043, 0x0 },
  294 + { 0x113043, 0x0 },
  295 + { 0x213043, 0x0 },
  296 + { 0x13143, 0x0 },
  297 + { 0x113143, 0x0 },
  298 + { 0x213143, 0x0 },
  299 + { 0x80, 0x0 },
  300 + { 0x100080, 0x0 },
  301 + { 0x200080, 0x0 },
  302 + { 0x1080, 0x0 },
  303 + { 0x101080, 0x0 },
  304 + { 0x201080, 0x0 },
  305 + { 0x2080, 0x0 },
  306 + { 0x102080, 0x0 },
  307 + { 0x202080, 0x0 },
  308 + { 0x3080, 0x0 },
  309 + { 0x103080, 0x0 },
  310 + { 0x203080, 0x0 },
  311 + { 0x4080, 0x0 },
  312 + { 0x104080, 0x0 },
  313 + { 0x204080, 0x0 },
  314 + { 0x5080, 0x0 },
  315 + { 0x105080, 0x0 },
  316 + { 0x205080, 0x0 },
  317 + { 0x6080, 0x0 },
  318 + { 0x106080, 0x0 },
  319 + { 0x206080, 0x0 },
  320 + { 0x7080, 0x0 },
  321 + { 0x107080, 0x0 },
  322 + { 0x207080, 0x0 },
  323 + { 0x8080, 0x0 },
  324 + { 0x108080, 0x0 },
  325 + { 0x208080, 0x0 },
  326 + { 0x9080, 0x0 },
  327 + { 0x109080, 0x0 },
  328 + { 0x209080, 0x0 },
  329 + { 0x10080, 0x0 },
  330 + { 0x110080, 0x0 },
  331 + { 0x210080, 0x0 },
  332 + { 0x10180, 0x0 },
  333 + { 0x110180, 0x0 },
  334 + { 0x210180, 0x0 },
  335 + { 0x11080, 0x0 },
  336 + { 0x111080, 0x0 },
  337 + { 0x211080, 0x0 },
  338 + { 0x11180, 0x0 },
  339 + { 0x111180, 0x0 },
  340 + { 0x211180, 0x0 },
  341 + { 0x12080, 0x0 },
  342 + { 0x112080, 0x0 },
  343 + { 0x212080, 0x0 },
  344 + { 0x12180, 0x0 },
  345 + { 0x112180, 0x0 },
  346 + { 0x212180, 0x0 },
  347 + { 0x13080, 0x0 },
  348 + { 0x113080, 0x0 },
  349 + { 0x213080, 0x0 },
  350 + { 0x13180, 0x0 },
  351 + { 0x113180, 0x0 },
  352 + { 0x213180, 0x0 },
  353 + { 0x10081, 0x0 },
  354 + { 0x110081, 0x0 },
  355 + { 0x210081, 0x0 },
  356 + { 0x10181, 0x0 },
  357 + { 0x110181, 0x0 },
  358 + { 0x210181, 0x0 },
  359 + { 0x11081, 0x0 },
  360 + { 0x111081, 0x0 },
  361 + { 0x211081, 0x0 },
  362 + { 0x11181, 0x0 },
  363 + { 0x111181, 0x0 },
  364 + { 0x211181, 0x0 },
  365 + { 0x12081, 0x0 },
  366 + { 0x112081, 0x0 },
  367 + { 0x212081, 0x0 },
  368 + { 0x12181, 0x0 },
  369 + { 0x112181, 0x0 },
  370 + { 0x212181, 0x0 },
  371 + { 0x13081, 0x0 },
  372 + { 0x113081, 0x0 },
  373 + { 0x213081, 0x0 },
  374 + { 0x13181, 0x0 },
  375 + { 0x113181, 0x0 },
  376 + { 0x213181, 0x0 },
  377 + { 0x100d0, 0x0 },
  378 + { 0x1100d0, 0x0 },
  379 + { 0x2100d0, 0x0 },
  380 + { 0x101d0, 0x0 },
  381 + { 0x1101d0, 0x0 },
  382 + { 0x2101d0, 0x0 },
  383 + { 0x110d0, 0x0 },
  384 + { 0x1110d0, 0x0 },
  385 + { 0x2110d0, 0x0 },
  386 + { 0x111d0, 0x0 },
  387 + { 0x1111d0, 0x0 },
  388 + { 0x2111d0, 0x0 },
  389 + { 0x120d0, 0x0 },
  390 + { 0x1120d0, 0x0 },
  391 + { 0x2120d0, 0x0 },
  392 + { 0x121d0, 0x0 },
  393 + { 0x1121d0, 0x0 },
  394 + { 0x2121d0, 0x0 },
  395 + { 0x130d0, 0x0 },
  396 + { 0x1130d0, 0x0 },
  397 + { 0x2130d0, 0x0 },
  398 + { 0x131d0, 0x0 },
  399 + { 0x1131d0, 0x0 },
  400 + { 0x2131d0, 0x0 },
  401 + { 0x100d1, 0x0 },
  402 + { 0x1100d1, 0x0 },
  403 + { 0x2100d1, 0x0 },
  404 + { 0x101d1, 0x0 },
  405 + { 0x1101d1, 0x0 },
  406 + { 0x2101d1, 0x0 },
  407 + { 0x110d1, 0x0 },
  408 + { 0x1110d1, 0x0 },
  409 + { 0x2110d1, 0x0 },
  410 + { 0x111d1, 0x0 },
  411 + { 0x1111d1, 0x0 },
  412 + { 0x2111d1, 0x0 },
  413 + { 0x120d1, 0x0 },
  414 + { 0x1120d1, 0x0 },
  415 + { 0x2120d1, 0x0 },
  416 + { 0x121d1, 0x0 },
  417 + { 0x1121d1, 0x0 },
  418 + { 0x2121d1, 0x0 },
  419 + { 0x130d1, 0x0 },
  420 + { 0x1130d1, 0x0 },
  421 + { 0x2130d1, 0x0 },
  422 + { 0x131d1, 0x0 },
  423 + { 0x1131d1, 0x0 },
  424 + { 0x2131d1, 0x0 },
  425 + { 0x10068, 0x0 },
  426 + { 0x10168, 0x0 },
  427 + { 0x10268, 0x0 },
  428 + { 0x10368, 0x0 },
  429 + { 0x10468, 0x0 },
  430 + { 0x10568, 0x0 },
  431 + { 0x10668, 0x0 },
  432 + { 0x10768, 0x0 },
  433 + { 0x10868, 0x0 },
  434 + { 0x11068, 0x0 },
  435 + { 0x11168, 0x0 },
  436 + { 0x11268, 0x0 },
  437 + { 0x11368, 0x0 },
  438 + { 0x11468, 0x0 },
  439 + { 0x11568, 0x0 },
  440 + { 0x11668, 0x0 },
  441 + { 0x11768, 0x0 },
  442 + { 0x11868, 0x0 },
  443 + { 0x12068, 0x0 },
  444 + { 0x12168, 0x0 },
  445 + { 0x12268, 0x0 },
  446 + { 0x12368, 0x0 },
  447 + { 0x12468, 0x0 },
  448 + { 0x12568, 0x0 },
  449 + { 0x12668, 0x0 },
  450 + { 0x12768, 0x0 },
  451 + { 0x12868, 0x0 },
  452 + { 0x13068, 0x0 },
  453 + { 0x13168, 0x0 },
  454 + { 0x13268, 0x0 },
  455 + { 0x13368, 0x0 },
  456 + { 0x13468, 0x0 },
  457 + { 0x13568, 0x0 },
  458 + { 0x13668, 0x0 },
  459 + { 0x13768, 0x0 },
  460 + { 0x13868, 0x0 },
  461 + { 0x10069, 0x0 },
  462 + { 0x10169, 0x0 },
  463 + { 0x10269, 0x0 },
  464 + { 0x10369, 0x0 },
  465 + { 0x10469, 0x0 },
  466 + { 0x10569, 0x0 },
  467 + { 0x10669, 0x0 },
  468 + { 0x10769, 0x0 },
  469 + { 0x10869, 0x0 },
  470 + { 0x11069, 0x0 },
  471 + { 0x11169, 0x0 },
  472 + { 0x11269, 0x0 },
  473 + { 0x11369, 0x0 },
  474 + { 0x11469, 0x0 },
  475 + { 0x11569, 0x0 },
  476 + { 0x11669, 0x0 },
  477 + { 0x11769, 0x0 },
  478 + { 0x11869, 0x0 },
  479 + { 0x12069, 0x0 },
  480 + { 0x12169, 0x0 },
  481 + { 0x12269, 0x0 },
  482 + { 0x12369, 0x0 },
  483 + { 0x12469, 0x0 },
  484 + { 0x12569, 0x0 },
  485 + { 0x12669, 0x0 },
  486 + { 0x12769, 0x0 },
  487 + { 0x12869, 0x0 },
  488 + { 0x13069, 0x0 },
  489 + { 0x13169, 0x0 },
  490 + { 0x13269, 0x0 },
  491 + { 0x13369, 0x0 },
  492 + { 0x13469, 0x0 },
  493 + { 0x13569, 0x0 },
  494 + { 0x13669, 0x0 },
  495 + { 0x13769, 0x0 },
  496 + { 0x13869, 0x0 },
  497 + { 0x1008c, 0x0 },
  498 + { 0x11008c, 0x0 },
  499 + { 0x21008c, 0x0 },
  500 + { 0x1018c, 0x0 },
  501 + { 0x11018c, 0x0 },
  502 + { 0x21018c, 0x0 },
  503 + { 0x1108c, 0x0 },
  504 + { 0x11108c, 0x0 },
  505 + { 0x21108c, 0x0 },
  506 + { 0x1118c, 0x0 },
  507 + { 0x11118c, 0x0 },
  508 + { 0x21118c, 0x0 },
  509 + { 0x1208c, 0x0 },
  510 + { 0x11208c, 0x0 },
  511 + { 0x21208c, 0x0 },
  512 + { 0x1218c, 0x0 },
  513 + { 0x11218c, 0x0 },
  514 + { 0x21218c, 0x0 },
  515 + { 0x1308c, 0x0 },
  516 + { 0x11308c, 0x0 },
  517 + { 0x21308c, 0x0 },
  518 + { 0x1318c, 0x0 },
  519 + { 0x11318c, 0x0 },
  520 + { 0x21318c, 0x0 },
  521 + { 0x1008d, 0x0 },
  522 + { 0x11008d, 0x0 },
  523 + { 0x21008d, 0x0 },
  524 + { 0x1018d, 0x0 },
  525 + { 0x11018d, 0x0 },
  526 + { 0x21018d, 0x0 },
  527 + { 0x1108d, 0x0 },
  528 + { 0x11108d, 0x0 },
  529 + { 0x21108d, 0x0 },
  530 + { 0x1118d, 0x0 },
  531 + { 0x11118d, 0x0 },
  532 + { 0x21118d, 0x0 },
  533 + { 0x1208d, 0x0 },
  534 + { 0x11208d, 0x0 },
  535 + { 0x21208d, 0x0 },
  536 + { 0x1218d, 0x0 },
  537 + { 0x11218d, 0x0 },
  538 + { 0x21218d, 0x0 },
  539 + { 0x1308d, 0x0 },
  540 + { 0x11308d, 0x0 },
  541 + { 0x21308d, 0x0 },
  542 + { 0x1318d, 0x0 },
  543 + { 0x11318d, 0x0 },
  544 + { 0x21318d, 0x0 },
  545 + { 0x100c0, 0x0 },
  546 + { 0x1100c0, 0x0 },
  547 + { 0x2100c0, 0x0 },
  548 + { 0x101c0, 0x0 },
  549 + { 0x1101c0, 0x0 },
  550 + { 0x2101c0, 0x0 },
  551 + { 0x102c0, 0x0 },
  552 + { 0x1102c0, 0x0 },
  553 + { 0x2102c0, 0x0 },
  554 + { 0x103c0, 0x0 },
  555 + { 0x1103c0, 0x0 },
  556 + { 0x2103c0, 0x0 },
  557 + { 0x104c0, 0x0 },
  558 + { 0x1104c0, 0x0 },
  559 + { 0x2104c0, 0x0 },
  560 + { 0x105c0, 0x0 },
  561 + { 0x1105c0, 0x0 },
  562 + { 0x2105c0, 0x0 },
  563 + { 0x106c0, 0x0 },
  564 + { 0x1106c0, 0x0 },
  565 + { 0x2106c0, 0x0 },
  566 + { 0x107c0, 0x0 },
  567 + { 0x1107c0, 0x0 },
  568 + { 0x2107c0, 0x0 },
  569 + { 0x108c0, 0x0 },
  570 + { 0x1108c0, 0x0 },
  571 + { 0x2108c0, 0x0 },
  572 + { 0x110c0, 0x0 },
  573 + { 0x1110c0, 0x0 },
  574 + { 0x2110c0, 0x0 },
  575 + { 0x111c0, 0x0 },
  576 + { 0x1111c0, 0x0 },
  577 + { 0x2111c0, 0x0 },
  578 + { 0x112c0, 0x0 },
  579 + { 0x1112c0, 0x0 },
  580 + { 0x2112c0, 0x0 },
  581 + { 0x113c0, 0x0 },
  582 + { 0x1113c0, 0x0 },
  583 + { 0x2113c0, 0x0 },
  584 + { 0x114c0, 0x0 },
  585 + { 0x1114c0, 0x0 },
  586 + { 0x2114c0, 0x0 },
  587 + { 0x115c0, 0x0 },
  588 + { 0x1115c0, 0x0 },
  589 + { 0x2115c0, 0x0 },
  590 + { 0x116c0, 0x0 },
  591 + { 0x1116c0, 0x0 },
  592 + { 0x2116c0, 0x0 },
  593 + { 0x117c0, 0x0 },
  594 + { 0x1117c0, 0x0 },
  595 + { 0x2117c0, 0x0 },
  596 + { 0x118c0, 0x0 },
  597 + { 0x1118c0, 0x0 },
  598 + { 0x2118c0, 0x0 },
  599 + { 0x120c0, 0x0 },
  600 + { 0x1120c0, 0x0 },
  601 + { 0x2120c0, 0x0 },
  602 + { 0x121c0, 0x0 },
  603 + { 0x1121c0, 0x0 },
  604 + { 0x2121c0, 0x0 },
  605 + { 0x122c0, 0x0 },
  606 + { 0x1122c0, 0x0 },
  607 + { 0x2122c0, 0x0 },
  608 + { 0x123c0, 0x0 },
  609 + { 0x1123c0, 0x0 },
  610 + { 0x2123c0, 0x0 },
  611 + { 0x124c0, 0x0 },
  612 + { 0x1124c0, 0x0 },
  613 + { 0x2124c0, 0x0 },
  614 + { 0x125c0, 0x0 },
  615 + { 0x1125c0, 0x0 },
  616 + { 0x2125c0, 0x0 },
  617 + { 0x126c0, 0x0 },
  618 + { 0x1126c0, 0x0 },
  619 + { 0x2126c0, 0x0 },
  620 + { 0x127c0, 0x0 },
  621 + { 0x1127c0, 0x0 },
  622 + { 0x2127c0, 0x0 },
  623 + { 0x128c0, 0x0 },
  624 + { 0x1128c0, 0x0 },
  625 + { 0x2128c0, 0x0 },
  626 + { 0x130c0, 0x0 },
  627 + { 0x1130c0, 0x0 },
  628 + { 0x2130c0, 0x0 },
  629 + { 0x131c0, 0x0 },
  630 + { 0x1131c0, 0x0 },
  631 + { 0x2131c0, 0x0 },
  632 + { 0x132c0, 0x0 },
  633 + { 0x1132c0, 0x0 },
  634 + { 0x2132c0, 0x0 },
  635 + { 0x133c0, 0x0 },
  636 + { 0x1133c0, 0x0 },
  637 + { 0x2133c0, 0x0 },
  638 + { 0x134c0, 0x0 },
  639 + { 0x1134c0, 0x0 },
  640 + { 0x2134c0, 0x0 },
  641 + { 0x135c0, 0x0 },
  642 + { 0x1135c0, 0x0 },
  643 + { 0x2135c0, 0x0 },
  644 + { 0x136c0, 0x0 },
  645 + { 0x1136c0, 0x0 },
  646 + { 0x2136c0, 0x0 },
  647 + { 0x137c0, 0x0 },
  648 + { 0x1137c0, 0x0 },
  649 + { 0x2137c0, 0x0 },
  650 + { 0x138c0, 0x0 },
  651 + { 0x1138c0, 0x0 },
  652 + { 0x2138c0, 0x0 },
  653 + { 0x100c1, 0x0 },
  654 + { 0x1100c1, 0x0 },
  655 + { 0x2100c1, 0x0 },
  656 + { 0x101c1, 0x0 },
  657 + { 0x1101c1, 0x0 },
  658 + { 0x2101c1, 0x0 },
  659 + { 0x102c1, 0x0 },
  660 + { 0x1102c1, 0x0 },
  661 + { 0x2102c1, 0x0 },
  662 + { 0x103c1, 0x0 },
  663 + { 0x1103c1, 0x0 },
  664 + { 0x2103c1, 0x0 },
  665 + { 0x104c1, 0x0 },
  666 + { 0x1104c1, 0x0 },
  667 + { 0x2104c1, 0x0 },
  668 + { 0x105c1, 0x0 },
  669 + { 0x1105c1, 0x0 },
  670 + { 0x2105c1, 0x0 },
  671 + { 0x106c1, 0x0 },
  672 + { 0x1106c1, 0x0 },
  673 + { 0x2106c1, 0x0 },
  674 + { 0x107c1, 0x0 },
  675 + { 0x1107c1, 0x0 },
  676 + { 0x2107c1, 0x0 },
  677 + { 0x108c1, 0x0 },
  678 + { 0x1108c1, 0x0 },
  679 + { 0x2108c1, 0x0 },
  680 + { 0x110c1, 0x0 },
  681 + { 0x1110c1, 0x0 },
  682 + { 0x2110c1, 0x0 },
  683 + { 0x111c1, 0x0 },
  684 + { 0x1111c1, 0x0 },
  685 + { 0x2111c1, 0x0 },
  686 + { 0x112c1, 0x0 },
  687 + { 0x1112c1, 0x0 },
  688 + { 0x2112c1, 0x0 },
  689 + { 0x113c1, 0x0 },
  690 + { 0x1113c1, 0x0 },
  691 + { 0x2113c1, 0x0 },
  692 + { 0x114c1, 0x0 },
  693 + { 0x1114c1, 0x0 },
  694 + { 0x2114c1, 0x0 },
  695 + { 0x115c1, 0x0 },
  696 + { 0x1115c1, 0x0 },
  697 + { 0x2115c1, 0x0 },
  698 + { 0x116c1, 0x0 },
  699 + { 0x1116c1, 0x0 },
  700 + { 0x2116c1, 0x0 },
  701 + { 0x117c1, 0x0 },
  702 + { 0x1117c1, 0x0 },
  703 + { 0x2117c1, 0x0 },
  704 + { 0x118c1, 0x0 },
  705 + { 0x1118c1, 0x0 },
  706 + { 0x2118c1, 0x0 },
  707 + { 0x120c1, 0x0 },
  708 + { 0x1120c1, 0x0 },
  709 + { 0x2120c1, 0x0 },
  710 + { 0x121c1, 0x0 },
  711 + { 0x1121c1, 0x0 },
  712 + { 0x2121c1, 0x0 },
  713 + { 0x122c1, 0x0 },
  714 + { 0x1122c1, 0x0 },
  715 + { 0x2122c1, 0x0 },
  716 + { 0x123c1, 0x0 },
  717 + { 0x1123c1, 0x0 },
  718 + { 0x2123c1, 0x0 },
  719 + { 0x124c1, 0x0 },
  720 + { 0x1124c1, 0x0 },
  721 + { 0x2124c1, 0x0 },
  722 + { 0x125c1, 0x0 },
  723 + { 0x1125c1, 0x0 },
  724 + { 0x2125c1, 0x0 },
  725 + { 0x126c1, 0x0 },
  726 + { 0x1126c1, 0x0 },
  727 + { 0x2126c1, 0x0 },
  728 + { 0x127c1, 0x0 },
  729 + { 0x1127c1, 0x0 },
  730 + { 0x2127c1, 0x0 },
  731 + { 0x128c1, 0x0 },
  732 + { 0x1128c1, 0x0 },
  733 + { 0x2128c1, 0x0 },
  734 + { 0x130c1, 0x0 },
  735 + { 0x1130c1, 0x0 },
  736 + { 0x2130c1, 0x0 },
  737 + { 0x131c1, 0x0 },
  738 + { 0x1131c1, 0x0 },
  739 + { 0x2131c1, 0x0 },
  740 + { 0x132c1, 0x0 },
  741 + { 0x1132c1, 0x0 },
  742 + { 0x2132c1, 0x0 },
  743 + { 0x133c1, 0x0 },
  744 + { 0x1133c1, 0x0 },
  745 + { 0x2133c1, 0x0 },
  746 + { 0x134c1, 0x0 },
  747 + { 0x1134c1, 0x0 },
  748 + { 0x2134c1, 0x0 },
  749 + { 0x135c1, 0x0 },
  750 + { 0x1135c1, 0x0 },
  751 + { 0x2135c1, 0x0 },
  752 + { 0x136c1, 0x0 },
  753 + { 0x1136c1, 0x0 },
  754 + { 0x2136c1, 0x0 },
  755 + { 0x137c1, 0x0 },
  756 + { 0x1137c1, 0x0 },
  757 + { 0x2137c1, 0x0 },
  758 + { 0x138c1, 0x0 },
  759 + { 0x1138c1, 0x0 },
  760 + { 0x2138c1, 0x0 },
  761 + { 0x10020, 0x0 },
  762 + { 0x110020, 0x0 },
  763 + { 0x210020, 0x0 },
  764 + { 0x11020, 0x0 },
  765 + { 0x111020, 0x0 },
  766 + { 0x211020, 0x0 },
  767 + { 0x12020, 0x0 },
  768 + { 0x112020, 0x0 },
  769 + { 0x212020, 0x0 },
  770 + { 0x13020, 0x0 },
  771 + { 0x113020, 0x0 },
  772 + { 0x213020, 0x0 },
  773 + { 0x20072, 0x0 },
  774 + { 0x20073, 0x0 },
  775 + { 0x20074, 0x0 },
  776 + { 0x100aa, 0x0 },
  777 + { 0x110aa, 0x0 },
  778 + { 0x120aa, 0x0 },
  779 + { 0x130aa, 0x0 },
  780 + { 0x20010, 0x0 },
  781 + { 0x120010, 0x0 },
  782 + { 0x220010, 0x0 },
  783 + { 0x20011, 0x0 },
  784 + { 0x120011, 0x0 },
  785 + { 0x220011, 0x0 },
  786 + { 0x100ae, 0x0 },
  787 + { 0x1100ae, 0x0 },
  788 + { 0x2100ae, 0x0 },
  789 + { 0x100af, 0x0 },
  790 + { 0x1100af, 0x0 },
  791 + { 0x2100af, 0x0 },
  792 + { 0x110ae, 0x0 },
  793 + { 0x1110ae, 0x0 },
  794 + { 0x2110ae, 0x0 },
  795 + { 0x110af, 0x0 },
  796 + { 0x1110af, 0x0 },
  797 + { 0x2110af, 0x0 },
  798 + { 0x120ae, 0x0 },
  799 + { 0x1120ae, 0x0 },
  800 + { 0x2120ae, 0x0 },
  801 + { 0x120af, 0x0 },
  802 + { 0x1120af, 0x0 },
  803 + { 0x2120af, 0x0 },
  804 + { 0x130ae, 0x0 },
  805 + { 0x1130ae, 0x0 },
  806 + { 0x2130ae, 0x0 },
  807 + { 0x130af, 0x0 },
  808 + { 0x1130af, 0x0 },
  809 + { 0x2130af, 0x0 },
  810 + { 0x20020, 0x0 },
  811 + { 0x120020, 0x0 },
  812 + { 0x220020, 0x0 },
  813 + { 0x100a0, 0x0 },
  814 + { 0x100a1, 0x0 },
  815 + { 0x100a2, 0x0 },
  816 + { 0x100a3, 0x0 },
  817 + { 0x100a4, 0x0 },
  818 + { 0x100a5, 0x0 },
  819 + { 0x100a6, 0x0 },
  820 + { 0x100a7, 0x0 },
  821 + { 0x110a0, 0x0 },
  822 + { 0x110a1, 0x0 },
  823 + { 0x110a2, 0x0 },
  824 + { 0x110a3, 0x0 },
  825 + { 0x110a4, 0x0 },
  826 + { 0x110a5, 0x0 },
  827 + { 0x110a6, 0x0 },
  828 + { 0x110a7, 0x0 },
  829 + { 0x120a0, 0x0 },
  830 + { 0x120a1, 0x0 },
  831 + { 0x120a2, 0x0 },
  832 + { 0x120a3, 0x0 },
  833 + { 0x120a4, 0x0 },
  834 + { 0x120a5, 0x0 },
  835 + { 0x120a6, 0x0 },
  836 + { 0x120a7, 0x0 },
  837 + { 0x130a0, 0x0 },
  838 + { 0x130a1, 0x0 },
  839 + { 0x130a2, 0x0 },
  840 + { 0x130a3, 0x0 },
  841 + { 0x130a4, 0x0 },
  842 + { 0x130a5, 0x0 },
  843 + { 0x130a6, 0x0 },
  844 + { 0x130a7, 0x0 },
  845 + { 0x2007c, 0x0 },
  846 + { 0x12007c, 0x0 },
  847 + { 0x22007c, 0x0 },
  848 + { 0x2007d, 0x0 },
  849 + { 0x12007d, 0x0 },
  850 + { 0x22007d, 0x0 },
  851 + { 0x400fd, 0x0 },
  852 + { 0x400c0, 0x0 },
  853 + { 0x90201, 0x0 },
  854 + { 0x190201, 0x0 },
  855 + { 0x290201, 0x0 },
  856 + { 0x90202, 0x0 },
  857 + { 0x190202, 0x0 },
  858 + { 0x290202, 0x0 },
  859 + { 0x90203, 0x0 },
  860 + { 0x190203, 0x0 },
  861 + { 0x290203, 0x0 },
  862 + { 0x90204, 0x0 },
  863 + { 0x190204, 0x0 },
  864 + { 0x290204, 0x0 },
  865 + { 0x90205, 0x0 },
  866 + { 0x190205, 0x0 },
  867 + { 0x290205, 0x0 },
  868 + { 0x90206, 0x0 },
  869 + { 0x190206, 0x0 },
  870 + { 0x290206, 0x0 },
  871 + { 0x90207, 0x0 },
  872 + { 0x190207, 0x0 },
  873 + { 0x290207, 0x0 },
  874 + { 0x90208, 0x0 },
  875 + { 0x190208, 0x0 },
  876 + { 0x290208, 0x0 },
  877 + { 0x10062, 0x0 },
  878 + { 0x10162, 0x0 },
  879 + { 0x10262, 0x0 },
  880 + { 0x10362, 0x0 },
  881 + { 0x10462, 0x0 },
  882 + { 0x10562, 0x0 },
  883 + { 0x10662, 0x0 },
  884 + { 0x10762, 0x0 },
  885 + { 0x10862, 0x0 },
  886 + { 0x11062, 0x0 },
  887 + { 0x11162, 0x0 },
  888 + { 0x11262, 0x0 },
  889 + { 0x11362, 0x0 },
  890 + { 0x11462, 0x0 },
  891 + { 0x11562, 0x0 },
  892 + { 0x11662, 0x0 },
  893 + { 0x11762, 0x0 },
  894 + { 0x11862, 0x0 },
  895 + { 0x12062, 0x0 },
  896 + { 0x12162, 0x0 },
  897 + { 0x12262, 0x0 },
  898 + { 0x12362, 0x0 },
  899 + { 0x12462, 0x0 },
  900 + { 0x12562, 0x0 },
  901 + { 0x12662, 0x0 },
  902 + { 0x12762, 0x0 },
  903 + { 0x12862, 0x0 },
  904 + { 0x13062, 0x0 },
  905 + { 0x13162, 0x0 },
  906 + { 0x13262, 0x0 },
  907 + { 0x13362, 0x0 },
  908 + { 0x13462, 0x0 },
  909 + { 0x13562, 0x0 },
  910 + { 0x13662, 0x0 },
  911 + { 0x13762, 0x0 },
  912 + { 0x13862, 0x0 },
  913 + { 0x20077, 0x0 },
  914 + { 0x10001, 0x0 },
  915 + { 0x11001, 0x0 },
  916 + { 0x12001, 0x0 },
  917 + { 0x13001, 0x0 },
  918 + { 0x10040, 0x0 },
  919 + { 0x10140, 0x0 },
  920 + { 0x10240, 0x0 },
  921 + { 0x10340, 0x0 },
  922 + { 0x10440, 0x0 },
  923 + { 0x10540, 0x0 },
  924 + { 0x10640, 0x0 },
  925 + { 0x10740, 0x0 },
  926 + { 0x10840, 0x0 },
  927 + { 0x10030, 0x0 },
  928 + { 0x10130, 0x0 },
  929 + { 0x10230, 0x0 },
  930 + { 0x10330, 0x0 },
  931 + { 0x10430, 0x0 },
  932 + { 0x10530, 0x0 },
  933 + { 0x10630, 0x0 },
  934 + { 0x10730, 0x0 },
  935 + { 0x10830, 0x0 },
  936 + { 0x11040, 0x0 },
  937 + { 0x11140, 0x0 },
  938 + { 0x11240, 0x0 },
  939 + { 0x11340, 0x0 },
  940 + { 0x11440, 0x0 },
  941 + { 0x11540, 0x0 },
  942 + { 0x11640, 0x0 },
  943 + { 0x11740, 0x0 },
  944 + { 0x11840, 0x0 },
  945 + { 0x11030, 0x0 },
  946 + { 0x11130, 0x0 },
  947 + { 0x11230, 0x0 },
  948 + { 0x11330, 0x0 },
  949 + { 0x11430, 0x0 },
  950 + { 0x11530, 0x0 },
  951 + { 0x11630, 0x0 },
  952 + { 0x11730, 0x0 },
  953 + { 0x11830, 0x0 },
  954 + { 0x12040, 0x0 },
  955 + { 0x12140, 0x0 },
  956 + { 0x12240, 0x0 },
  957 + { 0x12340, 0x0 },
  958 + { 0x12440, 0x0 },
  959 + { 0x12540, 0x0 },
  960 + { 0x12640, 0x0 },
  961 + { 0x12740, 0x0 },
  962 + { 0x12840, 0x0 },
  963 + { 0x12030, 0x0 },
  964 + { 0x12130, 0x0 },
  965 + { 0x12230, 0x0 },
  966 + { 0x12330, 0x0 },
  967 + { 0x12430, 0x0 },
  968 + { 0x12530, 0x0 },
  969 + { 0x12630, 0x0 },
  970 + { 0x12730, 0x0 },
  971 + { 0x12830, 0x0 },
  972 + { 0x13040, 0x0 },
  973 + { 0x13140, 0x0 },
  974 + { 0x13240, 0x0 },
  975 + { 0x13340, 0x0 },
  976 + { 0x13440, 0x0 },
  977 + { 0x13540, 0x0 },
  978 + { 0x13640, 0x0 },
  979 + { 0x13740, 0x0 },
  980 + { 0x13840, 0x0 },
  981 + { 0x13030, 0x0 },
  982 + { 0x13130, 0x0 },
  983 + { 0x13230, 0x0 },
  984 + { 0x13330, 0x0 },
  985 + { 0x13430, 0x0 },
  986 + { 0x13530, 0x0 },
  987 + { 0x13630, 0x0 },
  988 + { 0x13730, 0x0 },
  989 + { 0x13830, 0x0 },
  990 +};
  991 +/* P0 message block paremeter for training firmware */
  992 +struct dram_cfg_param ddr_fsp0_cfg[] = {
  993 + {0xd0000, 0x0},
  994 + {0x54003,0xc80},
  995 + {0x54004,0x2},
  996 + {0x54005,0x2228},
  997 + {0x54006,0x11},
  998 + {0x54008,0x131f},
  999 + {0x54009,0xc8},
  1000 + {0x5400b,0x2},
  1001 + {0x5400d,0x100},
  1002 + {0x54012,0x310},
  1003 + {0x54019,0x2dd4},
  1004 + {0x5401a,0x31},
  1005 + {0x5401b,0x4a66},
  1006 + {0x5401c,0x4a08},
  1007 + {0x5401e,0x16},
  1008 + {0x5401f,0x2dd4},
  1009 + {0x54020,0x31},
  1010 + {0x54021,0x4a66},
  1011 + {0x54022,0x4a08},
  1012 + {0x54024,0x16},
  1013 + {0x5402b,0x1000},
  1014 + {0x5402c,0x3},
  1015 + {0x54032,0xd400},
  1016 + {0x54033,0x312d},
  1017 + {0x54034,0x6600},
  1018 + {0x54035,0x84a},
  1019 + {0x54036,0x4a},
  1020 + {0x54037,0x1600},
  1021 + {0x54038,0xd400},
  1022 + {0x54039,0x312d},
  1023 + {0x5403a,0x6600},
  1024 + {0x5403b,0x84a},
  1025 + {0x5403c,0x4a},
  1026 + {0x5403d,0x1600},
  1027 + {0xd0000, 0x1},
  1028 +};
  1029 +
  1030 +
  1031 +/* P1 message block paremeter for training firmware */
  1032 +struct dram_cfg_param ddr_fsp1_cfg[] = {
  1033 + {0xd0000, 0x0},
  1034 + {0x54002,0x1},
  1035 + {0x54003,0x29c},
  1036 + {0x54004,0x2},
  1037 + {0x54005,0x2228},
  1038 + {0x54006,0x11},
  1039 + {0x54008,0x121f},
  1040 + {0x54009,0xc8},
  1041 + {0x5400b,0x2},
  1042 + {0x5400d,0x100},
  1043 + {0x54012,0x310},
  1044 + {0x54019,0x994},
  1045 + {0x5401a,0x31},
  1046 + {0x5401b,0x4a66},
  1047 + {0x5401c,0x4a08},
  1048 + {0x5401e,0x16},
  1049 + {0x5401f,0x994},
  1050 + {0x54020,0x31},
  1051 + {0x54021,0x4a66},
  1052 + {0x54022,0x4a08},
  1053 + {0x54024,0x16},
  1054 + {0x5402b,0x1000},
  1055 + {0x5402c,0x3},
  1056 + {0x54032,0x9400},
  1057 + {0x54033,0x3109},
  1058 + {0x54034,0x6600},
  1059 + {0x54035,0x84a},
  1060 + {0x54036,0x4a},
  1061 + {0x54037,0x1600},
  1062 + {0x54038,0x9400},
  1063 + {0x54039,0x3109},
  1064 + {0x5403a,0x6600},
  1065 + {0x5403b,0x84a},
  1066 + {0x5403c,0x4a},
  1067 + {0x5403d,0x1600},
  1068 + {0xd0000, 0x1},
  1069 +};
  1070 +
  1071 +
  1072 +/* P0 2D message block paremeter for training firmware */
  1073 +struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
  1074 + {0xd0000, 0x0},
  1075 + {0x54003,0xc80},
  1076 + {0x54004,0x2},
  1077 + {0x54005,0x2228},
  1078 + {0x54006,0x11},
  1079 + {0x54008,0x61},
  1080 + {0x54009,0xc8},
  1081 + {0x5400b,0x2},
  1082 + {0x5400f,0x100},
  1083 + {0x54010,0x1f7f},
  1084 + {0x54012,0x310},
  1085 + {0x54019,0x2dd4},
  1086 + {0x5401a,0x31},
  1087 + {0x5401b,0x4a66},
  1088 + {0x5401c,0x4a08},
  1089 + {0x5401e,0x16},
  1090 + {0x5401f,0x2dd4},
  1091 + {0x54020,0x31},
  1092 + {0x54021,0x4a66},
  1093 + {0x54022,0x4a08},
  1094 + {0x54024,0x16},
  1095 + {0x5402b,0x1000},
  1096 + {0x5402c,0x3},
  1097 + {0x54032,0xd400},
  1098 + {0x54033,0x312d},
  1099 + {0x54034,0x6600},
  1100 + {0x54035,0x84a},
  1101 + {0x54036,0x4a},
  1102 + {0x54037,0x1600},
  1103 + {0x54038,0xd400},
  1104 + {0x54039,0x312d},
  1105 + {0x5403a,0x6600},
  1106 + {0x5403b,0x84a},
  1107 + {0x5403c,0x4a},
  1108 + {0x5403d,0x1600},
  1109 + { 0xd0000, 0x1 },
  1110 +};
  1111 +
  1112 +/* DRAM PHY init engine image */
  1113 +struct dram_cfg_param ddr_phy_pie[] = {
  1114 + {0xd0000, 0x0},
  1115 + {0x90000,0x10},
  1116 + {0x90001,0x400},
  1117 + {0x90002,0x10e},
  1118 + {0x90003,0x0},
  1119 + {0x90004,0x0},
  1120 + {0x90005,0x8},
  1121 + {0x90029,0xb},
  1122 + {0x9002a,0x480},
  1123 + {0x9002b,0x109},
  1124 + {0x9002c,0x8},
  1125 + {0x9002d,0x448},
  1126 + {0x9002e,0x139},
  1127 + {0x9002f,0x8},
  1128 + {0x90030,0x478},
  1129 + {0x90031,0x109},
  1130 + {0x90032,0x0},
  1131 + {0x90033,0xe8},
  1132 + {0x90034,0x109},
  1133 + {0x90035,0x2},
  1134 + {0x90036,0x10},
  1135 + {0x90037,0x139},
  1136 + {0x90038,0xf},
  1137 + {0x90039,0x7c0},
  1138 + {0x9003a,0x139},
  1139 + {0x9003b,0x44},
  1140 + {0x9003c,0x630},
  1141 + {0x9003d,0x159},
  1142 + {0x9003e,0x14f},
  1143 + {0x9003f,0x630},
  1144 + {0x90040,0x159},
  1145 + {0x90041,0x47},
  1146 + {0x90042,0x630},
  1147 + {0x90043,0x149},
  1148 + {0x90044,0x4f},
  1149 + {0x90045,0x630},
  1150 + {0x90046,0x179},
  1151 + {0x90047,0x8},
  1152 + {0x90048,0xe0},
  1153 + {0x90049,0x109},
  1154 + {0x9004a,0x0},
  1155 + {0x9004b,0x7c8},
  1156 + {0x9004c,0x109},
  1157 + {0x9004d,0x0},
  1158 + {0x9004e,0x1},
  1159 + {0x9004f,0x8},
  1160 + {0x90050,0x0},
  1161 + {0x90051,0x45a},
  1162 + {0x90052,0x9},
  1163 + {0x90053,0x0},
  1164 + {0x90054,0x448},
  1165 + {0x90055,0x109},
  1166 + {0x90056,0x40},
  1167 + {0x90057,0x630},
  1168 + {0x90058,0x179},
  1169 + {0x90059,0x1},
  1170 + {0x9005a,0x618},
  1171 + {0x9005b,0x109},
  1172 + {0x9005c,0x40c0},
  1173 + {0x9005d,0x630},
  1174 + {0x9005e,0x149},
  1175 + {0x9005f,0x8},
  1176 + {0x90060,0x4},
  1177 + {0x90061,0x48},
  1178 + {0x90062,0x4040},
  1179 + {0x90063,0x630},
  1180 + {0x90064,0x149},
  1181 + {0x90065,0x0},
  1182 + {0x90066,0x4},
  1183 + {0x90067,0x48},
  1184 + {0x90068,0x40},
  1185 + {0x90069,0x630},
  1186 + {0x9006a,0x149},
  1187 + {0x9006b,0x10},
  1188 + {0x9006c,0x4},
  1189 + {0x9006d,0x18},
  1190 + {0x9006e,0x0},
  1191 + {0x9006f,0x4},
  1192 + {0x90070,0x78},
  1193 + {0x90071,0x549},
  1194 + {0x90072,0x630},
  1195 + {0x90073,0x159},
  1196 + {0x90074,0xd49},
  1197 + {0x90075,0x630},
  1198 + {0x90076,0x159},
  1199 + {0x90077,0x94a},
  1200 + {0x90078,0x630},
  1201 + {0x90079,0x159},
  1202 + {0x9007a,0x441},
  1203 + {0x9007b,0x630},
  1204 + {0x9007c,0x149},
  1205 + {0x9007d,0x42},
  1206 + {0x9007e,0x630},
  1207 + {0x9007f,0x149},
  1208 + {0x90080,0x1},
  1209 + {0x90081,0x630},
  1210 + {0x90082,0x149},
  1211 + {0x90083,0x0},
  1212 + {0x90084,0xe0},
  1213 + {0x90085,0x109},
  1214 + {0x90086,0xa},
  1215 + {0x90087,0x10},
  1216 + {0x90088,0x109},
  1217 + {0x90089,0x9},
  1218 + {0x9008a,0x3c0},
  1219 + {0x9008b,0x149},
  1220 + {0x9008c,0x9},
  1221 + {0x9008d,0x3c0},
  1222 + {0x9008e,0x159},
  1223 + {0x9008f,0x18},
  1224 + {0x90090,0x10},
  1225 + {0x90091,0x109},
  1226 + {0x90092,0x0},
  1227 + {0x90093,0x3c0},
  1228 + {0x90094,0x109},
  1229 + {0x90095,0x18},
  1230 + {0x90096,0x4},
  1231 + {0x90097,0x48},
  1232 + {0x90098,0x18},
  1233 + {0x90099,0x4},
  1234 + {0x9009a,0x58},
  1235 + {0x9009b,0xa},
  1236 + {0x9009c,0x10},
  1237 + {0x9009d,0x109},
  1238 + {0x9009e,0x2},
  1239 + {0x9009f,0x10},
  1240 + {0x900a0,0x109},
  1241 + {0x900a1,0x5},
  1242 + {0x900a2,0x7c0},
  1243 + {0x900a3,0x109},
  1244 + {0x900a4,0x10},
  1245 + {0x900a5,0x10},
  1246 + {0x900a6,0x109},
  1247 + {0x40000,0x811},
  1248 + {0x40020,0x880},
  1249 + {0x40040,0x0},
  1250 + {0x40060,0x0},
  1251 + {0x40001,0x4008},
  1252 + {0x40021,0x83},
  1253 + {0x40041,0x4f},
  1254 + {0x40061,0x0},
  1255 + {0x40002,0x4040},
  1256 + {0x40022,0x83},
  1257 + {0x40042,0x51},
  1258 + {0x40062,0x0},
  1259 + {0x40003,0x811},
  1260 + {0x40023,0x880},
  1261 + {0x40043,0x0},
  1262 + {0x40063,0x0},
  1263 + {0x40004,0x720},
  1264 + {0x40024,0xf},
  1265 + {0x40044,0x1740},
  1266 + {0x40064,0x0},
  1267 + {0x40005,0x16},
  1268 + {0x40025,0x83},
  1269 + {0x40045,0x4b},
  1270 + {0x40065,0x0},
  1271 + {0x40006,0x716},
  1272 + {0x40026,0xf},
  1273 + {0x40046,0x2001},
  1274 + {0x40066,0x0},
  1275 + {0x40007,0x716},
  1276 + {0x40027,0xf},
  1277 + {0x40047,0x2800},
  1278 + {0x40067,0x0},
  1279 + {0x40008,0x716},
  1280 + {0x40028,0xf},
  1281 + {0x40048,0xf00},
  1282 + {0x40068,0x0},
  1283 + {0x40009,0x720},
  1284 + {0x40029,0xf},
  1285 + {0x40049,0x1400},
  1286 + {0x40069,0x0},
  1287 + {0x4000a,0xe08},
  1288 + {0x4002a,0xc15},
  1289 + {0x4004a,0x0},
  1290 + {0x4006a,0x0},
  1291 + {0x4000b,0x623},
  1292 + {0x4002b,0x15},
  1293 + {0x4004b,0x0},
  1294 + {0x4006b,0x0},
  1295 + {0x4000c,0x4028},
  1296 + {0x4002c,0x80},
  1297 + {0x4004c,0x0},
  1298 + {0x4006c,0x0},
  1299 + {0x4000d,0xe08},
  1300 + {0x4002d,0xc1a},
  1301 + {0x4004d,0x0},
  1302 + {0x4006d,0x0},
  1303 + {0x4000e,0x623},
  1304 + {0x4002e,0x1a},
  1305 + {0x4004e,0x0},
  1306 + {0x4006e,0x0},
  1307 + {0x4000f,0x4040},
  1308 + {0x4002f,0x80},
  1309 + {0x4004f,0x0},
  1310 + {0x4006f,0x0},
  1311 + {0x40010,0x2604},
  1312 + {0x40030,0x15},
  1313 + {0x40050,0x0},
  1314 + {0x40070,0x0},
  1315 + {0x40011,0x708},
  1316 + {0x40031,0x5},
  1317 + {0x40051,0x0},
  1318 + {0x40071,0x2002},
  1319 + {0x40012,0x8},
  1320 + {0x40032,0x80},
  1321 + {0x40052,0x0},
  1322 + {0x40072,0x0},
  1323 + {0x40013,0x2604},
  1324 + {0x40033,0x1a},
  1325 + {0x40053,0x0},
  1326 + {0x40073,0x0},
  1327 + {0x40014,0x708},
  1328 + {0x40034,0xa},
  1329 + {0x40054,0x0},
  1330 + {0x40074,0x2002},
  1331 + {0x40015,0x4040},
  1332 + {0x40035,0x80},
  1333 + {0x40055,0x0},
  1334 + {0x40075,0x0},
  1335 + {0x40016,0x60a},
  1336 + {0x40036,0x15},
  1337 + {0x40056,0x1200},
  1338 + {0x40076,0x0},
  1339 + {0x40017,0x61a},
  1340 + {0x40037,0x15},
  1341 + {0x40057,0x1300},
  1342 + {0x40077,0x0},
  1343 + {0x40018,0x60a},
  1344 + {0x40038,0x1a},
  1345 + {0x40058,0x1200},
  1346 + {0x40078,0x0},
  1347 + {0x40019,0x642},
  1348 + {0x40039,0x1a},
  1349 + {0x40059,0x1300},
  1350 + {0x40079,0x0},
  1351 + {0x4001a,0x4808},
  1352 + {0x4003a,0x880},
  1353 + {0x4005a,0x0},
  1354 + {0x4007a,0x0},
  1355 + {0x900a7,0x0},
  1356 + {0x900a8,0x790},
  1357 + {0x900a9,0x11a},
  1358 + {0x900aa,0x8},
  1359 + {0x900ab,0x7aa},
  1360 + {0x900ac,0x2a},
  1361 + {0x900ad,0x10},
  1362 + {0x900ae,0x7b2},
  1363 + {0x900af,0x2a},
  1364 + {0x900b0,0x0},
  1365 + {0x900b1,0x7c8},
  1366 + {0x900b2,0x109},
  1367 + {0x900b3,0x10},
  1368 + {0x900b4,0x2a8},
  1369 + {0x900b5,0x129},
  1370 + {0x900b6,0x8},
  1371 + {0x900b7,0x370},
  1372 + {0x900b8,0x129},
  1373 + {0x900b9,0xa},
  1374 + {0x900ba,0x3c8},
  1375 + {0x900bb,0x1a9},
  1376 + {0x900bc,0xc},
  1377 + {0x900bd,0x408},
  1378 + {0x900be,0x199},
  1379 + {0x900bf,0x14},
  1380 + {0x900c0,0x790},
  1381 + {0x900c1,0x11a},
  1382 + {0x900c2,0x8},
  1383 + {0x900c3,0x4},
  1384 + {0x900c4,0x18},
  1385 + {0x900c5,0xe},
  1386 + {0x900c6,0x408},
  1387 + {0x900c7,0x199},
  1388 + {0x900c8,0x8},
  1389 + {0x900c9,0x8568},
  1390 + {0x900ca,0x108},
  1391 + {0x900cb,0x18},
  1392 + {0x900cc,0x790},
  1393 + {0x900cd,0x16a},
  1394 + {0x900ce,0x8},
  1395 + {0x900cf,0x1d8},
  1396 + {0x900d0,0x169},
  1397 + {0x900d1,0x10},
  1398 + {0x900d2,0x8558},
  1399 + {0x900d3,0x168},
  1400 + {0x900d4,0x70},
  1401 + {0x900d5,0x788},
  1402 + {0x900d6,0x16a},
  1403 + {0x900d7,0x1ff8},
  1404 + {0x900d8,0x85a8},
  1405 + {0x900d9,0x1e8},
  1406 + {0x900da,0x50},
  1407 + {0x900db,0x798},
  1408 + {0x900dc,0x16a},
  1409 + {0x900dd,0x60},
  1410 + {0x900de,0x7a0},
  1411 + {0x900df,0x16a},
  1412 + {0x900e0,0x8},
  1413 + {0x900e1,0x8310},
  1414 + {0x900e2,0x168},
  1415 + {0x900e3,0x8},
  1416 + {0x900e4,0xa310},
  1417 + {0x900e5,0x168},
  1418 + {0x900e6,0xa},
  1419 + {0x900e7,0x408},
  1420 + {0x900e8,0x169},
  1421 + {0x900e9,0x6e},
  1422 + {0x900ea,0x0},
  1423 + {0x900eb,0x68},
  1424 + {0x900ec,0x0},
  1425 + {0x900ed,0x408},
  1426 + {0x900ee,0x169},
  1427 + {0x900ef,0x0},
  1428 + {0x900f0,0x8310},
  1429 + {0x900f1,0x168},
  1430 + {0x900f2,0x0},
  1431 + {0x900f3,0xa310},
  1432 + {0x900f4,0x168},
  1433 + {0x900f5,0x1ff8},
  1434 + {0x900f6,0x85a8},
  1435 + {0x900f7,0x1e8},
  1436 + {0x900f8,0x68},
  1437 + {0x900f9,0x798},
  1438 + {0x900fa,0x16a},
  1439 + {0x900fb,0x78},
  1440 + {0x900fc,0x7a0},
  1441 + {0x900fd,0x16a},
  1442 + {0x900fe,0x68},
  1443 + {0x900ff,0x790},
  1444 + {0x90100,0x16a},
  1445 + {0x90101,0x8},
  1446 + {0x90102,0x8b10},
  1447 + {0x90103,0x168},
  1448 + {0x90104,0x8},
  1449 + {0x90105,0xab10},
  1450 + {0x90106,0x168},
  1451 + {0x90107,0xa},
  1452 + {0x90108,0x408},
  1453 + {0x90109,0x169},
  1454 + {0x9010a,0x58},
  1455 + {0x9010b,0x0},
  1456 + {0x9010c,0x68},
  1457 + {0x9010d,0x0},
  1458 + {0x9010e,0x408},
  1459 + {0x9010f,0x169},
  1460 + {0x90110,0x0},
  1461 + {0x90111,0x8b10},
  1462 + {0x90112,0x168},
  1463 + {0x90113,0x0},
  1464 + {0x90114,0xab10},
  1465 + {0x90115,0x168},
  1466 + {0x90116,0x0},
  1467 + {0x90117,0x1d8},
  1468 + {0x90118,0x169},
  1469 + {0x90119,0x80},
  1470 + {0x9011a,0x790},
  1471 + {0x9011b,0x16a},
  1472 + {0x9011c,0x18},
  1473 + {0x9011d,0x7aa},
  1474 + {0x9011e,0x6a},
  1475 + {0x9011f,0xa},
  1476 + {0x90120,0x0},
  1477 + {0x90121,0x1e9},
  1478 + {0x90122,0x8},
  1479 + {0x90123,0x8080},
  1480 + {0x90124,0x108},
  1481 + {0x90125,0xf},
  1482 + {0x90126,0x408},
  1483 + {0x90127,0x169},
  1484 + {0x90128,0xc},
  1485 + {0x90129,0x0},
  1486 + {0x9012a,0x68},
  1487 + {0x9012b,0x9},
  1488 + {0x9012c,0x0},
  1489 + {0x9012d,0x1a9},
  1490 + {0x9012e,0x0},
  1491 + {0x9012f,0x408},
  1492 + {0x90130,0x169},
  1493 + {0x90131,0x0},
  1494 + {0x90132,0x8080},
  1495 + {0x90133,0x108},
  1496 + {0x90134,0x8},
  1497 + {0x90135,0x7aa},
  1498 + {0x90136,0x6a},
  1499 + {0x90137,0x0},
  1500 + {0x90138,0x8568},
  1501 + {0x90139,0x108},
  1502 + {0x9013a,0xb7},
  1503 + {0x9013b,0x790},
  1504 + {0x9013c,0x16a},
  1505 + {0x9013d,0x1f},
  1506 + {0x9013e,0x0},
  1507 + {0x9013f,0x68},
  1508 + {0x90140,0x8},
  1509 + {0x90141,0x8558},
  1510 + {0x90142,0x168},
  1511 + {0x90143,0xf},
  1512 + {0x90144,0x408},
  1513 + {0x90145,0x169},
  1514 + {0x90146,0xc},
  1515 + {0x90147,0x0},
  1516 + {0x90148,0x68},
  1517 + {0x90149,0x0},
  1518 + {0x9014a,0x408},
  1519 + {0x9014b,0x169},
  1520 + {0x9014c,0x0},
  1521 + {0x9014d,0x8558},
  1522 + {0x9014e,0x168},
  1523 + {0x9014f,0x8},
  1524 + {0x90150,0x3c8},
  1525 + {0x90151,0x1a9},
  1526 + {0x90152,0x3},
  1527 + {0x90153,0x370},
  1528 + {0x90154,0x129},
  1529 + {0x90155,0x20},
  1530 + {0x90156,0x2aa},
  1531 + {0x90157,0x9},
  1532 + {0x90158,0x0},
  1533 + {0x90159,0x400},
  1534 + {0x9015a,0x10e},
  1535 + {0x9015b,0x8},
  1536 + {0x9015c,0xe8},
  1537 + {0x9015d,0x109},
  1538 + {0x9015e,0x0},
  1539 + {0x9015f,0x8140},
  1540 + {0x90160,0x10c},
  1541 + {0x90161,0x10},
  1542 + {0x90162,0x8138},
  1543 + {0x90163,0x10c},
  1544 + {0x90164,0x8},
  1545 + {0x90165,0x7c8},
  1546 + {0x90166,0x101},
  1547 + {0x90167,0x8},
  1548 + {0x90168,0x0},
  1549 + {0x90169,0x8},
  1550 + {0x9016a,0x8},
  1551 + {0x9016b,0x448},
  1552 + {0x9016c,0x109},
  1553 + {0x9016d,0xf},
  1554 + {0x9016e,0x7c0},
  1555 + {0x9016f,0x109},
  1556 + {0x90170,0x0},
  1557 + {0x90171,0xe8},
  1558 + {0x90172,0x109},
  1559 + {0x90173,0x47},
  1560 + {0x90174,0x630},
  1561 + {0x90175,0x109},
  1562 + {0x90176,0x8},
  1563 + {0x90177,0x618},
  1564 + {0x90178,0x109},
  1565 + {0x90179,0x8},
  1566 + {0x9017a,0xe0},
  1567 + {0x9017b,0x109},
  1568 + {0x9017c,0x0},
  1569 + {0x9017d,0x7c8},
  1570 + {0x9017e,0x109},
  1571 + {0x9017f,0x8},
  1572 + {0x90180,0x8140},
  1573 + {0x90181,0x10c},
  1574 + {0x90182,0x0},
  1575 + {0x90183,0x1},
  1576 + {0x90184,0x8},
  1577 + {0x90185,0x8},
  1578 + {0x90186,0x4},
  1579 + {0x90187,0x8},
  1580 + {0x90188,0x8},
  1581 + {0x90189,0x7c8},
  1582 + {0x9018a,0x101},
  1583 + {0x90006,0x0},
  1584 + {0x90007,0x0},
  1585 + {0x90008,0x8},
  1586 + {0x90009,0x0},
  1587 + {0x9000a,0x0},
  1588 + {0x9000b,0x0},
  1589 + {0xd00e7,0x400},
  1590 + {0x90017,0x0},
  1591 + {0x9001f,0x2a},
  1592 + {0x90026,0x6a},
  1593 + {0x400d0,0x0},
  1594 + {0x400d1,0x101},
  1595 + {0x400d2,0x105},
  1596 + {0x400d3,0x107},
  1597 + {0x400d4,0x10f},
  1598 + {0x400d5,0x202},
  1599 + {0x400d6,0x20a},
  1600 + {0x400d7,0x20b},
  1601 + {0x2003a,0x2},
  1602 + {0x2000b,0x64},
  1603 + {0x2000c,0xc8},
  1604 + {0x2000d,0x7d0},
  1605 + {0x2000e,0x2c},
  1606 + {0x12000b,0x14},
  1607 + {0x12000c,0x29},
  1608 + {0x12000d,0x1a1},
  1609 + {0x12000e,0x10},
  1610 + {0x9000c,0x0},
  1611 + {0x9000d,0x173},
  1612 + {0x9000e,0x60},
  1613 + {0x9000f,0x6110},
  1614 + {0x90010,0x2152},
  1615 + {0x90011,0xdfbd},
  1616 + {0x90012,0x60},
  1617 + {0x90013,0x6152},
  1618 + {0x20010,0x5a},
  1619 + {0x20011,0x3},
  1620 + {0x120010,0x5a},
  1621 + {0x120011,0x3},
  1622 + {0x40080,0xe0},
  1623 + {0x40081,0x12},
  1624 + {0x40082,0xe0},
  1625 + {0x40083,0x12},
  1626 + {0x40084,0xe0},
  1627 + {0x40085,0x12},
  1628 + {0x140080,0xe0},
  1629 + {0x140081,0x12},
  1630 + {0x140082,0xe0},
  1631 + {0x140083,0x12},
  1632 + {0x140084,0xe0},
  1633 + {0x140085,0x12},
  1634 + {0x400fd,0xf},
  1635 + {0x10011,0x1},
  1636 + {0x10012,0x1},
  1637 + {0x10013,0x180},
  1638 + {0x10018,0x1},
  1639 + {0x10002,0x6209},
  1640 + {0x100b2,0x1},
  1641 + {0x101b4,0x1},
  1642 + {0x102b4,0x1},
  1643 + {0x103b4,0x1},
  1644 + {0x104b4,0x1},
  1645 + {0x105b4,0x1},
  1646 + {0x106b4,0x1},
  1647 + {0x107b4,0x1},
  1648 + {0x108b4,0x1},
  1649 + {0x11011,0x1},
  1650 + {0x11012,0x1},
  1651 + {0x11013,0x180},
  1652 + {0x11018,0x1},
  1653 + {0x11002,0x6209},
  1654 + {0x110b2,0x1},
  1655 + {0x111b4,0x1},
  1656 + {0x112b4,0x1},
  1657 + {0x113b4,0x1},
  1658 + {0x114b4,0x1},
  1659 + {0x115b4,0x1},
  1660 + {0x116b4,0x1},
  1661 + {0x117b4,0x1},
  1662 + {0x118b4,0x1},
  1663 + {0x12011,0x1},
  1664 + {0x12012,0x1},
  1665 + {0x12013,0x180},
  1666 + {0x12018,0x1},
  1667 + {0x12002,0x6209},
  1668 + {0x120b2,0x1},
  1669 + {0x121b4,0x1},
  1670 + {0x122b4,0x1},
  1671 + {0x123b4,0x1},
  1672 + {0x124b4,0x1},
  1673 + {0x125b4,0x1},
  1674 + {0x126b4,0x1},
  1675 + {0x127b4,0x1},
  1676 + {0x128b4,0x1},
  1677 + {0x13011,0x1},
  1678 + {0x13012,0x1},
  1679 + {0x13013,0x180},
  1680 + {0x13018,0x1},
  1681 + {0x13002,0x6209},
  1682 + {0x130b2,0x1},
  1683 + {0x131b4,0x1},
  1684 + {0x132b4,0x1},
  1685 + {0x133b4,0x1},
  1686 + {0x134b4,0x1},
  1687 + {0x135b4,0x1},
  1688 + {0x136b4,0x1},
  1689 + {0x137b4,0x1},
  1690 + {0x138b4,0x1},
  1691 + {0x2003a,0x2},
  1692 + {0xc0080,0x2},
  1693 + {0xd0000, 0x1}
  1694 +};
  1695 +
  1696 +struct dram_fsp_msg ddr_dram_fsp_msg[] = {
  1697 + {
  1698 + /* P0 3200mts 1D */
  1699 + .drate = 3200,
  1700 + .fw_type = FW_1D_IMAGE,
  1701 + .fsp_cfg = ddr_fsp0_cfg,
  1702 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
  1703 + },
  1704 + {
  1705 + /* P1 667mts 1D */
  1706 + .drate = 667,
  1707 + .fw_type = FW_1D_IMAGE,
  1708 + .fsp_cfg = ddr_fsp1_cfg,
  1709 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
  1710 + },
  1711 + {
  1712 + /* P0 3200mts 2D */
  1713 + .drate = 3200,
  1714 + .fw_type = FW_2D_IMAGE,
  1715 + .fsp_cfg = ddr_fsp0_2d_cfg,
  1716 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
  1717 + },
  1718 +};
  1719 +
  1720 +/* ddr timing config params */
  1721 +struct dram_timing_info dram_timing_3g = {
  1722 + .ddrc_cfg = ddr_ddrc_cfg,
  1723 + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
  1724 + .ddrphy_cfg = ddr_ddrphy_cfg,
  1725 + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
  1726 + .fsp_msg = ddr_dram_fsp_msg,
  1727 + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
  1728 + .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
  1729 + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
  1730 + .ddrphy_pie = ddr_phy_pie,
  1731 + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
  1732 + .fsp_table = { 3200, 667, },
  1733 +};
board/freescale/imx8mq_aiy/spl.c
Diff comments   View file @ 63dbfc0
... ... @@ -20,14 +20,16 @@
20 20 #include <asm/mach-imx/mxc_i2c.h>
21 21 #include <fsl_esdhc.h>
22 22 #include <mmc.h>
23   -#include "ddr/ddr.h"
  23 +#include <asm/arch/imx8m_ddr.h>
24 24  
25 25 DECLARE_GLOBAL_DATA_PTR;
26 26  
  27 +extern struct dram_timing_info dram_timing_3g;
  28 +
27 29 void spl_dram_init(void)
28 30 {
29 31 /* ddr init */
30   - ddr_init();
  32 + ddr_init(&dram_timing_3g);
31 33 }
32 34  
33 35 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
configs/imx8mq_aiy_android_defconfig
Diff comments   View file @ 63dbfc0
... ... @@ -74,6 +74,7 @@
74 74 CONFIG_SPL_USB_HOST_SUPPORT=y
75 75 CONFIG_SPL_USB_GADGET_SUPPORT=y
76 76 CONFIG_SPL_USB_SDP_SUPPORT=y
  77 +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
77 78  
78 79 CONFIG_NOT_UUU_BUILD=y
79 80 CONFIG_APPEND_BOOTARGS=y
configs/imx8mq_aiy_android_uuu_defconfig
Diff comments   View file @ 63dbfc0
... ... @@ -74,4 +74,5 @@
74 74 CONFIG_SPL_USB_HOST_SUPPORT=y
75 75 CONFIG_SPL_USB_GADGET_SUPPORT=y
76 76 CONFIG_SPL_USB_SDP_SUPPORT=y
  77 +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000