Some code cleanup.

Wolfgang Denk · Wolfgang Denk
1 parent b24444f1b3
Showing 8 changed files with 80 additions and 96 deletions Side-by-side Diff
board/mpc7448hpc2/mpc7448hpc2.c
board/mpc7448hpc2/tsi108_init.c
cpu/74xx_7xx/cpu.c
cpu/ppc4xx/44x_spd_ddr2.c
cpu/ppc4xx/start.S
doc/README.mpc7448hpc2
drivers/tsi108_i2c.c
include/configs/mpc7448hpc2.h
@@ -47,7 +47,7 @@
 void after_reloc (ulong dest_addr)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	
+
 	/*
 	 * Jump to the main U-Boot board init code
 	 */
@@ -179,7 +179,7 @@
 	ulong temp, i;
 	ulong reg_val;
 	volatile ulong *reg_ptr;
-	
+
 	reg_ptr =
 		(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
  
@@ -300,7 +300,7 @@
 	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
 		0x7C0F2000);
 	__asm__ __volatile__ ("sync");
-	
+
 	/*
 	 * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
 	 * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
@@ -312,7 +312,7 @@
 	/* Make sure that OCN_BAR2 decoder is set (to allow following
 	 * immediate read from SDRAM)
 	 */
-	
+
 	temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
 	__asm__ __volatile__ ("sync");
  
  
@@ -327,11 +327,11 @@
 	 * and enable all HLP banks and not just HLP 0 as is being done for
 	 * Taiga Rev. 2.
 	 */
-	
+
 	env_init ();
  
 #ifndef DISABLE_PBM
-	
+
 	/*
 	 * For IBM processors we have to set Address-Only commands generated
 	 * by PBM that are different from ones set after reset.
  
@@ -475,10 +475,10 @@
  
 	for (i = 0; i < 32; i++) {
 		*reg_ptr++ = reg_val;	/* P2O_BAR3_LUTx */
-		
+
 /* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
-		*reg_ptr++ = 0;	
-		
+		*reg_ptr++ = 0;
+
 /* offset = 16MB, address translation is enabled to allow byte swapping */
 		reg_val += 0x01000000;
 	}
@@ -507,7 +507,7 @@
  
 #endif	/* !DISABLE_PBM */
  
-#ifdef ENABLE_PCI_CSR_BAR	
+#ifdef ENABLE_PCI_CSR_BAR
 	/* open if required access to Tsi108 CSRs from the PCI/X bus */
 	/* enable BAR0 on the PCI/X bus */
 	reg_val = in32(CFG_TSI108_CSR_BASE +
@@ -528,7 +528,7 @@
 	/*
 	 * Finally enable PCI/X Bus Master and Memory Space access
 	 */
-	
+
 	reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
 	reg_val |= 0x06;
 	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
@@ -555,7 +555,7 @@
 	 * Ensure that Machine Check exception is enabled
 	 * We need it to support PCI Bus probing (configuration reads)
 	 */
-	
+
 	reg_val = mfmsr ();
 	mtmsr(reg_val | MSR_ME);
  
@@ -631,7 +631,7 @@
 	 * thing done with regards to enabling diabling the cache.
 	 * So this seems like a good place to print all this information
 	 */
-	
+
 	printf ("CACHE: ");
 	switch (get_cpu_type()) {
 	case CPU_7447A:
@@ -308,9 +308,9 @@
 	u32 *p;
 	ulong clock;
 	int len;
-		
+
 	clock = bd->bi_busfreq;
-	
+
 	p = ft_get_prop (blob, "/cpus/" OF_CPU "/bus-frequency", &len);
 	if (p != NULL)
 		*p = cpu_to_be32 (clock);
@@ -168,8 +168,8 @@
 static void program_mode(unsigned long *dimm_populated,
 			 unsigned char *iic0_dimm_addr,
 			 unsigned long num_dimm_banks,
-                         ddr_cas_id_t *selected_cas,
-                         int *write_recovery);
+			 ddr_cas_id_t *selected_cas,
+			 int *write_recovery);
 static void program_tr(unsigned long *dimm_populated,
 		       unsigned char *iic0_dimm_addr,
 		       unsigned long num_dimm_banks);
@@ -185,7 +185,7 @@
 static void program_initplr(unsigned long *dimm_populated,
 			    unsigned char *iic0_dimm_addr,
 			    unsigned long num_dimm_banks,
-                            ddr_cas_id_t selected_cas,
+			    ddr_cas_id_t selected_cas,
 			    int write_recovery);
 static unsigned long is_ecc_enabled(void);
 static void program_ecc(unsigned long *dimm_populated,
@@ -1110,7 +1110,7 @@
 				modt3 = 0x00000000;
 			}
 		}
-  	} else {
+	} else {
 		codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
 		modt0 = 0x00000000;
 		modt1 = 0x00000000;
@@ -1149,7 +1149,7 @@
 static void program_initplr(unsigned long *dimm_populated,
 			    unsigned char *iic0_dimm_addr,
 			    unsigned long num_dimm_banks,
-                            ddr_cas_id_t selected_cas,
+			    ddr_cas_id_t selected_cas,
 			    int write_recovery)
 {
 	u32 cas = 0;
@@ -1858,11 +1858,11 @@
 #endif /* CONFIG_405EP */
  
 #if defined(CONFIG_440)
-#define function_prolog(func_name)      .text; \
+#define function_prolog(func_name)	.text; \
 					.align 2; \
 					.globl func_name; \
 					func_name:
-#define function_epilog(func_name)      .type func_name,@function; \
+#define function_epilog(func_name)	.type func_name,@function; \
 					.size func_name,.-func_name
  
 /*----------------------------------------------------------------------------+
  
  
@@ -1916,44 +1916,44 @@
 /*----------------------------------------------------------------------------+
 | dcbz_area.
 +----------------------------------------------------------------------------*/
-        function_prolog(dcbz_area)
-        rlwinm. r5,r4,0,27,31
-        rlwinm  r5,r4,27,5,31
-        beq     ..d_ra2
-        addi    r5,r5,0x0001
-..d_ra2:mtctr   r5
-..d_ag2:dcbz    r0,r3
-        addi    r3,r3,32
-        bdnz    ..d_ag2
-        sync
-        blr
-        function_epilog(dcbz_area)
+	function_prolog(dcbz_area)
+	rlwinm. r5,r4,0,27,31
+	rlwinm	r5,r4,27,5,31
+	beq	..d_ra2
+	addi	r5,r5,0x0001
+..d_ra2:mtctr	r5
+..d_ag2:dcbz	r0,r3
+	addi	r3,r3,32
+	bdnz	..d_ag2
+	sync
+	blr
+	function_epilog(dcbz_area)
  
 /*----------------------------------------------------------------------------+
 | dflush.  Assume 32K at vector address is cachable.
 +----------------------------------------------------------------------------*/
-        function_prolog(dflush)
-        mfmsr   r9
-        rlwinm  r8,r9,0,15,13
-        rlwinm  r8,r8,0,17,15
-        mtmsr   r8
-        addi    r3,r0,0x0000
-        mtspr   dvlim,r3
-        mfspr   r3,ivpr
-        addi    r4,r0,1024
-        mtctr   r4
+	function_prolog(dflush)
+	mfmsr	r9
+	rlwinm	r8,r9,0,15,13
+	rlwinm	r8,r8,0,17,15
+	mtmsr	r8
+	addi	r3,r0,0x0000
+	mtspr	dvlim,r3
+	mfspr	r3,ivpr
+	addi	r4,r0,1024
+	mtctr	r4
 ..dflush_loop:
-        lwz     r6,0x0(r3)
-        addi    r3,r3,32
-        bdnz    ..dflush_loop
-        addi    r3,r3,-32
-        mtctr   r4
-..ag:   dcbf    r0,r3
-        addi    r3,r3,-32
-        bdnz    ..ag
-        sync
-        mtmsr   r9
-        blr
-        function_epilog(dflush)
+	lwz	r6,0x0(r3)
+	addi	r3,r3,32
+	bdnz	..dflush_loop
+	addi	r3,r3,-32
+	mtctr	r4
+..ag:	dcbf	r0,r3
+	addi	r3,r3,-32
+	bdnz	..ag
+	sync
+	mtmsr	r9
+	blr
+	function_epilog(dflush)
 #endif /* CONFIG_440 */
@@ -92,7 +92,7 @@
 		CPU Core Frequency (MHz)
 			Bus Frequency
 	123456		100	133	167	200	Ratio
-	
+
 	------
 	SW2=101100	500	667	833	1000	5x
 	SW2=100100	550	733	917	1100	5.5x
  
  
  
  
  
  
  
@@ -109,43 +109,43 @@
  
 SW2[7-8]: Bus Protocol and CPU Reset Option
  
-	7		
+	7
 	-
 	SW2=0		System bus uses MPX bus protocol
 	SW2=1		System bus uses 60x bus protocol
  
-	8		
+	8
 	-
 	SW2=0		TSI108 can cause CPU reset
 	SW2=1		TSI108 can not cause CPU reset
  
 SW3[1-8] system options
  
-	123		
+	123
 	---
 	SW3=xxx		Connected to GPIO[0:2] on TSI108
  
-	4		
+	4
 	-
 	SW3=0		CPU boots from low half of flash
 	SW3=1		CPU boots from high half of flash
  
-	5		
+	5
 	-
 	SW3=0		SATA and slot2 connected to PCI bus
 	SW3=1		Only slot1 connected to PCI bus
  
-	6		
+	6
 	-
 	SW3=0		USB connected to PCI bus
 	SW3=1		USB disconnected from PCI bus
  
-	7		
+	7
 	-
 	SW3=0		Flash is write protected
 	SW3=1		Flash is NOT write protected
  
-	8		
+	8
 	-
 	SW3=0		CPU will boot from flash
 	SW3=1		CPU will boot from PromJet
  
  
@@ -166,19 +166,19 @@
 			Bus Frequency (MHz)
 	---
 	SW4=000		external clock
-	SW4=011		system clock	
+	SW4=011		system clock
 	SW4=100		133
 	SW4=101		166
 	SW4=110		200
 	others		reserved
  
 SW4[7-8]: PCI/PCI-X frequency control
-	7		
+	7
 	-
 	SW4=0		PCI/PCI-X bus operates normally
 	SW4=1		PCI bus forced to PCI-33 mode
  
-	8		
+	8
 	-
 	SW4=0		PCI-X mode at 133 MHz allowed
 	SW4=1		PCI-X mode limited to 100 MHz
@@ -82,15 +82,10 @@
 		/* Wait until operation completed */
 		do {
 			/* Read I2C operation status */
-			temp =
-			    *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset +
-				      I2C_CNTRL2);
+			temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
  
-			if (0 ==
-			    (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START)))
-			{
-				if (0 ==
-				    (temp &
+			if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) {
+				if (0 == (temp &
 				     (I2C_CNTRL2_I2C_CFGERR |
 				      I2C_CNTRL2_I2C_TO_ERR))
 				    ) {
@@ -152,9 +147,7 @@
 	/* Check for valid I2C address */
 	if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
 		while (len--) {
-			op_status =
-			    i2c_read_byte(i2c_if, chip_addr, byte_addr++,
-					  buffer++);
+			op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++);
  
 			if (TSI108_I2C_SUCCESS != op_status) {
 				DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
@@ -182,10 +175,7 @@
 	/* Check if I2C operation is in progress */
 	temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
  
-	if (0 ==
-	    (temp &
-	     (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START)))
-	{
+	if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
 		/* Place data into the I2C Tx Register */
 		*(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
 			  I2C_TX_DATA) = (u32) * buffer;
@@ -200,7 +190,7 @@
 		/* Issue the write command (at this moment all other parameters
 		 * are 0 (size = 1 byte, lane = 0)
 		 */
-		
+
 		*(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
 			  I2C_CNTRL2) = (I2C_CNTRL2_START);
  
  
@@ -209,15 +199,10 @@
 		/* Wait until operation completed */
 		do {
 			/* Read I2C operation status */
-			temp =
-			    *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
-				      I2C_CNTRL2);
+			temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
  
-			if (0 ==
-			    (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START)))
-			{
-				if (0 ==
-				    (temp &
+			if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
+				if (0 == (temp &
 				     (I2C_CNTRL2_I2C_CFGERR |
 				      I2C_CNTRL2_I2C_TO_ERR))) {
 					op_status = TSI108_I2C_SUCCESS;
@@ -285,7 +285,7 @@
 /* PCI view of System Memory */
 #define CFG_PCI_MEMORY_BUS	0x00000000
 #define CFG_PCI_MEMORY_PHYS	0x00000000
-#define CFG_PCI_MEMORY_SIZE	0x80000000	
+#define CFG_PCI_MEMORY_SIZE	0x80000000
  
 /* PCI Memory Space */
 #define CFG_PCI_MEM_BUS		(CFG_PCI_MEM_PHYS)
...	...	@@ -47,7 +47,7 @@
47	47	void after_reloc (ulong dest_addr)
48	48	{
49	49	DECLARE_GLOBAL_DATA_PTR;
50		-
	50	+
51	51	/*
52	52	* Jump to the main U-Boot board init code
53	53	*/
...	...	@@ -179,7 +179,7 @@
179	179	ulong temp, i;
180	180	ulong reg_val;
181	181	volatile ulong *reg_ptr;
182		-
	182	+
183	183	reg_ptr =
184	184	(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
185	185
...	...	@@ -300,7 +300,7 @@
300	300	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
301	301	0x7C0F2000);
302	302	__asm__ __volatile__ ("sync");
303		-
	303	+
304	304	/*
305	305	* Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
306	306	* value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
...	...	@@ -312,7 +312,7 @@
312	312	/* Make sure that OCN_BAR2 decoder is set (to allow following
313	313	* immediate read from SDRAM)
314	314	*/
315		-
	315	+
316	316	temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
317	317	__asm__ __volatile__ ("sync");
318	318
319	319
...	...	@@ -327,11 +327,11 @@
327	327	* and enable all HLP banks and not just HLP 0 as is being done for
328	328	* Taiga Rev. 2.
329	329	*/
330		-
	330	+
331	331	env_init ();
332	332
333	333	#ifndef DISABLE_PBM
334		-
	334	+
335	335	/*
336	336	* For IBM processors we have to set Address-Only commands generated
337	337	* by PBM that are different from ones set after reset.
338	338
...	...	@@ -475,10 +475,10 @@
475	475
476	476	for (i = 0; i < 32; i++) {
477	477	reg_ptr++ = reg_val; / P2O_BAR3_LUTx */
478		-
	478	+
479	479	/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
480		- *reg_ptr++ = 0;
481		-
	480	+ *reg_ptr++ = 0;
	481	+
482	482	/* offset = 16MB, address translation is enabled to allow byte swapping */
483	483	reg_val += 0x01000000;
484	484	}
...	...	@@ -507,7 +507,7 @@
507	507
508	508	#endif /* !DISABLE_PBM */
509	509
510		-#ifdef ENABLE_PCI_CSR_BAR
	510	+#ifdef ENABLE_PCI_CSR_BAR
511	511	/* open if required access to Tsi108 CSRs from the PCI/X bus */
512	512	/* enable BAR0 on the PCI/X bus */
513	513	reg_val = in32(CFG_TSI108_CSR_BASE +
...	...	@@ -528,7 +528,7 @@
528	528	/*
529	529	* Finally enable PCI/X Bus Master and Memory Space access
530	530	*/
531		-
	531	+
532	532	reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
533	533	reg_val \|= 0x06;
534	534	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
...	...	@@ -555,7 +555,7 @@
555	555	* Ensure that Machine Check exception is enabled
556	556	* We need it to support PCI Bus probing (configuration reads)
557	557	*/
558		-
	558	+
559	559	reg_val = mfmsr ();
560	560	mtmsr(reg_val \| MSR_ME);
561	561
...	...	@@ -631,7 +631,7 @@
631	631	* thing done with regards to enabling diabling the cache.
632	632	* So this seems like a good place to print all this information
633	633	*/
634		-
	634	+
635	635	printf ("CACHE: ");
636	636	switch (get_cpu_type()) {
637	637	case CPU_7447A:
...	...	@@ -308,9 +308,9 @@
308	308	u32 *p;
309	309	ulong clock;
310	310	int len;
311		-
	311	+
312	312	clock = bd->bi_busfreq;
313		-
	313	+
314	314	p = ft_get_prop (blob, "/cpus/" OF_CPU "/bus-frequency", &len);
315	315	if (p != NULL)
316	316	*p = cpu_to_be32 (clock);
...	...	@@ -168,8 +168,8 @@
168	168	static void program_mode(unsigned long *dimm_populated,
169	169	unsigned char *iic0_dimm_addr,
170	170	unsigned long num_dimm_banks,
171		- ddr_cas_id_t *selected_cas,
172		- int *write_recovery);
	171	+ ddr_cas_id_t *selected_cas,
	172	+ int *write_recovery);
173	173	static void program_tr(unsigned long *dimm_populated,
174	174	unsigned char *iic0_dimm_addr,
175	175	unsigned long num_dimm_banks);
...	...	@@ -185,7 +185,7 @@
185	185	static void program_initplr(unsigned long *dimm_populated,
186	186	unsigned char *iic0_dimm_addr,
187	187	unsigned long num_dimm_banks,
188		- ddr_cas_id_t selected_cas,
	188	+ ddr_cas_id_t selected_cas,
189	189	int write_recovery);
190	190	static unsigned long is_ecc_enabled(void);
191	191	static void program_ecc(unsigned long *dimm_populated,
...	...	@@ -1110,7 +1110,7 @@
1110	1110	modt3 = 0x00000000;
1111	1111	}
1112	1112	}
1113		- } else {
	1113	+ } else {
1114	1114	codt \|= SDRAM_CODT_DQS_2_5_V_DDR1;
1115	1115	modt0 = 0x00000000;
1116	1116	modt1 = 0x00000000;
...	...	@@ -1149,7 +1149,7 @@
1149	1149	static void program_initplr(unsigned long *dimm_populated,
1150	1150	unsigned char *iic0_dimm_addr,
1151	1151	unsigned long num_dimm_banks,
1152		- ddr_cas_id_t selected_cas,
	1152	+ ddr_cas_id_t selected_cas,
1153	1153	int write_recovery)
1154	1154	{
1155	1155	u32 cas = 0;
...	...	@@ -1858,11 +1858,11 @@
1858	1858	#endif /* CONFIG_405EP */
1859	1859
1860	1860	#if defined(CONFIG_440)
1861		-#define function_prolog(func_name) .text; \
	1861	+#define function_prolog(func_name) .text; \
1862	1862	.align 2; \
1863	1863	.globl func_name; \
1864	1864	func_name:
1865		-#define function_epilog(func_name) .type func_name,@function; \
	1865	+#define function_epilog(func_name) .type func_name,@function; \
1866	1866	.size func_name,.-func_name
1867	1867
1868	1868	/*----------------------------------------------------------------------------+
1869	1869
1870	1870
...	...	@@ -1916,44 +1916,44 @@
1916	1916	/*----------------------------------------------------------------------------+
1917	1917	\| dcbz_area.
1918	1918	+----------------------------------------------------------------------------*/
1919		- function_prolog(dcbz_area)
1920		- rlwinm. r5,r4,0,27,31
1921		- rlwinm r5,r4,27,5,31
1922		- beq ..d_ra2
1923		- addi r5,r5,0x0001
1924		-..d_ra2:mtctr r5
1925		-..d_ag2:dcbz r0,r3
1926		- addi r3,r3,32
1927		- bdnz ..d_ag2
1928		- sync
1929		- blr
1930		- function_epilog(dcbz_area)
	1919	+ function_prolog(dcbz_area)
	1920	+ rlwinm. r5,r4,0,27,31
	1921	+ rlwinm r5,r4,27,5,31
	1922	+ beq ..d_ra2
	1923	+ addi r5,r5,0x0001
	1924	+..d_ra2:mtctr r5
	1925	+..d_ag2:dcbz r0,r3
	1926	+ addi r3,r3,32
	1927	+ bdnz ..d_ag2
	1928	+ sync
	1929	+ blr
	1930	+ function_epilog(dcbz_area)
1931	1931
1932	1932	/*----------------------------------------------------------------------------+
1933	1933	\| dflush. Assume 32K at vector address is cachable.
1934	1934	+----------------------------------------------------------------------------*/
1935		- function_prolog(dflush)
1936		- mfmsr r9
1937		- rlwinm r8,r9,0,15,13
1938		- rlwinm r8,r8,0,17,15
1939		- mtmsr r8
1940		- addi r3,r0,0x0000
1941		- mtspr dvlim,r3
1942		- mfspr r3,ivpr
1943		- addi r4,r0,1024
1944		- mtctr r4
	1935	+ function_prolog(dflush)
	1936	+ mfmsr r9
	1937	+ rlwinm r8,r9,0,15,13
	1938	+ rlwinm r8,r8,0,17,15
	1939	+ mtmsr r8
	1940	+ addi r3,r0,0x0000
	1941	+ mtspr dvlim,r3
	1942	+ mfspr r3,ivpr
	1943	+ addi r4,r0,1024
	1944	+ mtctr r4
1945	1945	..dflush_loop:
1946		- lwz r6,0x0(r3)
1947		- addi r3,r3,32
1948		- bdnz ..dflush_loop
1949		- addi r3,r3,-32
1950		- mtctr r4
1951		-..ag: dcbf r0,r3
1952		- addi r3,r3,-32
1953		- bdnz ..ag
1954		- sync
1955		- mtmsr r9
1956		- blr
1957		- function_epilog(dflush)
	1946	+ lwz r6,0x0(r3)
	1947	+ addi r3,r3,32
	1948	+ bdnz ..dflush_loop
	1949	+ addi r3,r3,-32
	1950	+ mtctr r4
	1951	+..ag: dcbf r0,r3
	1952	+ addi r3,r3,-32
	1953	+ bdnz ..ag
	1954	+ sync
	1955	+ mtmsr r9
	1956	+ blr
	1957	+ function_epilog(dflush)
1958	1958	#endif /* CONFIG_440 */
...	...	@@ -92,7 +92,7 @@
92	92	CPU Core Frequency (MHz)
93	93	Bus Frequency
94	94	123456 100 133 167 200 Ratio
95		-
	95	+
96	96	------
97	97	SW2=101100 500 667 833 1000 5x
98	98	SW2=100100 550 733 917 1100 5.5x
99	99
100	100
101	101
102	102
103	103
104	104
105	105
...	...	@@ -109,43 +109,43 @@
109	109
110	110	SW2[7-8]: Bus Protocol and CPU Reset Option
111	111
112		- 7
	112	+ 7
113	113	-
114	114	SW2=0 System bus uses MPX bus protocol
115	115	SW2=1 System bus uses 60x bus protocol
116	116
117		- 8
	117	+ 8
118	118	-
119	119	SW2=0 TSI108 can cause CPU reset
120	120	SW2=1 TSI108 can not cause CPU reset
121	121
122	122	SW3[1-8] system options
123	123
124		- 123
	124	+ 123
125	125	---
126	126	SW3=xxx Connected to GPIO[0:2] on TSI108
127	127
128		- 4
	128	+ 4
129	129	-
130	130	SW3=0 CPU boots from low half of flash
131	131	SW3=1 CPU boots from high half of flash
132	132
133		- 5
	133	+ 5
134	134	-
135	135	SW3=0 SATA and slot2 connected to PCI bus
136	136	SW3=1 Only slot1 connected to PCI bus
137	137
138		- 6
	138	+ 6
139	139	-
140	140	SW3=0 USB connected to PCI bus
141	141	SW3=1 USB disconnected from PCI bus
142	142
143		- 7
	143	+ 7
144	144	-
145	145	SW3=0 Flash is write protected
146	146	SW3=1 Flash is NOT write protected
147	147
148		- 8
	148	+ 8
149	149	-
150	150	SW3=0 CPU will boot from flash
151	151	SW3=1 CPU will boot from PromJet
152	152
153	153
...	...	@@ -166,19 +166,19 @@
166	166	Bus Frequency (MHz)
167	167	---
168	168	SW4=000 external clock
169		- SW4=011 system clock
	169	+ SW4=011 system clock
170	170	SW4=100 133
171	171	SW4=101 166
172	172	SW4=110 200
173	173	others reserved
174	174
175	175	SW4[7-8]: PCI/PCI-X frequency control
176		- 7
	176	+ 7
177	177	-
178	178	SW4=0 PCI/PCI-X bus operates normally
179	179	SW4=1 PCI bus forced to PCI-33 mode
180	180
181		- 8
	181	+ 8
182	182	-
183	183	SW4=0 PCI-X mode at 133 MHz allowed
184	184	SW4=1 PCI-X mode limited to 100 MHz
...	...	@@ -82,15 +82,10 @@
82	82	/* Wait until operation completed */
83	83	do {
84	84	/* Read I2C operation status */
85		- temp =
86		- (u32 ) (CFG_TSI108_CSR_BASE + chan_offset +
87		- I2C_CNTRL2);
	85	+ temp = (u32 ) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
88	86
89		- if (0 ==
90		- (temp & (I2C_CNTRL2_RD_STATUS \| I2C_CNTRL2_START)))
91		- {
92		- if (0 ==
93		- (temp &
	87	+ if (0 == (temp & (I2C_CNTRL2_RD_STATUS \| I2C_CNTRL2_START))) {
	88	+ if (0 == (temp &
94	89	(I2C_CNTRL2_I2C_CFGERR \|
95	90	I2C_CNTRL2_I2C_TO_ERR))
96	91	) {
...	...	@@ -152,9 +147,7 @@
152	147	/* Check for valid I2C address */
153	148	if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
154	149	while (len--) {
155		- op_status =
156		- i2c_read_byte(i2c_if, chip_addr, byte_addr++,
157		- buffer++);
	150	+ op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++);
158	151
159	152	if (TSI108_I2C_SUCCESS != op_status) {
160	153	DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
...	...	@@ -182,10 +175,7 @@
182	175	/* Check if I2C operation is in progress */
183	176	temp = (u32 ) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
184	177
185		- if (0 ==
186		- (temp &
187		- (I2C_CNTRL2_RD_STATUS \| I2C_CNTRL2_WR_STATUS \| I2C_CNTRL2_START)))
188		- {
	178	+ if (0 == (temp & (I2C_CNTRL2_RD_STATUS \| I2C_CNTRL2_WR_STATUS \| I2C_CNTRL2_START))) {
189	179	/* Place data into the I2C Tx Register */
190	180	(u32 ) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
191	181	I2C_TX_DATA) = (u32) * buffer;
...	...	@@ -200,7 +190,7 @@
200	190	/* Issue the write command (at this moment all other parameters
201	191	* are 0 (size = 1 byte, lane = 0)
202	192	*/
203		-
	193	+
204	194	(u32 ) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
205	195	I2C_CNTRL2) = (I2C_CNTRL2_START);
206	196
207	197
...	...	@@ -209,15 +199,10 @@
209	199	/* Wait until operation completed */
210	200	do {
211	201	/* Read I2C operation status */
212		- temp =
213		- (u32 ) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
214		- I2C_CNTRL2);
	202	+ temp = (u32 ) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
215	203
216		- if (0 ==
217		- (temp & (I2C_CNTRL2_WR_STATUS \| I2C_CNTRL2_START)))
218		- {
219		- if (0 ==
220		- (temp &
	204	+ if (0 == (temp & (I2C_CNTRL2_WR_STATUS \| I2C_CNTRL2_START))) {
	205	+ if (0 == (temp &
221	206	(I2C_CNTRL2_I2C_CFGERR \|
222	207	I2C_CNTRL2_I2C_TO_ERR))) {
223	208	op_status = TSI108_I2C_SUCCESS;
...	...	@@ -285,7 +285,7 @@
285	285	/* PCI view of System Memory */
286	286	#define CFG_PCI_MEMORY_BUS 0x00000000
287	287	#define CFG_PCI_MEMORY_PHYS 0x00000000
288		-#define CFG_PCI_MEMORY_SIZE 0x80000000
	288	+#define CFG_PCI_MEMORY_SIZE 0x80000000
289	289
290	290	/* PCI Memory Space */
291	291	#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS)