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Commit 649acfe149e8a534a17eab54004a51d69b5556ed

Authored by Wolfgang Denk
Committed by Tom Rini
1 parent d770f3961f
Exists in master and in 50 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

MPC824x: remove obsolete "PN62" board 

The MPC824x processors have long reached EOL, and the PN62 board has
not seen any board-specific updates for more than a decade.  It is now
causing build issues.  Instead of wasting time on things nobody is
interested in any more, we rather drop this board.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Grandegger <wg@grandegger.com>
cc: Tom Rini <trini@ti.com>

Showing 11 changed files with 4 additions and 990 deletions Side-by-side Diff

... ... @@ -143,7 +143,7 @@
143 143  
144 144 N: Dr. Wolfgang Grandegger
145 145 E: wg@denx.de
146   -D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
  146 +D: Support for Interphase 4539 T1/E1/J1 PMC, CCM, SCM boards
147 147 W: www.denx.de
148 148  
149 149 N: Peter Figuli
arch/powerpc/cpu/mpc824x/cpu_init.c
Diff comments   View file @ 649acfe
... ... @@ -52,7 +52,7 @@
52 52 CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
53 53 /* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
54 54  
55   -#if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62)
  55 +#if defined(CONFIG_MUSENKI)
56 56 /* Why is this here, you ask? Try, just try setting 0x8000
57 57 * in PCIACR with CONFIG_WRITE_HALFWORD()
58 58 * this one was a stumper, and we are annoyed
59 59  
... ... @@ -142,9 +142,7 @@
142 142  
143 143 CONFIG_READ_WORD(PICR2, val);
144 144 val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
145   -#ifndef CONFIG_PN62
146 145 val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
147   -#endif
148 146 CONFIG_WRITE_WORD(PICR2, val);
149 147  
150 148 CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
... ... @@ -186,7 +184,7 @@
186 184 * should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
187 185 * its not set, we define it to zero in this file
188 186 */
189   -#if defined(CONFIG_CU824) || defined(CONFIG_PN62)
  187 +#if defined(CONFIG_CU824)
190 188 CONFIG_WRITE_WORD(MCCR4,
191 189 (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
192 190 (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
board/pn62/Makefile
View file @ 649acfe
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = pn62.o cmd_pn62.o misc.o
board/pn62/cmd_pn62.c
View file @ 649acfe
1   -/*
2   - * (C) Copyright 2002
3   - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <malloc.h>
10   -#include <net.h>
11   -#include <asm/io.h>
12   -#include <pci.h>
13   -#include <command.h>
14   -#include "pn62.h"
15   -
16   -#if defined(CONFIG_CMD_BSP)
17   -
18   -/*
19   - * Command led: controls the various LEDs 0..11 on the PN62 card.
20   - */
21   -int do_led(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
22   -{
23   - unsigned int number, function;
24   -
25   - if (argc != 3)
26   - return cmd_usage(cmdtp);
27   -
28   - number = simple_strtoul(argv[1], NULL, 10);
29   - if (number > PN62_LED_MAX)
30   - return 1;
31   -
32   - function = simple_strtoul(argv[2], NULL, 16);
33   - set_led(number, function);
34   - return 0;
35   -}
36   -U_BOOT_CMD(
37   - led , 3, 1, do_led,
38   - "set LED 0..11 on the PN62 board",
39   - "i fun"
40   - " - set 'i'th LED to function 'fun'"
41   -);
42   -
43   -/*
44   - * Command loadpci: loads a image over PCI.
45   - */
46   -#define CMD_MOVE_WINDOW 0x1
47   -#define CMD_BOOT_IMAGE 0x2
48   -
49   -int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
50   -{
51   - char *s;
52   - ulong addr = 0, count = 0;
53   - u32 off;
54   - int cmd, rcode = 0;
55   -
56   - /* pre-set load_addr */
57   - if ((s = getenv("loadaddr")) != NULL) {
58   - addr = simple_strtoul(s, NULL, 16);
59   - }
60   -
61   - switch (argc) {
62   - case 1:
63   - break;
64   - case 2:
65   - addr = simple_strtoul(argv[1], NULL, 16);
66   - break;
67   - default:
68   - return cmd_usage(cmdtp);
69   - }
70   -
71   - printf ("## Ready for image download ...\n");
72   -
73   - show_startup_phase(12);
74   -
75   - while (1) {
76   - /* Alive indicator */
77   - i2155x_write_scrapad(BOOT_PROTO, BOOT_PROTO_READY);
78   -
79   - /* Toggle status LEDs */
80   - cmd = (count / 200) % 4; /* downscale */
81   - set_led(4, cmd == 0 ? LED_1 : LED_0);
82   - set_led(5, cmd == 1 ? LED_1 : LED_0);
83   - set_led(6, cmd == 2 ? LED_1 : LED_0);
84   - set_led(7, cmd == 3 ? LED_1 : LED_0);
85   - udelay(1000);
86   - count++;
87   -
88   - cmd = i2155x_read_scrapad(BOOT_CMD);
89   -
90   - if (cmd == BOOT_CMD_MOVE) {
91   - off = i2155x_read_scrapad(BOOT_DATA);
92   - off += addr;
93   - i2155x_set_bar_base(3, off);
94   - printf ("## BAR3 Addr moved = 0x%08x\n", off);
95   - i2155x_write_scrapad(BOOT_CMD, ~cmd);
96   - show_startup_phase(13);
97   - }
98   - else if (cmd == BOOT_CMD_BOOT) {
99   - set_led(4, LED_1);
100   - set_led(5, LED_1);
101   - set_led(6, LED_1);
102   - set_led(7, LED_1);
103   -
104   - i2155x_write_scrapad(BOOT_CMD, ~cmd);
105   - show_startup_phase(14);
106   - break;
107   - }
108   -
109   - /* Abort if ctrl-c was pressed */
110   - if (ctrlc()) {
111   - printf("\nAbort\n");
112   - return 0;
113   - }
114   -
115   - }
116   -
117   - /* Repoint to the default shared memory */
118   - i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
119   -
120   - load_addr = addr;
121   - printf ("## Start Addr = 0x%08lx\n", addr);
122   -
123   - show_startup_phase(15);
124   -
125   - /* Loading ok, check if we should attempt an auto-start */
126   - if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) {
127   - char *local_args[2];
128   - local_args[0] = argv[0];
129   - local_args[1] = NULL;
130   -
131   - printf ("Automatic boot of image at addr 0x%08lX ...\n",
132   - load_addr);
133   - rcode = do_bootm (cmdtp, 0, 1, local_args);
134   - }
135   -
136   - return rcode;
137   -}
138   -
139   -U_BOOT_CMD(
140   - loadpci, 2, 1, do_loadpci,
141   - "load binary file over PCI",
142   - "[addr]\n"
143   - " - load binary file over PCI to address 'addr'"
144   -);
145   -
146   -#endif
board/pn62/misc.c
View file @ 649acfe
1   -/*
2   - * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <common.h>
8   -#include <mpc824x.h>
9   -#include <asm/io.h>
10   -#include <pci.h>
11   -
12   -#include "pn62.h"
13   -
14   -typedef struct {
15   - pci_dev_t devno;
16   - volatile u32 *csr;
17   -
18   -} i2155x_t;
19   -
20   -static i2155x_t i2155x = { 0, NULL };
21   -
22   -static struct pci_device_id i2155x_ids[] = {
23   - { 0x1011, 0x0046 }, /* i21554 */
24   - { 0x8086, 0xb555 } /* i21555 */
25   -};
26   -
27   -int i2155x_init(void)
28   -{
29   - pci_dev_t devno;
30   - u32 val;
31   - int i;
32   -
33   - /*
34   - * Find the Intel bridge.
35   - */
36   - if ((devno = pci_find_devices(i2155x_ids, 0)) < 0) {
37   - printf("Error: Intel bridge 2155x not found!\n");
38   - return -1;
39   - }
40   - i2155x.devno = devno;
41   -
42   - /*
43   - * Get auto-configured base address for CSR access.
44   - */
45   - pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &val);
46   - if (val & PCI_BASE_ADDRESS_SPACE_IO) {
47   - val &= PCI_BASE_ADDRESS_IO_MASK;
48   - i2155x.csr = (volatile u32 *)(_IO_BASE + val);
49   - } else {
50   - val &= PCI_BASE_ADDRESS_MEM_MASK;
51   - i2155x.csr = (volatile u32 *)val;
52   - }
53   -
54   - /*
55   - * Translate downstream memory 2 (bar3) to base of shared memory.
56   - */
57   - i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
58   -
59   - /*
60   - * Enable memory space, I/O space and bus master bits
61   - * in both Primary and Secondary command registers.
62   - */
63   - val = PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_IO;
64   - pci_write_config_word(devno, 0x44, val);
65   - pci_write_config_word(devno, 0x04, val);
66   -
67   - /*
68   - * Clear scratchpad registers.
69   - */
70   - for (i = 0; i < (I2155X_SCRAPAD_MAX - 1); i++) {
71   - i2155x_write_scrapad(i, 0x0);
72   - }
73   -
74   - /*
75   - * Set interrupt line for Linux.
76   - */
77   - pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 3);
78   -
79   - return 0;
80   -}
81   -
82   -/*
83   - * Access the Scratchpad registers 0..7 of the Intel bridge.
84   - */
85   -void i2155x_write_scrapad(int idx, u32 val)
86   -{
87   - if (idx >= 0 && idx < I2155X_SCRAPAD_MAX)
88   - out_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx, val);
89   - else
90   - printf("i2155x_write_scrapad: invalid index\n");
91   -}
92   -
93   -u32 i2155x_read_scrapad(int idx)
94   -{
95   - if (idx >= 0 && idx < I2155X_SCRAPAD_MAX)
96   - return in_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx);
97   - else
98   - printf("i2155x_read_scrapad: invalid index\n");
99   - return -1;
100   -}
101   -
102   -void i2155x_set_bar_base(int bar, u32 base)
103   -{
104   - if (bar >= 2 && bar <= 4) {
105   - pci_write_config_dword(i2155x.devno,
106   - I2155X_BAR2_BASE + (bar - 2) * 4,
107   - base);
108   - }
109   -}
110   -
111   -/*
112   - * Read Vital Product Data (VPD) from the Serial EPROM attached
113   - * to the Intel bridge.
114   - */
115   -int i2155x_read_vpd(int offset, int size, unsigned char *data)
116   -{
117   - int i, n;
118   - u16 val16;
119   -
120   - for (i = 0; i < size; i++) {
121   - pci_write_config_word(i2155x.devno, I2155X_VPD_ADDR,
122   - offset + i - I2155X_VPD_START);
123   - for (n = 10000; n > 0; n--) {
124   - pci_read_config_word(i2155x.devno, I2155X_VPD_ADDR, &val16);
125   - if ((val16 & 0x8000) != 0) /* wait for completion */
126   - break;
127   - udelay(100);
128   - }
129   - if (n == 0) {
130   - printf("i2155x_read_vpd: TIMEOUT\n");
131   - return -1;
132   - }
133   -
134   - pci_read_config_byte(i2155x.devno, I2155X_VPD_DATA, &data[i]);
135   - }
136   -
137   - return i;
138   -}
139   -
140   -static struct pci_device_id am79c95x_ids [] = {
141   - { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE },
142   - { }
143   -};
144   -
145   -
146   -/*
147   - * Initialize the AMD ethernet controllers.
148   - */
149   -int am79c95x_init(void)
150   -{
151   - pci_dev_t devno;
152   - int i;
153   -
154   - /*
155   - * Set interrupt line for Linux.
156   - */
157   - for (i = 0; i < 2; i++) {
158   - if ((devno = pci_find_devices(am79c95x_ids, i)) < 0)
159   - break;
160   - pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 2+i);
161   - }
162   - if (i < 2)
163   - printf("Error: Only %d AMD Ethernet Controller found!\n", i);
164   -
165   - return 0;
166   -}
167   -
168   -
169   -void set_led(unsigned int number, unsigned int function)
170   -{
171   - volatile u8 *addr;
172   -
173   - if ((number >= 0) && (number < PN62_LED_MAX) &&
174   - (function >= 0) && (function <= LED_LAST_FUNCTION)) {
175   - addr = (volatile u8 *)(PN62_LED_BASE + number * 8);
176   - out_8(addr, function&0xff);
177   - }
178   -}
179   -
180   -/*
181   - * Show fatal error indicated by Kinght Rider(tm) effect
182   - * in LEDS 0-7. LEDS 8-11 contain 4 bit error code.
183   - * Note: this function will not terminate.
184   - */
185   -void fatal_error(unsigned int error_code)
186   -{
187   - int i, d;
188   -
189   - for (i = 0; i < 12; i++) {
190   - set_led(i, LED_0);
191   - }
192   -
193   - /*
194   - * Write error code.
195   - */
196   - set_led(8, (error_code & 0x01) ? LED_1 : LED_0);
197   - set_led(9, (error_code & 0x02) ? LED_1 : LED_0);
198   - set_led(10, (error_code & 0x04) ? LED_1 : LED_0);
199   - set_led(11, (error_code & 0x08) ? LED_1 : LED_0);
200   -
201   - /*
202   - * Yay - Knight Rider effect!
203   - */
204   - while(1) {
205   - unsigned int delay = 2000;
206   -
207   - for (i = 0; i < 8; i++) {
208   - set_led(i, LED_1);
209   - for (d = 0; d < delay; d++);
210   - set_led(i, LED_0);
211   - }
212   -
213   - for (i = 7; i > 0; i--) {
214   - set_led(i, LED_1);
215   - for (d = 0; d < delay; d++);
216   - set_led(i, LED_0);
217   - }
218   - }
219   -}
board/pn62/pn62.c
View file @ 649acfe
1   -/*
2   - * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <common.h>
8   -#include <mpc824x.h>
9   -#include <net.h>
10   -#include <pci.h>
11   -#include <netdev.h>
12   -
13   -#include "pn62.h"
14   -
15   -DECLARE_GLOBAL_DATA_PTR;
16   -
17   -static int get_serial_number (char *string, int size);
18   -static void get_mac_address(int id, u8 *mac);
19   -
20   -#ifdef CONFIG_SHOW_BOOT_PROGRESS
21   -void show_boot_progress (int phase)
22   -{
23   - /*
24   - * Show phases of the bootm command on the front panel
25   - * LEDs and the scratchpad register #3 as well. We use
26   - * blinking LEDs for logical "1".
27   - */
28   - if (phase > 0) {
29   - set_led (8, (phase & 0x1) ? LED_SLOW_CLOCK : LED_0);
30   - set_led (9, (phase & 0x2) ? LED_SLOW_CLOCK : LED_0);
31   - set_led (10, (phase & 0x4) ? LED_SLOW_CLOCK : LED_0);
32   - set_led (11, (phase & 0x8) ? LED_SLOW_CLOCK : LED_0);
33   - }
34   - i2155x_write_scrapad (BOOT_STATUS, phase);
35   - if (phase < 0)
36   - i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR);
37   -}
38   -#endif
39   -
40   -void show_startup_phase (int phase)
41   -{
42   - /*
43   - * Show the phase of U-Boot startup on the front panel
44   - * LEDs and the scratchpad register #3 as well.
45   - */
46   - if (phase > 0) {
47   - set_led (8, (phase & 0x1) ? LED_1 : LED_0);
48   - set_led (9, (phase & 0x2) ? LED_1 : LED_0);
49   - set_led (10, (phase & 0x4) ? LED_1 : LED_0);
50   - set_led (11, (phase & 0x8) ? LED_1 : LED_0);
51   - }
52   - i2155x_write_scrapad (BOOT_STATUS, phase);
53   - if (phase < 0)
54   - i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR);
55   -}
56   -
57   -int checkboard (void)
58   -{
59   - show_startup_phase (1);
60   - puts ("Board: PN62\n");
61   - return 0;
62   -}
63   -
64   -phys_size_t initdram (int board_type)
65   -{
66   - long size;
67   - long new_bank0_end;
68   - long mear1;
69   - long emear1;
70   -
71   - show_startup_phase (2);
72   -
73   - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
74   -
75   - new_bank0_end = size - 1;
76   - mear1 = mpc824x_mpc107_getreg (MEAR1);
77   - emear1 = mpc824x_mpc107_getreg (EMEAR1);
78   - mear1 = (mear1 & 0xFFFFFF00) |
79   - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
80   - emear1 = (emear1 & 0xFFFFFF00) |
81   - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
82   - mpc824x_mpc107_setreg (MEAR1, mear1);
83   - mpc824x_mpc107_setreg (EMEAR1, emear1);
84   -
85   - return (size);
86   -}
87   -
88   -/*
89   - * Initialize PCI Devices. We rely on auto-configuration.
90   - */
91   -#ifndef CONFIG_PCI_PNP
92   -#error "CONFIG_PCI_PNP is not defined, please correct!"
93   -#endif
94   -
95   -struct pci_controller hose = {
96   -};
97   -
98   -void pci_init_board (void)
99   -{
100   - show_startup_phase (4);
101   - pci_mpc824x_init (&hose);
102   -
103   - show_startup_phase (5);
104   - i2155x_init ();
105   - show_startup_phase (6);
106   - am79c95x_init ();
107   - show_startup_phase (7);
108   -}
109   -
110   -int misc_init_r (void)
111   -{
112   - char str[20];
113   - u8 mac[6];
114   -
115   - show_startup_phase (8);
116   - /*
117   - * Get serial number and ethernet addresses if not already defined
118   - * and update the board info structure and the environment.
119   - */
120   - if (getenv ("serial#") == NULL &&
121   - get_serial_number (str, strlen (str)) > 0) {
122   - setenv ("serial#", str);
123   - }
124   - show_startup_phase (9);
125   -
126   - if (!eth_getenv_enetaddr("ethaddr", mac)) {
127   - get_mac_address(0, mac);
128   - eth_setenv_enetaddr("ethaddr", mac);
129   - }
130   - show_startup_phase (10);
131   -
132   -#ifdef CONFIG_HAS_ETH1
133   - if (!eth_getenv_enetaddr("eth1addr", mac)) {
134   - get_mac_address(1, mac);
135   - eth_setenv_enetaddr("eth1addr", mac);
136   - }
137   -#endif /* CONFIG_HAS_ETH1 */
138   - show_startup_phase (11);
139   -
140   - /* Tell everybody that U-Boot is up and runnig */
141   - i2155x_write_scrapad (0, 0x12345678);
142   - return (0);
143   -}
144   -
145   -static int get_serial_number (char *string, int size)
146   -{
147   - int i;
148   - char c;
149   -
150   - if (size < I2155X_VPD_SN_SIZE)
151   - size = I2155X_VPD_SN_SIZE;
152   - for (i = 0; i < (size - 1); i++) {
153   - i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, (uchar *)&c);
154   - if (c == '\0')
155   - break;
156   - string[i] = c;
157   - }
158   - string[i] = '\0'; /* make sure it's terminated */
159   -
160   - return i;
161   -}
162   -
163   -static void get_mac_address(int id, u8 *mac)
164   -{
165   - i2155x_read_vpd (I2155X_VPD_MAC0_START + 6 * id, 6, mac);
166   -}
167   -
168   -int board_eth_init(bd_t *bis)
169   -{
170   - return pci_eth_init(bis);
171   -}
board/pn62/pn62.h
View file @ 649acfe
1   -/*
2   - * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#ifndef _PN62_H_
8   -#define _PN62_H_
9   -
10   -/*
11   - * Definitions for the Intel Bridge 21554 or 21555.
12   - */
13   -#define I2155X_VPD_ADDR 0xe6
14   -#define I2155X_VPD_DATA 0xe8
15   -
16   -#define I2155X_VPD_START 0x80
17   -#define I2155X_VPD_SN_START 0x80
18   -#define I2155X_VPD_SN_SIZE 0x10
19   -#define I2155X_VPD_MAC0_START 0x90
20   -#define I2155X_VPD_MAC1_START 0x96
21   -
22   -#define I2155X_SCRAPAD_ADDR 0xa8
23   -#define I2155X_SCRAPAD_MAX 8
24   -
25   -#define I2155X_BAR2_BASE 0x98
26   -#define I2155X_BAR3_BASE 0x9c
27   -#define I2155X_BAR4_BASE 0xa0
28   -
29   -#define I2155X_BAR2_SETUP 0xb0
30   -#define I2155X_BAR3_SETUP 0xb4
31   -#define I2155X_BAR4_SETUP 0xb8
32   -
33   -/*
34   - * Interrupt request numbers
35   - */
36   -#define PN62_IRQ_HOST 0x0
37   -#define PN62_IRQ_PLX9054 0x1
38   -#define PN62_IRQ_ETH0 0x2
39   -#define PN62_IRQ_ETH1 0x3
40   -#define PN62_IRQ_COM1 0x4
41   -#define PN62_IRQ_COM2 0x4
42   -
43   -/*
44   - * Miscellaneous definitons.
45   - */
46   -#define PN62_SMEM_DEFAULT 0x1f00000
47   -
48   -/*
49   - * Definitions for boot protocol using Scratchpad registers.
50   - */
51   -#define BOOT_DONE 0
52   -#define BOOT_DONE_CLEAR 0x00dead00
53   -#define BOOT_DONE_ERROR 0xbad0dead
54   -#define BOOT_DONE_U_BOOT 0x12345678
55   -#define BOOT_DONE_LINUX 0x87654321
56   -#define BOOT_CMD 1
57   -#define BOOT_CMD_MOVE 0x1
58   -#define BOOT_CMD_BOOT 0x2
59   -#define BOOT_DATA 2
60   -#define BOOT_PROTO 3
61   -#define BOOT_PROTO_READY 0x23456789
62   -#define BOOT_PROTO_CLEAR 0x00000000
63   -#define BOOT_STATUS 4
64   -
65   -/*
66   - * LED Definitions:
67   - */
68   -#define PN62_LED_BASE 0xff800300
69   -#define PN62_LED_MAX 12
70   -
71   -/*
72   - * LED0 - 7 mounted on top of board, D1 - D8
73   - * LED8 - 11 upper four LEDs on the front panel of the board.
74   - */
75   -#define LED_0 0x00 /* OFF */
76   -#define LED_1 0x01 /* ON */
77   -#define LED_SLOW_CLOCK 0x02 /* SLOW 1Hz ish */
78   -#define LED_nSLOW_CLOCK 0x03 /* inverse of above */
79   -#define LED_WATCHDOG_OUT 0x06 /* Reset Watchdog level */
80   -#define LED_WATCHDOG_CLOCK 0x07 /* clock to watchdog */
81   -
82   -/*
83   - * LED's currently setup in AMD79C973 device as the following:
84   - * LED0 100Mbit
85   - * LED1 LNKSE
86   - * LED2 TX Activity
87   - * LED3 RX Activity
88   - */
89   -#define LED_E0_LED0 0x08 /* Ethernet Port 0 LED 0 */
90   -#define LED_E0_LED1 0x09 /* Ethernet Port 0 LED 1 */
91   -#define LED_E0_LED2 0x0A /* Ethernet Port 0 LED 2 */
92   -#define LED_E0_LED3 0x0B /* Ethernet Port 0 LED 3 */
93   -#define LED_E1_LED0 0x0C /* Ethernet Port 1 LED 0 */
94   -#define LED_E1_LED1 0x0D /* Ethernet Port 1 LED 1 */
95   -#define LED_E1_LED2 0x0E /* Ethernet Port 1 LED 2 */
96   -#define LED_E1_LED3 0x0F /* Ethernet Port 1 LED 3 */
97   -#define LED_STROBE0 0x10 /* Processor Strobe 0 */
98   -#define LED_STROBE1 0x11 /* Processor Strobe 1 */
99   -#define LED_STROBE2 0x12 /* Processor Strobe 2 */
100   -#define LED_STROBE3 0x13 /* Processor Strobe 3 */
101   -#define LED_STROBE4 0x14 /* Processor Strobe 4 */
102   -#define LED_STROBE5 0x15 /* Processor Strobe 5 */
103   -#define LED_STROBE6 0x16 /* Processor Strobe 6 */
104   -#define LED_STROBE7 0x17 /* Processor Strobe 7 */
105   -#define LED_HOST_STROBE0 0x18 /* Host strobe 0 */
106   -#define LED_HOST_STROBE1 0x19 /* Host strobe 1 */
107   -#define LED_HOST_STROBE2 0x1A /* Host strobe 2 */
108   -#define LED_HOST_STROBE3 0x1B /* Host strobe 3 */
109   -#define LED_HOST_STROBE4 0x1C /* Host strobe 4 */
110   -#define LED_HOST_STROBE5 0x1D /* Host strobe 5 */
111   -#define LED_HOST_STROBE6 0x1E /* Host strobe 6 */
112   -#define LED_HOST_STROBE7 0x1F /* Host strobe 7 */
113   -#define LED_MPC_INT0 0x20 /* MPC8240 INT 0 */
114   -#define LED_MPC_INT1 0x21 /* MPC8240 INT 1 */
115   -#define LED_MPC_INT2 0x22 /* MPC8240 INT 2 */
116   -#define LED_MPC_INT3 0x23 /* MPC8240 INT 3 */
117   -#define LED_MPC_INT4 0x24 /* MPC8240 INT 4 */
118   -#define LED_UART0_CS 0x25 /* UART 0 Chip Select */
119   -#define LED_UART1_CS 0x26 /* UART 1 Chip Select */
120   -#define LED_SRAM_CS 0x27 /* SRAM Chip Select */
121   -#define LED_SRAM_WR 0x28 /* SRAM WR Signal */
122   -#define LED_SRAM_RD 0x29 /* SRAM RD Signal */
123   -#define LED_MPC_RCS0 0x2A /* MPC8240 RCS0 Signal */
124   -#define LED_S_PCI_FRAME 0x2B /* Secondary PCI Frame Signal */
125   -#define LED_MPC_CS0 0x2C /* MPC8240 CS0 Signal */
126   -#define LED_HOST_INT 0x2D /* MPC8240 to Host Interrupt signal */
127   -#define LED_LAST_FUNCTION LED_HOST_INT /* last function */
128   -
129   -/*
130   - * Forward declarations
131   - */
132   -int i2155x_init (void);
133   -void i2155x_write_scrapad(int idx, u32 val);
134   -u32 i2155x_read_scrapad (int idx);
135   -void i2155x_set_bar_base (int bar, u32 addr);
136   -int i2155x_read_vpd (int offset, int size, unsigned char *data);
137   -
138   -int am79c95x_init (void);
139   -
140   -void set_led (unsigned int number, unsigned int function);
141   -void fatal_error (unsigned int error_code);
142   -void show_startup_phase (int phase);
143   -
144   -
145   -#endif /* _PN62_H_ */
... ... @@ -632,7 +632,6 @@
632 632 Active powerpc mpc824x - - linkstation linkstation_HGLAN linkstation:HGLAN=1 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
633 633 Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
634 634 Active powerpc mpc824x - - mvblue MVBLUE - -
635   -Active powerpc mpc824x - - pn62 PN62 - Wolfgang Grandegger <wg@denx.de>
636 635 Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de>
637 636 Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com>
638 637 Active powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
doc/README.scrapyard
Diff comments   View file @ 649acfe
... ... @@ -11,6 +11,7 @@
11 11  
12 12 Board Arch CPU Commit Removed Last known maintainer/contact
13 13 =================================================================================================
  14 +pn62 powerpc mpc824x - 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
14 15 pdnb3 arm ixp - 2013-09-24 Stefan Roese <sr@denx.de>
15 16 scpu arm ixp - 2013-09-24 Stefan Roese <sr@denx.de>
16 17 omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta <kshitij@ti.com>
... ... @@ -291,16 +291,6 @@
291 291 /* Switch pcnet to 32bit mode */
292 292 pcnet_write_bcr(dev, 20, 2);
293 293  
294   -#ifdef CONFIG_PN62
295   - /* Setup LED registers */
296   - val = pcnet_read_bcr(dev, 2) | 0x1000;
297   - pcnet_write_bcr(dev, 2, val); /* enable LEDPE */
298   - pcnet_write_bcr(dev, 4, 0x5080); /* 100MBit */
299   - pcnet_write_bcr(dev, 5, 0x40c0); /* LNKSE */
300   - pcnet_write_bcr(dev, 6, 0x4090); /* TX Activity */
301   - pcnet_write_bcr(dev, 7, 0x4084); /* RX Activity */
302   -#endif
303   -
304 294 /* Set/reset autoselect bit */
305 295 val = pcnet_read_bcr(dev, 2) & ~2;
306 296 val |= 2;
include/configs/PN62.h
View file @ 649acfe
1   -/*
2   - * (C) Copyright 2002
3   - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/* ------------------------------------------------------------------------- */
9   -
10   -/*
11   - * board/config.h - configuration options, board specific
12   - */
13   -
14   -#ifndef __CONFIG_H
15   -#define __CONFIG_H
16   -
17   -/*
18   - * High Level Configuration Options
19   - * (easy to change)
20   - */
21   -
22   -#define CONFIG_MPC824X 1
23   -#define CONFIG_MPC8240 1
24   -#define CONFIG_PN62 1
25   -
26   -#define CONFIG_SYS_TEXT_BASE 0xFFF00000
27   -
28   -#define CONFIG_CONS_INDEX 1
29   -
30   -
31   -/*
32   - * BOOTP options
33   - */
34   -#define CONFIG_BOOTP_BOOTFILESIZE
35   -#define CONFIG_BOOTP_BOOTPATH
36   -#define CONFIG_BOOTP_GATEWAY
37   -#define CONFIG_BOOTP_HOSTNAME
38   -
39   -
40   -/*
41   - * Command line configuration.
42   - */
43   -#include <config_cmd_default.h>
44   -
45   -#define CONFIG_CMD_PCI
46   -#define CONFIG_CMD_BSP
47   -
48   -#undef CONFIG_CMD_FLASH
49   -#undef CONFIG_CMD_IMLS
50   -#undef CONFIG_CMD_LOADS
51   -#undef CONFIG_CMD_SAVEENV
52   -#undef CONFIG_CMD_SOURCE
53   -
54   -
55   -#define CONFIG_BAUDRATE 19200 /* console baudrate */
56   -
57   -#define CONFIG_BOOTDELAY 1 /* autoboot after n seconds */
58   -
59   -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
60   -
61   -#define CONFIG_SERVERIP 10.0.0.201
62   -#define CONFIG_IPADDR 10.0.0.200
63   -#define CONFIG_ROOTPATH "/opt/eldk/ppc_82xx"
64   -#define CONFIG_NETMASK 255.255.255.0
65   -#undef CONFIG_BOOTARGS
66   -#if 0
67   -/* Boot Linux with NFS root filesystem */
68   -#define CONFIG_BOOTCOMMAND \
69   - "setenv verify y;" \
70   - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
71   - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
72   - "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
73   - "loadp 100000; bootm"
74   - /* "tftpboot 100000 uImage; bootm" */
75   -#else
76   -/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
77   -#define CONFIG_BOOTCOMMAND \
78   - "setenv verify n;" \
79   - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
80   - "root=/dev/ram rw " \
81   - "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
82   - "loadp 200000; bootm"
83   -#endif
84   -
85   -/*
86   - * Miscellaneous configurable options
87   - */
88   -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
89   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
90   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
91   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
92   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
93   -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
94   -
95   -#define CONFIG_PRAM 1024 /* reserve 1 MB protected RAM */
96   -
97   -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
98   -
99   -#define CONFIG_HAS_ETH1 1 /* add support for eth1addr */
100   -
101   -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
102   -
103   -/*
104   - * PCI stuff
105   - */
106   -#define CONFIG_PCI /* include pci support */
107   -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
108   -#define CONFIG_PCI_PNP /* we need Plug 'n Play */
109   -#if 0
110   -#define CONFIG_PCI_SCAN_SHOW /* show PCI auto-scan at boot */
111   -#endif
112   -
113   -/*
114   - * Networking stuff
115   - */
116   -
117   -#define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */
118   -#define CONFIG_PCNET_79C973
119   -
120   -#define _IO_BASE 0xfe000000 /* points to PCI I/O space */
121   -
122   -
123   -/*
124   - * Start addresses for the final memory configuration
125   - * (Set up by the startup code)
126   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
127   - */
128   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
129   -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
130   -
131   -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
132   -
133   -#undef CONFIG_SYS_RAMBOOT
134   -#define CONFIG_SYS_MONITOR_LEN 0x00030000
135   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
136   -
137   -
138   -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
139   -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
140   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
141   -
142   -
143   -#define CONFIG_SYS_NO_FLASH 1 /* There is no FLASH memory */
144   -
145   -#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
146   -#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
147   -#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
148   -
149   -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
150   -
151   -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
152   -#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */
153   -
154   -/*
155   - * Serial port configuration
156   - */
157   -
158   -#define CONFIG_SYS_NS16550
159   -#define CONFIG_SYS_NS16550_SERIAL
160   -
161   -#define CONFIG_SYS_NS16550_REG_SIZE 1
162   -
163   -#define CONFIG_SYS_NS16550_CLK 1843200
164   -
165   -#define CONFIG_SYS_NS16550_COM1 0xff800008
166   -#define CONFIG_SYS_NS16550_COM2 0xff800000
167   -
168   -/*
169   - * Low Level Configuration Settings
170   - * (address mappings, register initial values, etc.)
171   - * You should know what you are doing if you make changes here.
172   - */
173   -
174   -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
175   -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
176   -
177   -#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
178   -
179   -/* MCCR1 */
180   -#define CONFIG_SYS_ROMNAL 3 /* rom/flash next access time */
181   -#define CONFIG_SYS_ROMFAL 7 /* rom/flash access time */
182   -
183   -/* MCCR2 */
184   -#define CONFIG_SYS_ASRISE 6 /* ASRISE in clocks */
185   -#define CONFIG_SYS_ASFALL 12 /* ASFALL in clocks */
186   -#define CONFIG_SYS_REFINT 5600 /* REFINT in clocks */
187   -
188   -/* MCCR3 */
189   -#define CONFIG_SYS_BSTOPRE 0x3cf /* Burst To Precharge */
190   -#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
191   -#define CONFIG_SYS_RDLAT 3 /* data latency from read command */
192   -
193   -/* MCCR4 */
194   -#define CONFIG_SYS_PRETOACT 1 /* Precharge to activate interval */
195   -#define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */
196   -#define CONFIG_SYS_ACTORW 2 /* Activate to R/W */
197   -#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
198   -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE Wrap type */
199   -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
200   -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
201   -
202   -/* Memory bank settings:
203   - *
204   - * only bits 20-29 are actually used from these vales to set the
205   - * start/qend address the upper two bits will be 0, and the lower 20
206   - * bits will be set to 0x00000 for a start address, or 0xfffff for an
207   - * end address
208   - */
209   -#define CONFIG_SYS_BANK0_START 0x00000000
210   -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
211   -#define CONFIG_SYS_BANK0_ENABLE 1
212   -#define CONFIG_SYS_BANK1_START 0x00000000
213   -#define CONFIG_SYS_BANK1_END 0x00000000
214   -#define CONFIG_SYS_BANK1_ENABLE 0
215   -#define CONFIG_SYS_BANK2_START 0x00000000
216   -#define CONFIG_SYS_BANK2_END 0x00000000
217   -#define CONFIG_SYS_BANK2_ENABLE 0
218   -#define CONFIG_SYS_BANK3_START 0x00000000
219   -#define CONFIG_SYS_BANK3_END 0x00000000
220   -#define CONFIG_SYS_BANK3_ENABLE 0
221   -#define CONFIG_SYS_BANK4_START 0x00000000
222   -#define CONFIG_SYS_BANK4_END 0x00000000
223   -#define CONFIG_SYS_BANK4_ENABLE 0
224   -#define CONFIG_SYS_BANK5_START 0x00000000
225   -#define CONFIG_SYS_BANK5_END 0x00000000
226   -#define CONFIG_SYS_BANK5_ENABLE 0
227   -#define CONFIG_SYS_BANK6_START 0x00000000
228   -#define CONFIG_SYS_BANK6_END 0x00000000
229   -#define CONFIG_SYS_BANK6_ENABLE 0
230   -#define CONFIG_SYS_BANK7_START 0x00000000
231   -#define CONFIG_SYS_BANK7_END 0x00000000
232   -#define CONFIG_SYS_BANK7_ENABLE 0
233   -
234   -/*
235   - * Memory bank enable bitmask, specifying which of the banks defined above
236   - * are actually present. MSB is for bank #7, LSB is for bank #0.
237   - */
238   -#define CONFIG_SYS_BANK_ENABLE 0x01
239   -
240   -#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
241   - /* see 8240 book for bit definitions */
242   -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
243   - /* currently accessed page in memory */
244   - /* see 8240 book for details */
245   -
246   -/* SDRAM 0 - 256MB */
247   -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
248   -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
249   -
250   -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
251   -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
252   -
253   -/* PCI memory space */
254   -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
255   -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
256   -
257   -/* Config addrs, etc */
258   -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
259   -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
260   -
261   -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
262   -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
263   -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
264   -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
265   -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
266   -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
267   -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
268   -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
269   -
270   -/*
271   - * For booting Linux, the board info and command line data
272   - * have to be in the first 8 MB of memory, since this is
273   - * the maximum mapped by the Linux kernel during initialization.
274   - */
275   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
276   -
277   -/*
278   - * Cache Configuration
279   - */
280   -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
281   -#if defined(CONFIG_CMD_KGDB)
282   -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
283   -#endif
284   -
285   -#endif /* __CONFIG_H */