Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 6615da4da36d1f0564adeb1b318e14532c3b1f3e

Authored by Peng Fan
Committed by Stefano Babic
1 parent 00ffa56d4b
Exists in v2017.01-smarct4x and in 28 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

imx: mx6ull: misc soc update 

Update misc SOC related settings for i.MX6ULL, such as FEC mac address,
cpu speed grading and mmdc channel mask clearing.

Also update s_init to skip pfd reset.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

Showing 1 changed file with 4 additions and 4 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ 6615da4
... ... @@ -126,7 +126,7 @@
126 126 val >>= OCOTP_CFG3_SPEED_SHIFT;
127 127 val &= 0x3;
128 128  
129   - if (is_mx6ul()) {
  129 + if (is_mx6ul() || is_mx6ull()) {
130 130 if (val == OCOTP_CFG3_SPEED_528MHZ)
131 131 return 528000000;
132 132 else if (val == OCOTP_CFG3_SPEED_696MHZ)
... ... @@ -293,7 +293,7 @@
293 293 reg = readl(&mxc_ccm->ccdr);
294 294  
295 295 /* Clear MMDC channel mask */
296   - if (is_mx6sx() || is_mx6ul() || is_mx6sl())
  296 + if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl())
297 297 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
298 298 else
299 299 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
... ... @@ -459,7 +459,7 @@
459 459 struct fuse_bank4_regs *fuse =
460 460 (struct fuse_bank4_regs *)bank->fuse_regs;
461 461  
462   - if ((is_mx6sx() || is_mx6ul()) && dev_id == 1) {
  462 + if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) {
463 463 u32 value = readl(&fuse->mac_addr2);
464 464 mac[0] = value >> 24 ;
465 465 mac[1] = value >> 16 ;
... ... @@ -523,7 +523,7 @@
523 523 u32 mask528;
524 524 u32 reg, periph1, periph2;
525 525  
526   - if (is_mx6sx() || is_mx6ul())
  526 + if (is_mx6sx() || is_mx6ul() || is_mx6ull())
527 527 return;
528 528  
529 529 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs