fsl: csu: add an API to set R/W permission to PCIe

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>

fsl: csu: add an API to set R/W permission to PCIe
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang · York Sun
1 parent c37fdbdbb0
Showing 3 changed files with 30 additions and 0 deletions Side-by-side Diff
arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
board/freescale/common/ns_access.c
include/fsl_csu.h
@@ -6,6 +6,7 @@
  
 #ifndef __FSL_NS_ACCESS_H_
 #define __FSL_NS_ACCESS_H_
+#include <fsl_csu.h>
  
 enum csu_cslx_ind {
 	CSU_CSLX_PCIE2_IO = 0,
@@ -8,6 +8,7 @@
 #include <asm/io.h>
 #include <fsl_csu.h>
 #include <asm/arch/ns_access.h>
+#include <asm/arch/fsl_serdes.h>
  
 void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)
 {
@@ -39,5 +40,32 @@
 void enable_layerscape_ns_access(void)
 {
 	enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+}
+
+void set_pcie_ns_access(int pcie, u16 val)
+{
+	switch (pcie) {
+#ifdef CONFIG_PCIE1
+	case PCIE1:
+		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val);
+		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val);
+		return;
+#endif
+#ifdef CONFIG_PCIE2
+	case PCIE2:
+		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val);
+		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val);
+		return;
+#endif
+#ifdef CONFIG_PCIE3
+	case PCIE3:
+		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val);
+		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val);
+		return;
+#endif
+	default:
+		debug("The PCIE%d doesn't exist!\n", pcie);
+		return;
+	}
 }
@@ -31,6 +31,7 @@
  
 void enable_layerscape_ns_access(void);
 void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val);
+void set_pcie_ns_access(int pcie, u16 val);
  
 #endif
...	...	@@ -6,6 +6,7 @@
6	6
7	7	#ifndef __FSL_NS_ACCESS_H_
8	8	#define __FSL_NS_ACCESS_H_
	9	+#include <fsl_csu.h>
9	10
10	11	enum csu_cslx_ind {
11	12	CSU_CSLX_PCIE2_IO = 0,
...	...	@@ -8,6 +8,7 @@
8	8	#include <asm/io.h>
9	9	#include <fsl_csu.h>
10	10	#include <asm/arch/ns_access.h>
	11	+#include <asm/arch/fsl_serdes.h>
11	12
12	13	void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)
13	14	{
...	...	@@ -39,5 +40,32 @@
39	40	void enable_layerscape_ns_access(void)
40	41	{
41	42	enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
	43	+}
	44	+
	45	+void set_pcie_ns_access(int pcie, u16 val)
	46	+{
	47	+ switch (pcie) {
	48	+#ifdef CONFIG_PCIE1
	49	+ case PCIE1:
	50	+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val);
	51	+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val);
	52	+ return;
	53	+#endif
	54	+#ifdef CONFIG_PCIE2
	55	+ case PCIE2:
	56	+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val);
	57	+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val);
	58	+ return;
	59	+#endif
	60	+#ifdef CONFIG_PCIE3
	61	+ case PCIE3:
	62	+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val);
	63	+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val);
	64	+ return;
	65	+#endif
	66	+ default:
	67	+ debug("The PCIE%d doesn't exist!\n", pcie);
	68	+ return;
	69	+ }
42	70	}
...	...	@@ -31,6 +31,7 @@
31	31
32	32	void enable_layerscape_ns_access(void);
33	33	void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val);
	34	+void set_pcie_ns_access(int pcie, u16 val);
34	35
35	36	#endif