Eric Lee / smarc-uboot

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Commit 66869f955417b89dbf6b7cbb72738b2205a26bf8

Authored by York Sun
1 parent f8cb101e1e
Exists in v2017.01-smarct4x and in 34 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

drivers/ddr/fsl: Update DDR driver for DDR4 

Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.

Signed-off-by: York Sun <yorksun@freescale.com>

Showing 5 changed files with 89 additions and 13 deletions Side-by-side Diff

drivers/ddr/fsl/ctrl_regs.c
Diff comments   View file @ 66869f9
... ... @@ -313,7 +313,10 @@
313 313 #ifdef CONFIG_SYS_FSL_DDR4
314 314 /* tXP=max(4nCK, 6ns) */
315 315 int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
316   - trwt_mclk = 2;
  316 + unsigned int data_rate = get_ddr_freq(ctrl_num);
  317 +
  318 + /* for faster clock, need more time for data setup */
  319 + trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
317 320 twrt_mclk = 1;
318 321 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
319 322 pre_pd_exit_mclk = act_pd_exit_mclk;
... ... @@ -338,7 +341,7 @@
338 341 */
339 342 txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
340 343  
341   - ip_rev = fsl_ddr_get_version();
  344 + ip_rev = fsl_ddr_get_version(ctrl_num);
342 345 if (ip_rev >= 0x40700) {
343 346 /*
344 347 * MRS_CYC = max(tMRD, tMOD)
... ... @@ -544,7 +547,7 @@
544 547 * we need set extend bit for it at
545 548 * TIMING_CFG_3[EXT_CASLAT]
546 549 */
547   - if (fsl_ddr_get_version() <= 0x40400)
  550 + if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
548 551 caslat_ctrl = 2 * cas_latency - 1;
549 552 else
550 553 caslat_ctrl = (cas_latency - 1) << 1;
551 554  
... ... @@ -1114,12 +1117,16 @@
1114 1117 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
1115 1118 unsigned short esdmode5; /* Extended SDRAM mode 5 */
1116 1119  
1117   - esdmode5 = 0x00000400; /* Data mask enabled */
  1120 + esdmode5 = 0x00000500; /* Data mask enabled */
1118 1121  
1119 1122 ddr->ddr_sdram_mode_9 = (0
1120 1123 | ((esdmode4 & 0xffff) << 16)
1121 1124 | ((esdmode5 & 0xffff) << 0)
1122 1125 );
  1126 +
  1127 + /* only mode_9 use 0x500, others use 0x400 */
  1128 + esdmode5 = 0x00000400; /* Data mask enabled */
  1129 +
1123 1130 debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1124 1131 if (unq_mrs_en) { /* unique mode registers are supported */
1125 1132 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
... ... @@ -2357,7 +2364,7 @@
2357 2364 set_ddr_cdr1(ddr, popts);
2358 2365 set_ddr_cdr2(ddr, popts);
2359 2366 set_ddr_sdram_cfg(ddr, popts, common_dimm);
2360   - ip_rev = fsl_ddr_get_version();
  2367 + ip_rev = fsl_ddr_get_version(ctrl_num);
2361 2368 if (ip_rev > 0x40400)
2362 2369 unq_mrs_en = 1;
2363 2370  
drivers/ddr/fsl/interactive.c
Diff comments   View file @ 66869f9
... ... @@ -205,6 +205,8 @@
205 205  
206 206 #define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
207 207 sizeof((dimm_params_t *)0)->x, 0}
  208 +#define DIMM_PARM_HEX(x) {#x, offsetof(dimm_params_t, x), \
  209 + sizeof((dimm_params_t *)0)->x, 1}
208 210  
209 211 static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
210 212 unsigned int ctrl_num,
... ... @@ -220,6 +222,7 @@
220 222 DIMM_PARM(primary_sdram_width),
221 223 DIMM_PARM(ec_sdram_width),
222 224 DIMM_PARM(registered_dimm),
  225 + DIMM_PARM(mirrored_dimm),
223 226 DIMM_PARM(device_width),
224 227  
225 228 DIMM_PARM(n_row_addr),
... ... @@ -274,7 +277,27 @@
274 277 DIMM_PARM(tdqsq_max_ps),
275 278 DIMM_PARM(tqhs_ps),
276 279 #endif
277   -
  280 +#ifdef CONFIG_SYS_FSL_DDR4
  281 + DIMM_PARM_HEX(dq_mapping[0]),
  282 + DIMM_PARM_HEX(dq_mapping[1]),
  283 + DIMM_PARM_HEX(dq_mapping[2]),
  284 + DIMM_PARM_HEX(dq_mapping[3]),
  285 + DIMM_PARM_HEX(dq_mapping[4]),
  286 + DIMM_PARM_HEX(dq_mapping[5]),
  287 + DIMM_PARM_HEX(dq_mapping[6]),
  288 + DIMM_PARM_HEX(dq_mapping[7]),
  289 + DIMM_PARM_HEX(dq_mapping[8]),
  290 + DIMM_PARM_HEX(dq_mapping[9]),
  291 + DIMM_PARM_HEX(dq_mapping[10]),
  292 + DIMM_PARM_HEX(dq_mapping[11]),
  293 + DIMM_PARM_HEX(dq_mapping[12]),
  294 + DIMM_PARM_HEX(dq_mapping[13]),
  295 + DIMM_PARM_HEX(dq_mapping[14]),
  296 + DIMM_PARM_HEX(dq_mapping[15]),
  297 + DIMM_PARM_HEX(dq_mapping[16]),
  298 + DIMM_PARM_HEX(dq_mapping[17]),
  299 + DIMM_PARM(dq_mapping_ors),
  300 +#endif
278 301 DIMM_PARM(rank_density),
279 302 DIMM_PARM(capacity),
280 303 DIMM_PARM(base_address),
... ... @@ -296,6 +319,7 @@
296 319 DIMM_PARM(primary_sdram_width),
297 320 DIMM_PARM(ec_sdram_width),
298 321 DIMM_PARM(registered_dimm),
  322 + DIMM_PARM(mirrored_dimm),
299 323 DIMM_PARM(device_width),
300 324  
301 325 DIMM_PARM(n_row_addr),
... ... @@ -314,6 +338,7 @@
314 338 DIMM_PARM(tckmax_ps),
315 339  
316 340 DIMM_PARM(caslat_x),
  341 + DIMM_PARM_HEX(caslat_x),
317 342 DIMM_PARM(taa_ps),
318 343 DIMM_PARM(caslat_x_minus_1),
319 344 DIMM_PARM(caslat_x_minus_2),
... ... @@ -322,6 +347,9 @@
322 347 DIMM_PARM(trcd_ps),
323 348 DIMM_PARM(trp_ps),
324 349 DIMM_PARM(tras_ps),
  350 +#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
  351 + DIMM_PARM(tfaw_ps),
  352 +#endif
325 353 #ifdef CONFIG_SYS_FSL_DDR4
326 354 DIMM_PARM(trfc1_ps),
327 355 DIMM_PARM(trfc2_ps),
... ... @@ -346,6 +374,27 @@
346 374 DIMM_PARM(tdh_ps),
347 375 DIMM_PARM(tdqsq_max_ps),
348 376 DIMM_PARM(tqhs_ps),
  377 +#endif
  378 +#ifdef CONFIG_SYS_FSL_DDR4
  379 + DIMM_PARM_HEX(dq_mapping[0]),
  380 + DIMM_PARM_HEX(dq_mapping[1]),
  381 + DIMM_PARM_HEX(dq_mapping[2]),
  382 + DIMM_PARM_HEX(dq_mapping[3]),
  383 + DIMM_PARM_HEX(dq_mapping[4]),
  384 + DIMM_PARM_HEX(dq_mapping[5]),
  385 + DIMM_PARM_HEX(dq_mapping[6]),
  386 + DIMM_PARM_HEX(dq_mapping[7]),
  387 + DIMM_PARM_HEX(dq_mapping[8]),
  388 + DIMM_PARM_HEX(dq_mapping[9]),
  389 + DIMM_PARM_HEX(dq_mapping[10]),
  390 + DIMM_PARM_HEX(dq_mapping[11]),
  391 + DIMM_PARM_HEX(dq_mapping[12]),
  392 + DIMM_PARM_HEX(dq_mapping[13]),
  393 + DIMM_PARM_HEX(dq_mapping[14]),
  394 + DIMM_PARM_HEX(dq_mapping[15]),
  395 + DIMM_PARM_HEX(dq_mapping[16]),
  396 + DIMM_PARM_HEX(dq_mapping[17]),
  397 + DIMM_PARM(dq_mapping_ors),
349 398 #endif
350 399 };
351 400 static const unsigned int n_opts = ARRAY_SIZE(options);
drivers/ddr/fsl/main.c
Diff comments   View file @ 66869f9
... ... @@ -453,7 +453,7 @@
453 453 retval = compute_dimm_parameters(
454 454 i, spd, pdimm, j);
455 455 #ifdef CONFIG_SYS_DDR_RAW_TIMING
456   - if (!i && !j && retval) {
  456 + if (!j && retval) {
457 457 printf("SPD error on controller %d! "
458 458 "Trying fallback to raw timing "
459 459 "calculation\n", i);
drivers/ddr/fsl/util.c
Diff comments   View file @ 66869f9
... ... @@ -23,12 +23,34 @@
23 23  
24 24 #define ULL_8FS 0xFFFFFFFFULL
25 25  
26   -u32 fsl_ddr_get_version(void)
  26 +u32 fsl_ddr_get_version(unsigned int ctrl_num)
27 27 {
28 28 struct ccsr_ddr __iomem *ddr;
29 29 u32 ver_major_minor_errata;
30 30  
31   - ddr = (void *)_DDR_ADDR;
  31 + switch (ctrl_num) {
  32 + case 0:
  33 + ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  34 + break;
  35 +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  36 + case 1:
  37 + ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  38 + break;
  39 +#endif
  40 +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  41 + case 2:
  42 + ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  43 + break;
  44 +#endif
  45 +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  46 + case 3:
  47 + ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  48 + break;
  49 +#endif
  50 + default:
  51 + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  52 + return 0;
  53 + }
32 54 ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
33 55 ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
34 56  
... ... @@ -212,7 +234,7 @@
212 234  
213 235 /* Calculate CAS latency based on timing cfg values */
214 236 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
215   - if (fsl_ddr_get_version() <= 0x40400)
  237 + if (fsl_ddr_get_version(0) <= 0x40400)
216 238 cas_lat += 1;
217 239 else
218 240 cas_lat += 2;
... ... @@ -34,9 +34,7 @@
34 34 #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
35 35 #endif
36 36  
37   -#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
38   -
39   -u32 fsl_ddr_get_version(void);
  37 +u32 fsl_ddr_get_version(unsigned int ctrl_num);
40 38  
41 39 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
42 40 /*