arm/dcc: use static support to allow to use it at anytime

the dcc can be used at the start of the cpu Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

arm/dcc: use static support to allow to use it at anytime
the dcc can be used at the start of the cpu Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Jean-Christophe PLAGNIOL-VILLARD · Wolfgang Denk
1 parent 7893aa1eb6
Showing 1 changed file with 42 additions and 114 deletions Side-by-side Diff
drivers/serial/arm_dcc.c
@@ -29,69 +29,50 @@
 #include <common.h>
 #include <devices.h>
  
-#define DCC_ARM9_RBIT	(1 << 0)
-#define DCC_ARM9_WBIT	(1 << 1)
-#define DCC_ARM11_RBIT	(1 << 30)
-#define DCC_ARM11_WBIT	(1 << 29)
-
-#define read_core_id(x)	do {						\
-		__asm__ ("mrc p15, 0, %0, c0, c0, 0\n" : "=r" (x));	\
-		x = (x >> 4) & 0xFFF;					\
-		} while (0);
-
+#if defined(CONFIG_CPU_V6)
 /*
- * ARM9
+ * ARMV6
  */
-#define write_arm9_dcc(x)	\
-		__asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
+#define DCC_RBIT	(1 << 30)
+#define DCC_WBIT	(1 << 29)
  
-#define read_arm9_dcc(x)	\
-		__asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
+#define write_dcc(x)	\
+		__asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
  
-#define status_arm9_dcc(x)	\
-		__asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
+#define read_dcc(x)	\
+		__asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
  
-#define can_read_arm9_dcc(x)	do {	\
-		status_arm9_dcc(x);	\
-		x &= DCC_ARM9_RBIT;	\
-		} while (0);
+#define status_dcc(x)	\
+		__asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
  
-#define can_write_arm9_dcc(x)	do {	\
-		status_arm9_dcc(x);	\
-		x &= DCC_ARM9_WBIT;	\
-		x = (x == 0);		\
-		} while (0);
+#else
+#define DCC_RBIT	(1 << 0)
+#define DCC_WBIT	(1 << 1)
  
-/*
- * ARM11
- */
-#define write_arm11_dcc(x)	\
-		__asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
+#define write_dcc(x)	\
+		__asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
  
-#define read_arm11_dcc(x)	\
-		__asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
+#define read_dcc(x)	\
+		__asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
  
-#define status_arm11_dcc(x)	\
-		__asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
+#define status_dcc(x)	\
+		__asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
  
-#define can_read_arm11_dcc(x)	do {	\
-		status_arm11_dcc(x);	\
-		x &= DCC_ARM11_RBIT;	\
+#endif
+
+#define can_read_dcc(x)	do {	\
+		status_dcc(x);	\
+		x &= DCC_RBIT;	\
 		} while (0);
  
-#define can_write_arm11_dcc(x)	do {	\
-		status_arm11_dcc(x);	\
-		x &= DCC_ARM11_WBIT;	\
-		x = (x == 0);		\
+#define can_write_dcc(x) do {	\
+		status_dcc(x);	\
+		x &= DCC_WBIT;	\
+		x = (x == 0);	\
 		} while (0);
  
 #define TIMEOUT_COUNT 0x4000000
  
-static enum {
-	arm9_and_earlier,
-	arm11_and_later
-} arm_type = arm9_and_earlier;
-
 #ifndef CONFIG_ARM_DCC_MULTI
 #define arm_dcc_init serial_init
 void serial_setbrg(void) {}
@@ -103,15 +84,6 @@
  
 int arm_dcc_init(void)
 {
-	register unsigned int id;
-
-	read_core_id(id);
-
-	if (id >= 0xb00)
-		arm_type = arm11_and_later;
-	else
-		arm_type = arm9_and_earlier;
-
 	return 0;
 }
  
  
@@ -120,23 +92,11 @@
 	int ch;
 	register unsigned int reg;
  
-	switch (arm_type) {
-	case arm11_and_later:
-		do {
-			can_read_arm11_dcc(reg);
-		} while (!reg);
-		read_arm11_dcc(ch);
-		break;
+	do {
+		can_read_dcc(reg);
+	} while (!reg);
+	read_dcc(ch);
  
-	case arm9_and_earlier:
-	default:
-		do {
-			can_read_arm9_dcc(reg);
-		} while (!reg);
-		read_arm9_dcc(ch);
-		break;
-	}
-
 	return ch;
 }
  
  
@@ -145,32 +105,15 @@
 	register unsigned int reg;
 	unsigned int timeout_count = TIMEOUT_COUNT;
  
-	switch (arm_type) {
-	case arm11_and_later:
-		while (--timeout_count) {
-			can_write_arm11_dcc(reg);
-			if (reg)
-				break;
-		}
-		if (timeout_count == 0)
-			return;
-		else
-			write_arm11_dcc(ch);
-		break;
-
-	case arm9_and_earlier:
-	default:
-		while (--timeout_count) {
-			can_write_arm9_dcc(reg);
-			if (reg)
-				break;
-		}
-		if (timeout_count == 0)
-			return;
-		else
-			write_arm9_dcc(ch);
-		break;
+	while (--timeout_count) {
+		can_write_dcc(reg);
+		if (reg)
+			break;
 	}
+	if (timeout_count == 0)
+		return;
+	else
+		write_dcc(ch);
 }
  
 void arm_dcc_puts(const char *s)
@@ -183,15 +126,7 @@
 {
 	register unsigned int reg;
  
-	switch (arm_type) {
-	case arm11_and_later:
-		can_read_arm11_dcc(reg);
-		break;
-	case arm9_and_earlier:
-	default:
-		can_read_arm9_dcc(reg);
-		break;
-	}
+	can_read_dcc(reg);
  
 	return reg;
 }
@@ -214,14 +149,7 @@
 	arm_dcc_dev.putc = arm_dcc_putc;	/* 'putc' function */
 	arm_dcc_dev.puts = arm_dcc_puts;	/* 'puts' function */
  
-	rc = device_register(&arm_dcc_dev);
-
-	if (rc == 0) {
-		arm_dcc_init();
-		return 1;
-	}
-
-	return 0;
+	return device_register(&arm_dcc_dev);
 }
 #endif
...	...	@@ -29,69 +29,50 @@
29	29	#include <common.h>
30	30	#include <devices.h>
31	31
32		-#define DCC_ARM9_RBIT (1 << 0)
33		-#define DCC_ARM9_WBIT (1 << 1)
34		-#define DCC_ARM11_RBIT (1 << 30)
35		-#define DCC_ARM11_WBIT (1 << 29)
36		-
37		-#define read_core_id(x) do { \
38		- __asm__ ("mrc p15, 0, %0, c0, c0, 0\n" : "=r" (x)); \
39		- x = (x >> 4) & 0xFFF; \
40		- } while (0);
41		-
	32	+#if defined(CONFIG_CPU_V6)
42	33	/*
43		- * ARM9
	34	+ * ARMV6
44	35	*/
45		-#define write_arm9_dcc(x) \
46		- __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
	36	+#define DCC_RBIT (1 << 30)
	37	+#define DCC_WBIT (1 << 29)
47	38
48		-#define read_arm9_dcc(x) \
49		- __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
	39	+#define write_dcc(x) \
	40	+ __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
50	41
51		-#define status_arm9_dcc(x) \
52		- __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
	42	+#define read_dcc(x) \
	43	+ __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
53	44
54		-#define can_read_arm9_dcc(x) do { \
55		- status_arm9_dcc(x); \
56		- x &= DCC_ARM9_RBIT; \
57		- } while (0);
	45	+#define status_dcc(x) \
	46	+ __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
58	47
59		-#define can_write_arm9_dcc(x) do { \
60		- status_arm9_dcc(x); \
61		- x &= DCC_ARM9_WBIT; \
62		- x = (x == 0); \
63		- } while (0);
	48	+#else
	49	+#define DCC_RBIT (1 << 0)
	50	+#define DCC_WBIT (1 << 1)
64	51
65		-/*
66		- * ARM11
67		- */
68		-#define write_arm11_dcc(x) \
69		- __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
	52	+#define write_dcc(x) \
	53	+ __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
70	54
71		-#define read_arm11_dcc(x) \
72		- __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
	55	+#define read_dcc(x) \
	56	+ __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
73	57
74		-#define status_arm11_dcc(x) \
75		- __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
	58	+#define status_dcc(x) \
	59	+ __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
76	60
77		-#define can_read_arm11_dcc(x) do { \
78		- status_arm11_dcc(x); \
79		- x &= DCC_ARM11_RBIT; \
	61	+#endif
	62	+
	63	+#define can_read_dcc(x) do { \
	64	+ status_dcc(x); \
	65	+ x &= DCC_RBIT; \
80	66	} while (0);
81	67
82		-#define can_write_arm11_dcc(x) do { \
83		- status_arm11_dcc(x); \
84		- x &= DCC_ARM11_WBIT; \
85		- x = (x == 0); \
	68	+#define can_write_dcc(x) do { \
	69	+ status_dcc(x); \
	70	+ x &= DCC_WBIT; \
	71	+ x = (x == 0); \
86	72	} while (0);
87	73
88	74	#define TIMEOUT_COUNT 0x4000000
89	75
90		-static enum {
91		- arm9_and_earlier,
92		- arm11_and_later
93		-} arm_type = arm9_and_earlier;
94		-
95	76	#ifndef CONFIG_ARM_DCC_MULTI
96	77	#define arm_dcc_init serial_init
97	78	void serial_setbrg(void) {}
...	...	@@ -103,15 +84,6 @@
103	84
104	85	int arm_dcc_init(void)
105	86	{
106		- register unsigned int id;
107		-
108		- read_core_id(id);
109		-
110		- if (id >= 0xb00)
111		- arm_type = arm11_and_later;
112		- else
113		- arm_type = arm9_and_earlier;
114		-
115	87	return 0;
116	88	}
117	89
118	90
...	...	@@ -120,23 +92,11 @@
120	92	int ch;
121	93	register unsigned int reg;
122	94
123		- switch (arm_type) {
124		- case arm11_and_later:
125		- do {
126		- can_read_arm11_dcc(reg);
127		- } while (!reg);
128		- read_arm11_dcc(ch);
129		- break;
	95	+ do {
	96	+ can_read_dcc(reg);
	97	+ } while (!reg);
	98	+ read_dcc(ch);
130	99
131		- case arm9_and_earlier:
132		- default:
133		- do {
134		- can_read_arm9_dcc(reg);
135		- } while (!reg);
136		- read_arm9_dcc(ch);
137		- break;
138		- }
139		-
140	100	return ch;
141	101	}
142	102
143	103
...	...	@@ -145,32 +105,15 @@
145	105	register unsigned int reg;
146	106	unsigned int timeout_count = TIMEOUT_COUNT;
147	107
148		- switch (arm_type) {
149		- case arm11_and_later:
150		- while (--timeout_count) {
151		- can_write_arm11_dcc(reg);
152		- if (reg)
153		- break;
154		- }
155		- if (timeout_count == 0)
156		- return;
157		- else
158		- write_arm11_dcc(ch);
159		- break;
160		-
161		- case arm9_and_earlier:
162		- default:
163		- while (--timeout_count) {
164		- can_write_arm9_dcc(reg);
165		- if (reg)
166		- break;
167		- }
168		- if (timeout_count == 0)
169		- return;
170		- else
171		- write_arm9_dcc(ch);
172		- break;
	108	+ while (--timeout_count) {
	109	+ can_write_dcc(reg);
	110	+ if (reg)
	111	+ break;
173	112	}
	113	+ if (timeout_count == 0)
	114	+ return;
	115	+ else
	116	+ write_dcc(ch);
174	117	}
175	118
176	119	void arm_dcc_puts(const char *s)
...	...	@@ -183,15 +126,7 @@
183	126	{
184	127	register unsigned int reg;
185	128
186		- switch (arm_type) {
187		- case arm11_and_later:
188		- can_read_arm11_dcc(reg);
189		- break;
190		- case arm9_and_earlier:
191		- default:
192		- can_read_arm9_dcc(reg);
193		- break;
194		- }
	129	+ can_read_dcc(reg);
195	130
196	131	return reg;
197	132	}
...	...	@@ -214,14 +149,7 @@
214	149	arm_dcc_dev.putc = arm_dcc_putc; /* 'putc' function */
215	150	arm_dcc_dev.puts = arm_dcc_puts; /* 'puts' function */
216	151
217		- rc = device_register(&arm_dcc_dev);
218		-
219		- if (rc == 0) {
220		- arm_dcc_init();
221		- return 1;
222		- }
223		-
224		- return 0;
	152	+ return device_register(&arm_dcc_dev);
225	153	}
226	154	#endif