Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 6721eb1a0df892eb44073d50dc52a87e758f8587

Authored by Ye Li
Committed by guoyin.chen
1 parent 58629b7f37
Exists in smarc-imx_v2015.04_4.1.15_1.0.0_ga and in 1 other branch imx_v2015.04_4.1.15_1.0.0_ga

MLK-12329-1 imx7d: Update DDR script for TO1.1 

On i.MX7D TO1.1, design team adds a mux cell at the CKE path to fix the suspend
 mode reset issue, but seems it add extra delay on CKE path, so CKE-CK timing violated.
When DDR enters self-refresh or retention for long time(> 15seconds per testing on some boards),
DDR data corruption occured, not able to decrease CKE delay, so we have to add extra
delay on all other signals to balance it.
DDR script needs to be fine-tuned according to this hardware change.

For DDR3, since the timing margin is not good, we have to decrease the DDR frequency from
533Mhz to 400Mhz.

Compass link:
http://compass.freescale.net/livelink/livelink?func=ll&objid=235010235&objAction=browse&sort=name

Test:
Overnight tests passed on all changed boards.

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 17 changed files with 998 additions and 24 deletions Side-by-side Diff

board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg
Diff comments   View file @ 6721eb1
1 1 /*
2   - * Copyright (C) 2015 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 *
... ... @@ -48,6 +48,9 @@
48 48 * value value to be stored in the register
49 49 */
50 50  
  51 +DATA 4 0x3038a080 0x15000000
  52 +DATA 4 0x30389880 0x01000000
  53 +
51 54 DATA 4 0x30340004 0x4F400005
52 55  
53 56 DATA 4 0x30391000 0x00000002
... ... @@ -83,7 +86,12 @@
83 86 DATA 4 0x30790000 0x17420f40
84 87 DATA 4 0x30790004 0x10210100
85 88 DATA 4 0x30790010 0x00060807
86   -DATA 4 0x3079009c 0x00000d6e
  89 +DATA 4 0x3079009c 0x00000dee
  90 +DATA 4 0x3079007c 0x18181818
  91 +DATA 4 0x30790080 0x18181818
  92 +DATA 4 0x30790084 0x40401818
  93 +DATA 4 0x30790088 0x00000040
  94 +DATA 4 0x3079006c 0x40404040
87 95 DATA 4 0x30790020 0x08080808
88 96 DATA 4 0x30790030 0x08080808
89 97 DATA 4 0x30790050 0x01000010
board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_0.cfg
Diff comments   View file @ 6721eb1
  1 +/*
  2 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * sd/onenand, nor
  22 + */
  23 +
  24 +#ifdef CONFIG_SYS_BOOT_EIMNOR
  25 +BOOT_FROM nor
  26 +#else
  27 +BOOT_FROM sd
  28 +#endif
  29 +
  30 +#ifdef CONFIG_USE_PLUGIN
  31 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  32 +PLUGIN board/freescale/mx7d_12x12_ddr3_arm2/plugin.bin 0x00910000
  33 +#else
  34 +
  35 +#ifdef CONFIG_SECURE_BOOT
  36 +CSF CONFIG_CSF_SIZE
  37 +#endif
  38 +
  39 +/*
  40 + * Device Configuration Data (DCD)
  41 + *
  42 + * Each entry must have the format:
  43 + * Addr-type Address Value
  44 + *
  45 + * where:
  46 + * Addr-type register length (1,2 or 4 bytes)
  47 + * Address absolute address of the register
  48 + * value value to be stored in the register
  49 + */
  50 +
  51 +DATA 4 0x30340004 0x4F400005
  52 +
  53 +DATA 4 0x30391000 0x00000002
  54 +DATA 4 0x307a0000 0x03040001
  55 +DATA 4 0x307a01a0 0x80400003
  56 +DATA 4 0x307a01a4 0x00100020
  57 +DATA 4 0x307a01a8 0x80100004
  58 +DATA 4 0x307a0064 0x0040005e
  59 +DATA 4 0x307a0490 0x00000001
  60 +DATA 4 0x307a00d0 0x00020001
  61 +DATA 4 0x307a00d4 0x00010000
  62 +DATA 4 0x307a00dc 0x09300004
  63 +DATA 4 0x307a00e0 0x04080000
  64 +DATA 4 0x307a00e4 0x00090004
  65 +DATA 4 0x307a00f4 0x0000033f
  66 +DATA 4 0x307a0100 0x0908120a
  67 +DATA 4 0x307a0104 0x0002020e
  68 +DATA 4 0x307a0108 0x03040407
  69 +DATA 4 0x307a010c 0x00002006
  70 +DATA 4 0x307a0110 0x04020204
  71 +DATA 4 0x307a0114 0x03030202
  72 +DATA 4 0x307a0120 0x03030803
  73 +DATA 4 0x307a0180 0x00800020
  74 +DATA 4 0x307a0190 0x02098204
  75 +DATA 4 0x307a0194 0x00030303
  76 +DATA 4 0x307a0200 0x00000016
  77 +DATA 4 0x307a0204 0x00171717
  78 +DATA 4 0x307a0214 0x04040404
  79 +DATA 4 0x307a0218 0x00040404
  80 +DATA 4 0x307a0240 0x06000601
  81 +DATA 4 0x307a0244 0x00001323
  82 +DATA 4 0x30391000 0x00000000
  83 +DATA 4 0x30790000 0x17420f40
  84 +DATA 4 0x30790004 0x10210100
  85 +DATA 4 0x30790010 0x00060807
  86 +DATA 4 0x3079009c 0x00000d6e
  87 +DATA 4 0x30790020 0x08080808
  88 +DATA 4 0x30790030 0x08080808
  89 +DATA 4 0x30790050 0x01000010
  90 +DATA 4 0x30790050 0x00000010
  91 +
  92 +DATA 4 0x307900c0 0x0e407304
  93 +DATA 4 0x307900c0 0x0e447304
  94 +DATA 4 0x307900c0 0x0e447306
  95 +
  96 +CHECK_BITS_SET 4 0x307900c4 0x1
  97 +
  98 +DATA 4 0x307900c0 0x0e447304
  99 +DATA 4 0x307900c0 0x0e407304
  100 +
  101 +DATA 4 0x30384130 0x00000000
  102 +DATA 4 0x30340020 0x00000178
  103 +DATA 4 0x30384130 0x00000002
  104 +DATA 4 0x30790018 0x0000000f
  105 +
  106 +CHECK_BITS_SET 4 0x307a0004 0x1
  107 +#endif
board/freescale/mx7d_12x12_ddr3_arm2/plugin.S
Diff comments   View file @ 6721eb1
1 1 /*
2   - * Copyright (C) 2015 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
6 6  
... ... @@ -7,7 +7,58 @@
7 7 #include <config.h>
8 8  
9 9 /* DDR script */
  10 +.macro imx7d_ddrphy_latency_setting
  11 + ldr r2, =ANATOP_BASE_ADDR
  12 + ldr r3, [r2, #0x800]
  13 + and r3, r3, #0xFF
  14 + cmp r3, #0x11
  15 + bne NO_DELAY
  16 +
  17 + /*TO 1.1*/
  18 + ldr r1, =0x00000dee
  19 + str r1, [r0, #0x9c]
  20 + ldr r1, =0x18181818
  21 + str r1, [r0, #0x7c]
  22 + ldr r1, =0x18181818
  23 + str r1, [r0, #0x80]
  24 + ldr r1, =0x40401818
  25 + str r1, [r0, #0x84]
  26 + ldr r1, =0x00000040
  27 + str r1, [r0, #0x88]
  28 + ldr r1, =0x40404040
  29 + str r1, [r0, #0x6c]
  30 + b TUNE_END
  31 +
  32 +NO_DELAY:
  33 + /*TO 1.0*/
  34 + ldr r1, =0x00000d6e
  35 + str r1, [r0, #0x9c]
  36 +
  37 +TUNE_END:
  38 +.endm
  39 +
  40 +.macro imx7d_ddr_freq_setting
  41 + ldr r2, =ANATOP_BASE_ADDR
  42 + ldr r3, [r2, #0x800]
  43 + and r3, r3, #0xFF
  44 + cmp r3, #0x11
  45 + bne FREQ_DEFAULT_533
  46 +
  47 + /* Change to 400Mhz for TO1.1 */
  48 + ldr r0, =CCM_BASE_ADDR
  49 + ldr r1, =0x15000000
  50 + ldr r2, =0xa080
  51 + str r1, [r0, r2]
  52 + ldr r1, =0x01000000
  53 + ldr r2, =0x9880
  54 + str r1, [r0, r2]
  55 +
  56 +FREQ_DEFAULT_533:
  57 +.endm
  58 +
10 59 .macro imx7d_12x12_ddr3_arm2_ddr_setting
  60 + imx7d_ddr_freq_setting
  61 +
11 62 /* Configure ocram_epdc */
12 63 ldr r0, =IOMUXC_GPR_BASE_ADDR
13 64 ldr r1, =0x4f400005
... ... @@ -90,8 +141,7 @@
90 141 str r1, [r0, #0x4]
91 142 ldr r1, =0x00060807
92 143 str r1, [r0, #0x10]
93   - ldr r1, =0x00000d6e
94   - str r1, [r0, #0x9c]
  144 + imx7d_ddrphy_latency_setting
95 145 ldr r1, =0x08080808
96 146 str r1, [r0, #0x20]
97 147 ldr r1, =0x08080808
board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg
Diff comments   View file @ 6721eb1
1 1 /*
2   - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 *
... ... @@ -92,6 +92,11 @@
92 92 DATA 4 0x30790004 0x10210100
93 93 DATA 4 0x30790008 0x00010000
94 94 DATA 4 0x30790010 0x0007080c
  95 +DATA 4 0x3079007c 0x1c1c1c1c
  96 +DATA 4 0x30790080 0x1c1c1c1c
  97 +DATA 4 0x30790084 0x30301c1c
  98 +DATA 4 0x30790088 0x00000030
  99 +DATA 4 0x3079006c 0x30303030
95 100 DATA 4 0x307900b0 0x1010007e
96 101  
97 102 DATA 4 0x3079001C 0x01010000
board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_0.cfg
Diff comments   View file @ 6721eb1
  1 +/*
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_SYS_BOOT_QSPI
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_SYS_BOOT_EIMNOR)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_USE_PLUGIN
  33 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  34 +PLUGIN board/freescale/mx7d_12x12_lpddr3_arm2/plugin.bin 0x00910000
  35 +#else
  36 +
  37 +#ifdef CONFIG_SECURE_BOOT
  38 +CSF CONFIG_CSF_SIZE
  39 +#endif
  40 +
  41 +/*
  42 + * Device Configuration Data (DCD)
  43 + *
  44 + * Each entry must have the format:
  45 + * Addr-type Address Value
  46 + *
  47 + * where:
  48 + * Addr-type register length (1,2 or 4 bytes)
  49 + * Address absolute address of the register
  50 + * value value to be stored in the register
  51 + */
  52 +
  53 +DATA 4 0x30340004 0x4F400005
  54 +
  55 +DATA 4 0x30391000 0x00000002
  56 +DATA 4 0x307a0000 0x03040008
  57 +DATA 4 0x307a0064 0x00200038
  58 +DATA 4 0x307a0490 0x00000001
  59 +DATA 4 0x307a00d0 0x00350001
  60 +DATA 4 0x307a00dc 0x00c3000a
  61 +DATA 4 0x307a00e0 0x00010000
  62 +DATA 4 0x307a00e4 0x00110006
  63 +DATA 4 0x307a00f4 0x0000033f
  64 +DATA 4 0x307a0100 0x0a0e110b
  65 +DATA 4 0x307a0104 0x00020211
  66 +DATA 4 0x307a0108 0x03060708
  67 +DATA 4 0x307a010c 0x00a0500c
  68 +DATA 4 0x307a0110 0x05020307
  69 +DATA 4 0x307a0114 0x02020404
  70 +DATA 4 0x307a0118 0x02020003
  71 +DATA 4 0x307a011c 0x00000202
  72 +DATA 4 0x307a0120 0x00000202
  73 +
  74 +DATA 4 0x307a0180 0x00600018
  75 +DATA 4 0x307a0184 0x00e00100
  76 +DATA 4 0x307a0190 0x02098205
  77 +DATA 4 0x307a0194 0x00060303
  78 +DATA 4 0x307a01a0 0x80400003
  79 +DATA 4 0x307a01a4 0x00100020
  80 +DATA 4 0x307a01a8 0x80100004
  81 +
  82 +DATA 4 0x307a0200 0x00000016
  83 +DATA 4 0x307a0204 0x00171717
  84 +DATA 4 0x307a0210 0x00000f00
  85 +DATA 4 0x307a0214 0x05050505
  86 +DATA 4 0x307a0218 0x0f0f0505
  87 +
  88 +DATA 4 0x307a0240 0x06000601
  89 +DATA 4 0x307a0244 0x00000000
  90 +DATA 4 0x30391000 0x00000000
  91 +DATA 4 0x30790000 0x17421e40
  92 +DATA 4 0x30790004 0x10210100
  93 +DATA 4 0x30790008 0x00010000
  94 +DATA 4 0x30790010 0x0007080c
  95 +DATA 4 0x307900b0 0x1010007e
  96 +
  97 +DATA 4 0x3079001C 0x01010000
  98 +DATA 4 0x3079009c 0x0db60d6e
  99 +
  100 +DATA 4 0x30790030 0x06060606
  101 +DATA 4 0x30790020 0x0a0a0a0a
  102 +DATA 4 0x30790050 0x01000008
  103 +DATA 4 0x30790050 0x00000008
  104 +DATA 4 0x30790018 0x0000000f
  105 +DATA 4 0x307900c0 0x1e487304
  106 +DATA 4 0x307900c0 0x1e487304
  107 +DATA 4 0x307900c0 0x1e487306
  108 +DATA 4 0x307900c0 0x1e4c7304
  109 +CHECK_BITS_SET 4 0x307900c4 0x1
  110 +
  111 +DATA 4 0x307900c0 0x1e487304
  112 +
  113 +DATA 4 0x30384130 0x00000000
  114 +DATA 4 0x30340020 0x00000178
  115 +DATA 4 0x30384130 0x00000002
  116 +
  117 +CHECK_BITS_SET 4 0x307a0004 0x1
  118 +#endif
board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S
Diff comments   View file @ 6721eb1
1 1 /*
2   - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
... ... @@ -7,6 +7,28 @@
7 7 #include <config.h>
8 8  
9 9 /* DDR script */
  10 +.macro imx7d_ddrphy_latency_setting
  11 + ldr r2, =ANATOP_BASE_ADDR
  12 + ldr r3, [r2, #0x800]
  13 + and r3, r3, #0xFF
  14 + cmp r3, #0x11
  15 + bne TUNE_END
  16 +
  17 + /*TO 1.1*/
  18 + ldr r1, =0x1c1c1c1c
  19 + str r1, [r0, #0x7c]
  20 + ldr r1, =0x1c1c1c1c
  21 + str r1, [r0, #0x80]
  22 + ldr r1, =0x30301c1c
  23 + str r1, [r0, #0x84]
  24 + ldr r1, =0x00000030
  25 + str r1, [r0, #0x88]
  26 + ldr r1, =0x30303030
  27 + str r1, [r0, #0x6c]
  28 +
  29 +TUNE_END:
  30 +.endm
  31 +
10 32 .macro imx7d_12x12_lpddr3_arm2_setting
11 33  
12 34 /* check whether it is a LPSR resume */
... ... @@ -204,7 +226,7 @@
204 226 str r7, [r2, r6]
205 227  
206 228 ldr r7, [r1, #0x800]
207   - and r7, r7, #0x11
  229 + and r7, r7, #0xFF
208 230 cmp r7, #0x10
209 231 beq 2f
210 232  
... ... @@ -242,6 +264,32 @@
242 264 ldr r7, =0x0007080C
243 265 str r7, [r4, r6]
244 266  
  267 + ldr r7, [r1, #0x800]
  268 + and r7, r7, #0xFF
  269 + cmp r7, #0x10
  270 + beq 4f
  271 +
  272 + ldr r6, =0x7c
  273 + ldr r7, =0x1c1c1c1c
  274 + str r7, [r4, r6]
  275 +
  276 + ldr r6, =0x80
  277 + ldr r7, =0x1c1c1c1c
  278 + str r7, [r4, r6]
  279 +
  280 + ldr r6, =0x84
  281 + ldr r7, =0x30301c1c
  282 + str r7, [r4, r6]
  283 +
  284 + ldr r6, =0x88
  285 + ldr r7, =0x00000030
  286 + str r7, [r4, r6]
  287 +
  288 + ldr r6, =0x6c
  289 + ldr r7, =0x30303030
  290 + str r7, [r4, r6]
  291 +
  292 +4:
245 293 ldr r6, =0x1c
246 294 ldr r7, =0x01010000
247 295 str r7, [r4, r6]
... ... @@ -439,6 +487,7 @@
439 487 str r1, [r0, #0x8]
440 488 ldr r1, =0x0007080c
441 489 str r1, [r0, #0x10]
  490 + imx7d_ddrphy_latency_setting
442 491 ldr r1, =0x1010007e
443 492 str r1, [r0, #0xb0]
444 493 ldr r1, =0x01010000
board/freescale/mx7d_19x19_ddr3_arm2/imximage.cfg
Diff comments   View file @ 6721eb1
1 1 /*
2   - * Copyright (C) 2014 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 *
... ... @@ -49,6 +49,8 @@
49 49 * Address absolute address of the register
50 50 * value value to be stored in the register
51 51 */
  52 +DATA 4 0x3038a080 0x15000000
  53 +DATA 4 0x30389880 0x01000000
52 54  
53 55 DATA 4 0x30340004 0x4F400005
54 56  
... ... @@ -85,7 +87,12 @@
85 87 DATA 4 0x30790000 0x17420f40
86 88 DATA 4 0x30790004 0x10210100
87 89 DATA 4 0x30790010 0x00060807
88   -DATA 4 0x3079009c 0x00000d6e
  90 +DATA 4 0x3079009c 0x00000dee
  91 +DATA 4 0x3079007c 0x18181818
  92 +DATA 4 0x30790080 0x18181818
  93 +DATA 4 0x30790084 0x40401818
  94 +DATA 4 0x30790088 0x00000040
  95 +DATA 4 0x3079006c 0x40404040
89 96 DATA 4 0x30790020 0x08080808
90 97 DATA 4 0x30790030 0x08080808
91 98 DATA 4 0x30790050 0x01000010
board/freescale/mx7d_19x19_ddr3_arm2/imximage_TO_1_0.cfg
Diff comments   View file @ 6721eb1
  1 +/*
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_SYS_BOOT_QSPI
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_SYS_BOOT_EIMNOR)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_USE_PLUGIN
  33 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  34 +PLUGIN board/freescale/mx7d_19x19_ddr3_arm2/plugin.bin 0x00910000
  35 +#else
  36 +
  37 +#ifdef CONFIG_SECURE_BOOT
  38 +CSF CONFIG_CSF_SIZE
  39 +#endif
  40 +
  41 +/*
  42 + * Device Configuration Data (DCD)
  43 + *
  44 + * Each entry must have the format:
  45 + * Addr-type Address Value
  46 + *
  47 + * where:
  48 + * Addr-type register length (1,2 or 4 bytes)
  49 + * Address absolute address of the register
  50 + * value value to be stored in the register
  51 + */
  52 +
  53 +DATA 4 0x30340004 0x4F400005
  54 +
  55 +DATA 4 0x30391000 0x00000002
  56 +DATA 4 0x307a0000 0x03040001
  57 +DATA 4 0x307a01a0 0x80400003
  58 +DATA 4 0x307a01a4 0x00100020
  59 +DATA 4 0x307a01a8 0x80100004
  60 +DATA 4 0x307a0064 0x0040005e
  61 +DATA 4 0x307a0490 0x00000001
  62 +DATA 4 0x307a00d0 0x00020001
  63 +DATA 4 0x307a00d4 0x00010000
  64 +DATA 4 0x307a00dc 0x09300004
  65 +DATA 4 0x307a00e0 0x04080000
  66 +DATA 4 0x307a00e4 0x00090004
  67 +DATA 4 0x307a00f4 0x0000033f
  68 +DATA 4 0x307a0100 0x0908120a
  69 +DATA 4 0x307a0104 0x0002020e
  70 +DATA 4 0x307a0108 0x03040407
  71 +DATA 4 0x307a010c 0x00002006
  72 +DATA 4 0x307a0110 0x04020204
  73 +DATA 4 0x307a0114 0x03030202
  74 +DATA 4 0x307a0120 0x03030803
  75 +DATA 4 0x307a0180 0x00800020
  76 +DATA 4 0x307a0190 0x02098204
  77 +DATA 4 0x307a0194 0x00030303
  78 +DATA 4 0x307a0200 0x00000016
  79 +DATA 4 0x307a0204 0x00171717
  80 +DATA 4 0x307a0214 0x04040404
  81 +DATA 4 0x307a0218 0x00040404
  82 +DATA 4 0x307a0240 0x06000601
  83 +DATA 4 0x307a0244 0x00001323
  84 +DATA 4 0x30391000 0x00000000
  85 +DATA 4 0x30790000 0x17420f40
  86 +DATA 4 0x30790004 0x10210100
  87 +DATA 4 0x30790010 0x00060807
  88 +DATA 4 0x3079009c 0x00000d6e
  89 +DATA 4 0x30790020 0x08080808
  90 +DATA 4 0x30790030 0x08080808
  91 +DATA 4 0x30790050 0x01000010
  92 +DATA 4 0x30790050 0x00000010
  93 +
  94 +DATA 4 0x307900c0 0x0e407304
  95 +DATA 4 0x307900c0 0x0e447304
  96 +DATA 4 0x307900c0 0x0e447306
  97 +
  98 +CHECK_BITS_SET 4 0x307900c4 0x1
  99 +
  100 +DATA 4 0x307900c0 0x0e447304
  101 +DATA 4 0x307900c0 0x0e407304
  102 +
  103 +
  104 +DATA 4 0x30384130 0x00000000
  105 +DATA 4 0x30340020 0x00000178
  106 +DATA 4 0x30384130 0x00000002
  107 +DATA 4 0x30790018 0x0000000f
  108 +
  109 +CHECK_BITS_SET 4 0x307a0004 0x1
  110 +#endif
board/freescale/mx7d_19x19_ddr3_arm2/plugin.S
Diff comments   View file @ 6721eb1
1 1 /*
2   - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
6 6  
... ... @@ -7,7 +7,58 @@
7 7 #include <config.h>
8 8  
9 9 /* DDR script */
  10 +.macro imx7d_ddrphy_latency_setting
  11 + ldr r2, =ANATOP_BASE_ADDR
  12 + ldr r3, [r2, #0x800]
  13 + and r3, r3, #0xFF
  14 + cmp r3, #0x11
  15 + bne NO_DELAY
  16 +
  17 + /*TO 1.1*/
  18 + ldr r1, =0x00000dee
  19 + str r1, [r0, #0x9c]
  20 + ldr r1, =0x18181818
  21 + str r1, [r0, #0x7c]
  22 + ldr r1, =0x18181818
  23 + str r1, [r0, #0x80]
  24 + ldr r1, =0x40401818
  25 + str r1, [r0, #0x84]
  26 + ldr r1, =0x00000040
  27 + str r1, [r0, #0x88]
  28 + ldr r1, =0x40404040
  29 + str r1, [r0, #0x6c]
  30 + b TUNE_END
  31 +
  32 +NO_DELAY:
  33 + /*TO 1.0*/
  34 + ldr r1, =0x00000d6e
  35 + str r1, [r0, #0x9c]
  36 +
  37 +TUNE_END:
  38 +.endm
  39 +
  40 +.macro imx7d_ddr_freq_setting
  41 + ldr r2, =ANATOP_BASE_ADDR
  42 + ldr r3, [r2, #0x800]
  43 + and r3, r3, #0xFF
  44 + cmp r3, #0x11
  45 + bne FREQ_DEFAULT_533
  46 +
  47 + /* Change to 400Mhz for TO1.1 */
  48 + ldr r0, =CCM_BASE_ADDR
  49 + ldr r1, =0x15000000
  50 + ldr r2, =0xa080
  51 + str r1, [r0, r2]
  52 + ldr r1, =0x01000000
  53 + ldr r2, =0x9880
  54 + str r1, [r0, r2]
  55 +
  56 +FREQ_DEFAULT_533:
  57 +.endm
  58 +
10 59 .macro imx7d_19x19_ddr3_arm2_ddr_setting
  60 + imx7d_ddr_freq_setting
  61 +
11 62 /* Configure ocram_epdc */
12 63 ldr r0, =IOMUXC_GPR_BASE_ADDR
13 64 ldr r1, =0x4f400005
... ... @@ -90,8 +141,7 @@
90 141 str r1, [r0, #0x4]
91 142 ldr r1, =0x00060807
92 143 str r1, [r0, #0x10]
93   - ldr r1, =0x00000d6e
94   - str r1, [r0, #0x9c]
  144 + imx7d_ddrphy_latency_setting
95 145 ldr r1, =0x08080808
96 146 str r1, [r0, #0x20]
97 147 ldr r1, =0x08080808
board/freescale/mx7d_19x19_lpddr3_arm2/imximage.cfg
Diff comments   View file @ 6721eb1
1 1 /*
2   - * Copyright (C) 2015 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 *
... ... @@ -92,6 +92,11 @@
92 92 DATA 4 0x30790004 0x10210100
93 93 DATA 4 0x30790008 0x00010000
94 94 DATA 4 0x30790010 0x0007080c
  95 +DATA 4 0x3079007c 0x1c1c1c1c
  96 +DATA 4 0x30790080 0x1c1c1c1c
  97 +DATA 4 0x30790084 0x30301c1c
  98 +DATA 4 0x30790088 0x00000030
  99 +DATA 4 0x3079006c 0x30303030
95 100 DATA 4 0x307900b0 0x1010007e
96 101  
97 102 DATA 4 0x3079001C 0x01010000
board/freescale/mx7d_19x19_lpddr3_arm2/imximage_TO_1_0.cfg
Diff comments   View file @ 6721eb1
  1 +/*
  2 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_SYS_BOOT_QSPI
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_SYS_BOOT_EIMNOR)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_USE_PLUGIN
  33 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  34 +PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000
  35 +#else
  36 +
  37 +#ifdef CONFIG_SECURE_BOOT
  38 +CSF CONFIG_CSF_SIZE
  39 +#endif
  40 +
  41 +/*
  42 + * Device Configuration Data (DCD)
  43 + *
  44 + * Each entry must have the format:
  45 + * Addr-type Address Value
  46 + *
  47 + * where:
  48 + * Addr-type register length (1,2 or 4 bytes)
  49 + * Address absolute address of the register
  50 + * value value to be stored in the register
  51 + */
  52 +
  53 +DATA 4 0x30340004 0x4F400005
  54 +
  55 +DATA 4 0x30391000 0x00000002
  56 +DATA 4 0x307a0000 0x03040008
  57 +DATA 4 0x307a0064 0x00200038
  58 +DATA 4 0x307a0490 0x00000001
  59 +DATA 4 0x307a00d0 0x00350001
  60 +DATA 4 0x307a00dc 0x00c3000a
  61 +DATA 4 0x307a00e0 0x00010000
  62 +DATA 4 0x307a00e4 0x00110006
  63 +DATA 4 0x307a00f4 0x0000033f
  64 +DATA 4 0x307a0100 0x0a0e110b
  65 +DATA 4 0x307a0104 0x00020211
  66 +DATA 4 0x307a0108 0x03060708
  67 +DATA 4 0x307a010c 0x00a0500c
  68 +DATA 4 0x307a0110 0x05020307
  69 +DATA 4 0x307a0114 0x02020404
  70 +DATA 4 0x307a0118 0x02020003
  71 +DATA 4 0x307a011c 0x00000202
  72 +DATA 4 0x307a0120 0x00000202
  73 +
  74 +DATA 4 0x307a0180 0x00600018
  75 +DATA 4 0x307a0184 0x00e00100
  76 +DATA 4 0x307a0190 0x02098205
  77 +DATA 4 0x307a0194 0x00060303
  78 +DATA 4 0x307a01a0 0x80400003
  79 +DATA 4 0x307a01a4 0x00100020
  80 +DATA 4 0x307a01a8 0x80100004
  81 +
  82 +DATA 4 0x307a0200 0x00000016
  83 +DATA 4 0x307a0204 0x00171717
  84 +DATA 4 0x307a0210 0x00000f00
  85 +DATA 4 0x307a0214 0x05050505
  86 +DATA 4 0x307a0218 0x0f0f0505
  87 +
  88 +DATA 4 0x307a0240 0x06000601
  89 +DATA 4 0x307a0244 0x00000000
  90 +DATA 4 0x30391000 0x00000000
  91 +DATA 4 0x30790000 0x17421e40
  92 +DATA 4 0x30790004 0x10210100
  93 +DATA 4 0x30790008 0x00010000
  94 +DATA 4 0x30790010 0x0007080c
  95 +DATA 4 0x307900b0 0x1010007e
  96 +
  97 +DATA 4 0x3079001C 0x01010000
  98 +DATA 4 0x3079009c 0x0db60d6e
  99 +
  100 +DATA 4 0x30790030 0x06060606
  101 +DATA 4 0x30790020 0x0a0a0a0a
  102 +DATA 4 0x30790050 0x01000008
  103 +DATA 4 0x30790050 0x00000008
  104 +DATA 4 0x30790018 0x0000000f
  105 +DATA 4 0x307900c0 0x1e487304
  106 +DATA 4 0x307900c0 0x1e487304
  107 +DATA 4 0x307900c0 0x1e487306
  108 +DATA 4 0x307900c0 0x1e4c7304
  109 +CHECK_BITS_SET 4 0x307900c4 0x1
  110 +
  111 +DATA 4 0x307900c0 0x1e487304
  112 +
  113 +DATA 4 0x30384130 0x00000000
  114 +DATA 4 0x30340020 0x00000178
  115 +DATA 4 0x30384130 0x00000002
  116 +
  117 +CHECK_BITS_SET 4 0x307a0004 0x1
  118 +#endif
board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2.cfg
Diff comments   View file @ 6721eb1
1 1 /*
2   - * Copyright (C) 2015 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 *
... ... @@ -96,7 +96,12 @@
96 96 DATA 4 0x307900b0 0x1010007e
97 97  
98 98 DATA 4 0x3079001C 0x01010000
99   -DATA 4 0x3079009C 0x00000d6e
  99 +DATA 4 0x3079009C 0x00000dee
  100 +DATA 4 0x3079007c 0x08080808
  101 +DATA 4 0x30790080 0x08080808
  102 +DATA 4 0x30790084 0x0a0a0808
  103 +DATA 4 0x30790088 0x0000000a
  104 +DATA 4 0x3079006c 0x0a0a0a0a
100 105 DATA 4 0x30790018 0x0000000f
101 106  
102 107 DATA 4 0x30790030 0x06060606
board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2_TO_1_0.cfg
Diff comments   View file @ 6721eb1
  1 +/*
  2 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_SYS_BOOT_QSPI
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_SYS_BOOT_EIMNOR)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_USE_PLUGIN
  33 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  34 +PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000
  35 +#else
  36 +
  37 +#ifdef CONFIG_SECURE_BOOT
  38 +CSF CONFIG_CSF_SIZE
  39 +#endif
  40 +
  41 +/*
  42 + * Device Configuration Data (DCD)
  43 + *
  44 + * Each entry must have the format:
  45 + * Addr-type Address Value
  46 + *
  47 + * where:
  48 + * Addr-type register length (1,2 or 4 bytes)
  49 + * Address absolute address of the register
  50 + * value value to be stored in the register
  51 + */
  52 +
  53 +DATA 4 0x30340004 0x4F400005
  54 +
  55 +DATA 4 0x30391000 0x00000002
  56 +DATA 4 0x307a0000 0x03020004
  57 +DATA 4 0x307a01a0 0x80400003
  58 +DATA 4 0x307a01a4 0x00100020
  59 +DATA 4 0x307a01a8 0x80100004
  60 +DATA 4 0x307a0064 0x00200023
  61 +DATA 4 0x307a0490 0x00000001
  62 +DATA 4 0x307a00d0 0x00350001
  63 +DATA 4 0x307a00d8 0x00001105
  64 +DATA 4 0x307a00dc 0x00c20006
  65 +DATA 4 0x307a00e0 0x00020000
  66 +DATA 4 0x307a00e4 0x00110006
  67 +DATA 4 0x307a00f4 0x0000033f
  68 +DATA 4 0x307a0100 0x080e110b
  69 +DATA 4 0x307a0104 0x00020211
  70 +DATA 4 0x307a0108 0x02040706
  71 +DATA 4 0x307a010c 0x00504000
  72 +DATA 4 0x307a0110 0x05010307
  73 +DATA 4 0x307a0114 0x02020404
  74 +DATA 4 0x307a0118 0x02020003
  75 +DATA 4 0x307a011c 0x00000202
  76 +DATA 4 0x307a0120 0x00000202
  77 +
  78 +DATA 4 0x307a0180 0x00600018
  79 +DATA 4 0x307a0184 0x00e00100
  80 +DATA 4 0x307a0190 0x02098203
  81 +DATA 4 0x307a0194 0x00060303
  82 +
  83 +DATA 4 0x307a0200 0x00000015
  84 +DATA 4 0x307a0204 0x00161616
  85 +DATA 4 0x307a0210 0x00000f0f
  86 +DATA 4 0x307a0214 0x04040404
  87 +DATA 4 0x307a0218 0x0f0f0404
  88 +
  89 +DATA 4 0x307a0240 0x06000600
  90 +DATA 4 0x307a0244 0x00000000
  91 +DATA 4 0x30391000 0x00000000
  92 +DATA 4 0x30790000 0x17421640
  93 +DATA 4 0x30790004 0x10210100
  94 +DATA 4 0x30790008 0x00010000
  95 +DATA 4 0x30790010 0x00050408
  96 +DATA 4 0x307900b0 0x1010007e
  97 +
  98 +DATA 4 0x3079001C 0x01010000
  99 +DATA 4 0x3079009C 0x00000d6e
  100 +DATA 4 0x30790018 0x0000000f
  101 +
  102 +DATA 4 0x30790030 0x06060606
  103 +DATA 4 0x30790020 0x0a0a0a0a
  104 +DATA 4 0x30790050 0x01000008
  105 +DATA 4 0x30790050 0x00000008
  106 +DATA 4 0x307900c0 0x0e487304
  107 +DATA 4 0x307900c0 0x0e4c7304
  108 +DATA 4 0x307900c0 0x0e4c7306
  109 +CHECK_BITS_SET 4 0x307900c4 0x1
  110 +
  111 +DATA 4 0x307900c0 0x0e4c7304
  112 +DATA 4 0x307900c0 0x0e487304
  113 +
  114 +DATA 4 0x30384130 0x00000000
  115 +DATA 4 0x30340020 0x000001f8
  116 +DATA 4 0x30384130 0x00000002
  117 +
  118 +CHECK_BITS_SET 4 0x307a0004 0x1
  119 +#endif
board/freescale/mx7d_19x19_lpddr3_arm2/plugin.S
Diff comments   View file @ 6721eb1
1 1 /*
2   - * Copyright (C) 2015 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
... ... @@ -7,6 +7,58 @@
7 7 #include <config.h>
8 8  
9 9 /* DDR script */
  10 +.macro imx7d_ddrphy_lpddr3_latency_setting
  11 + ldr r2, =ANATOP_BASE_ADDR
  12 + ldr r3, [r2, #0x800]
  13 + and r3, r3, #0xFF
  14 + cmp r3, #0x11
  15 + bne TUNE_END
  16 +
  17 + /*TO 1.1*/
  18 + ldr r1, =0x1c1c1c1c
  19 + str r1, [r0, #0x7c]
  20 + ldr r1, =0x1c1c1c1c
  21 + str r1, [r0, #0x80]
  22 + ldr r1, =0x30301c1c
  23 + str r1, [r0, #0x84]
  24 + ldr r1, =0x00000030
  25 + str r1, [r0, #0x88]
  26 + ldr r1, =0x30303030
  27 + str r1, [r0, #0x6c]
  28 +
  29 +TUNE_END:
  30 +.endm
  31 +
  32 +.macro imx7d_ddrphy_lpddr2_latency_setting
  33 + ldr r2, =ANATOP_BASE_ADDR
  34 + ldr r3, [r2, #0x800]
  35 + and r3, r3, #0xFF
  36 + cmp r3, #0x11
  37 + bne NO_DELAY
  38 +
  39 + /*TO 1.1*/
  40 + ldr r1, =0x00000dee
  41 + str r1, [r0, #0x9c]
  42 + ldr r1, =0x08080808
  43 + str r1, [r0, #0x7c]
  44 + ldr r1, =0x08080808
  45 + str r1, [r0, #0x80]
  46 + ldr r1, =0x0a0a0808
  47 + str r1, [r0, #0x84]
  48 + ldr r1, =0x0000000a
  49 + str r1, [r0, #0x88]
  50 + ldr r1, =0x0a0a0a0a
  51 + str r1, [r0, #0x6c]
  52 + b TUNE_END
  53 +
  54 +NO_DELAY:
  55 + /*TO 1.0*/
  56 + ldr r1, =0x00000d6e
  57 + str r1, [r0, #0x9c]
  58 +
  59 +TUNE_END:
  60 +.endm
  61 +
10 62 .macro imx7d_19x19_lpddr3_arm2_setting
11 63 /* Configure ocram_epdc */
12 64 ldr r0, =IOMUXC_GPR_BASE_ADDR
... ... @@ -98,6 +150,7 @@
98 150 str r1, [r0, #0x8]
99 151 ldr r1, =0x0007080c
100 152 str r1, [r0, #0x10]
  153 + imx7d_ddrphy_lpddr3_latency_setting
101 154 ldr r1, =0x1010007e
102 155 str r1, [r0, #0xb0]
103 156 ldr r1, =0x01010000
... ... @@ -249,8 +302,7 @@
249 302 str r1, [r0, #0xb0]
250 303 ldr r1, =0x01010000
251 304 str r1, [r0, #0x1c]
252   - ldr r1, =0x00000d6e
253   - str r1, [r0, #0x9c]
  305 + imx7d_ddrphy_lpddr2_latency_setting
254 306 ldr r1, =0x0000000f
255 307 str r1, [r0, #0x18]
256 308  
board/freescale/mx7dsabresd/imximage.cfg
Diff comments   View file @ 6721eb1
1 1 /*
2   - * Copyright (C) 2014 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 *
... ... @@ -50,6 +50,9 @@
50 50 * value value to be stored in the register
51 51 */
52 52  
  53 +DATA 4 0x3038a080 0x15000000
  54 +DATA 4 0x30389880 0x01000000
  55 +
53 56 DATA 4 0x30340004 0x4F400005
54 57  
55 58 DATA 4 0x30391000 0x00000002
... ... @@ -87,7 +90,12 @@
87 90 DATA 4 0x30790004 0x10210100
88 91 DATA 4 0x30790010 0x00060807
89 92 DATA 4 0x307900b0 0x1010007e
90   -DATA 4 0x3079009c 0x00000d6e
  93 +DATA 4 0x3079009c 0x00000dee
  94 +DATA 4 0x3079007c 0x18181818
  95 +DATA 4 0x30790080 0x18181818
  96 +DATA 4 0x30790084 0x40401818
  97 +DATA 4 0x30790088 0x00000040
  98 +DATA 4 0x3079006c 0x40404040
91 99 DATA 4 0x30790020 0x08080808
92 100 DATA 4 0x30790030 0x08080808
93 101 DATA 4 0x30790050 0x01000010
board/freescale/mx7dsabresd/imximage_TO_1_0.cfg
Diff comments   View file @ 6721eb1
  1 +/*
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_SYS_BOOT_QSPI
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_SYS_BOOT_EIMNOR)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_USE_PLUGIN
  33 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  34 +PLUGIN board/freescale/mx7dsabresd/plugin.bin 0x00910000
  35 +#else
  36 +
  37 +#ifdef CONFIG_SECURE_BOOT
  38 +CSF CONFIG_CSF_SIZE
  39 +#endif
  40 +
  41 +/*
  42 + * Device Configuration Data (DCD)
  43 + *
  44 + * Each entry must have the format:
  45 + * Addr-type Address Value
  46 + *
  47 + * where:
  48 + * Addr-type register length (1,2 or 4 bytes)
  49 + * Address absolute address of the register
  50 + * value value to be stored in the register
  51 + */
  52 +
  53 +DATA 4 0x30340004 0x4F400005
  54 +
  55 +DATA 4 0x30391000 0x00000002
  56 +DATA 4 0x307a0000 0x01040001
  57 +DATA 4 0x307a01a0 0x80400003
  58 +DATA 4 0x307a01a4 0x00100020
  59 +DATA 4 0x307a01a8 0x80100004
  60 +DATA 4 0x307a0064 0x00400046
  61 +DATA 4 0x307a0490 0x00000001
  62 +DATA 4 0x307a00d0 0x00020083
  63 +DATA 4 0x307a00d4 0x00690000
  64 +DATA 4 0x307a00dc 0x09300004
  65 +DATA 4 0x307a00e0 0x04080000
  66 +DATA 4 0x307a00e4 0x00100004
  67 +DATA 4 0x307a00f4 0x0000033f
  68 +DATA 4 0x307a0100 0x09081109
  69 +DATA 4 0x307a0104 0x0007020d
  70 +DATA 4 0x307a0108 0x03040407
  71 +DATA 4 0x307a010c 0x00002006
  72 +DATA 4 0x307a0110 0x04020205
  73 +DATA 4 0x307a0114 0x03030202
  74 +DATA 4 0x307a0120 0x00000803
  75 +DATA 4 0x307a0180 0x00800020
  76 +DATA 4 0x307a0184 0x02000100
  77 +DATA 4 0x307a0190 0x02098204
  78 +DATA 4 0x307a0194 0x00030303
  79 +DATA 4 0x307a0200 0x00000016
  80 +DATA 4 0x307a0204 0x00171717
  81 +DATA 4 0x307a0214 0x04040404
  82 +DATA 4 0x307a0218 0x0f040404
  83 +DATA 4 0x307a0240 0x06000604
  84 +DATA 4 0x307a0244 0x00000001
  85 +DATA 4 0x30391000 0x00000000
  86 +DATA 4 0x30790000 0x17420f40
  87 +DATA 4 0x30790004 0x10210100
  88 +DATA 4 0x30790010 0x00060807
  89 +DATA 4 0x307900b0 0x1010007e
  90 +DATA 4 0x3079009c 0x00000d6e
  91 +DATA 4 0x30790020 0x08080808
  92 +DATA 4 0x30790030 0x08080808
  93 +DATA 4 0x30790050 0x01000010
  94 +DATA 4 0x30790050 0x00000010
  95 +
  96 +DATA 4 0x307900c0 0x0e407304
  97 +DATA 4 0x307900c0 0x0e447304
  98 +DATA 4 0x307900c0 0x0e447306
  99 +
  100 +CHECK_BITS_SET 4 0x307900c4 0x1
  101 +
  102 +DATA 4 0x307900c0 0x0e447304
  103 +DATA 4 0x307900c0 0x0e407304
  104 +
  105 +
  106 +DATA 4 0x30384130 0x00000000
  107 +DATA 4 0x30340020 0x00000178
  108 +DATA 4 0x30384130 0x00000002
  109 +DATA 4 0x30790018 0x0000000f
  110 +
  111 +CHECK_BITS_SET 4 0x307a0004 0x1
  112 +
  113 +#endif
board/freescale/mx7dsabresd/plugin.S
Diff comments   View file @ 6721eb1
1 1 /*
2   - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
6 6  
... ... @@ -7,7 +7,58 @@
7 7 #include <config.h>
8 8  
9 9 /* DDR script */
  10 +.macro imx7d_ddrphy_latency_setting
  11 + ldr r2, =ANATOP_BASE_ADDR
  12 + ldr r3, [r2, #0x800]
  13 + and r3, r3, #0xFF
  14 + cmp r3, #0x11
  15 + bne NO_DELAY
  16 +
  17 + /*TO 1.1*/
  18 + ldr r1, =0x00000dee
  19 + str r1, [r0, #0x9c]
  20 + ldr r1, =0x18181818
  21 + str r1, [r0, #0x7c]
  22 + ldr r1, =0x18181818
  23 + str r1, [r0, #0x80]
  24 + ldr r1, =0x40401818
  25 + str r1, [r0, #0x84]
  26 + ldr r1, =0x00000040
  27 + str r1, [r0, #0x88]
  28 + ldr r1, =0x40404040
  29 + str r1, [r0, #0x6c]
  30 + b TUNE_END
  31 +
  32 +NO_DELAY:
  33 + /*TO 1.0*/
  34 + ldr r1, =0x00000d6e
  35 + str r1, [r0, #0x9c]
  36 +
  37 +TUNE_END:
  38 +.endm
  39 +
  40 +.macro imx7d_ddr_freq_setting
  41 + ldr r2, =ANATOP_BASE_ADDR
  42 + ldr r3, [r2, #0x800]
  43 + and r3, r3, #0xFF
  44 + cmp r3, #0x11
  45 + bne FREQ_DEFAULT_533
  46 +
  47 + /* Change to 400Mhz for TO1.1 */
  48 + ldr r0, =CCM_BASE_ADDR
  49 + ldr r1, =0x15000000
  50 + ldr r2, =0xa080
  51 + str r1, [r0, r2]
  52 + ldr r1, =0x01000000
  53 + ldr r2, =0x9880
  54 + str r1, [r0, r2]
  55 +
  56 +FREQ_DEFAULT_533:
  57 +.endm
  58 +
10 59 .macro imx7d_sabresd_ddr_setting
  60 + imx7d_ddr_freq_setting
  61 +
11 62 /* Configure ocram_epdc */
12 63 ldr r0, =IOMUXC_GPR_BASE_ADDR
13 64 ldr r1, =0x4f400005
... ... @@ -94,8 +145,7 @@
94 145 str r1, [r0, #0x10]
95 146 ldr r1, =0x1010007e
96 147 str r1, [r0, #0xb0]
97   - ldr r1, =0x00000d6e
98   - str r1, [r0, #0x9c]
  148 + imx7d_ddrphy_latency_setting
99 149 ldr r1, =0x08080808
100 150 str r1, [r0, #0x20]
101 151 ldr r1, =0x08080808