Eric Lee / smarc-uboot

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Commit 6785c7c84ad6803587b247f363fe977d3e0775fb

Authored by Thomas Petazzoni
Committed by Albert ARIBAUD
1 parent 0cb77bfa7a
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

sbc35_a9g20: update board to the new AT91 organization 

Cc: Albin Tonnerre <tonnerrealbin@gmail.com>
Cc: Gregory Hermant <gregory.hermant@calao-systems.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>

Removed SBC35 from MAKEALL

Showing 5 changed files with 88 additions and 97 deletions Side-by-side Diff

... ... @@ -446,7 +446,6 @@
446 446 LIST_at91="$(boards_by_soc at91)\
447 447 at91sam9m10g45ek \
448 448 pm9g45 \
449   - SBC35_A9G20 \
450 449 TNY_A9260 \
451 450 TNY_A9G20 \
452 451 "
... ... @@ -827,13 +827,6 @@
827 827 @mkdir -p $(obj)include
828 828 @$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
829 829  
830   -SBC35_A9G20_NANDFLASH_config \
831   -SBC35_A9G20_EEPROM_config \
832   -SBC35_A9G20_config : unconfig
833   - @mkdir -p $(obj)include
834   - @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
835   - @$(MKCONFIG) -n $@ -a sbc35_a9g20 arm arm926ejs sbc35_a9g20 calao at91
836   -
837 830 TNY_A9G20_NANDFLASH_config \
838 831 TNY_A9G20_EEPROM_config \
839 832 TNY_A9G20_config \
board/calao/sbc35_a9g20/sbc35_a9g20.c
Diff comments   View file @ 6785c7c
... ... @@ -26,15 +26,14 @@
26 26 */
27 27  
28 28 #include <common.h>
29   -#include <asm/arch/at91sam9260.h>
  29 +#include <asm/io.h>
30 30 #include <asm/arch/at91sam9260_matrix.h>
31 31 #include <asm/arch/at91sam9_smc.h>
32 32 #include <asm/arch/at91_common.h>
33 33 #include <asm/arch/at91_pmc.h>
34 34 #include <asm/arch/at91_rstc.h>
35 35 #include <asm/arch/gpio.h>
36   -#include <asm/arch/io.h>
37   -#include <asm/arch/hardware.h>
  36 +
38 37 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
39 38 #include <net.h>
40 39 #endif
41 40  
42 41  
43 42  
44 43  
45 44  
46 45  
... ... @@ -50,33 +49,36 @@
50 49 #ifdef CONFIG_CMD_NAND
51 50 static void sbc35_a9g20_nand_hw_init(void)
52 51 {
  52 + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  53 + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  54 + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
53 55 unsigned long csa;
54 56  
55 57 /* Enable CS3 */
56   - csa = at91_sys_read(AT91_MATRIX_EBICSA);
57   - at91_sys_write(AT91_MATRIX_EBICSA,
58   - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
  58 + csa = readl(&matrix->ebicsa);
  59 + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  60 + writel(csa, &matrix->ebicsa);
59 61  
60 62 /* Configure SMC CS3 for NAND/SmartMedia */
61   - at91_sys_write(AT91_SMC_SETUP(3),
62   - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
63   - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
64   - at91_sys_write(AT91_SMC_PULSE(3),
65   - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
66   - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
67   - at91_sys_write(AT91_SMC_CYCLE(3),
68   - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
69   - at91_sys_write(AT91_SMC_MODE(3),
70   - AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
71   - AT91_SMC_EXNWMODE_DISABLE |
  63 + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  64 + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  65 + &smc->cs[3].setup);
  66 + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  67 + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  68 + &smc->cs[3].pulse);
  69 + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  70 + &smc->cs[3].cycle);
  71 + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  72 + AT91_SMC_MODE_EXNW_DISABLE |
72 73 #ifdef CONFIG_SYS_NAND_DBW_16
73   - AT91_SMC_DBW_16 |
  74 + AT91_SMC_MODE_DBW_16 |
74 75 #else /* CONFIG_SYS_NAND_DBW_8 */
75   - AT91_SMC_DBW_8 |
  76 + AT91_SMC_MODE_DBW_8 |
76 77 #endif
77   - AT91_SMC_TDF_(2));
  78 + AT91_SMC_MODE_TDF_CYCLE(2),
  79 + &smc->cs[3].mode);
78 80  
79   - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
  81 + writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
80 82  
81 83 /* Configure RDY/BSY */
82 84 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
83 85  
... ... @@ -89,10 +91,13 @@
89 91 #ifdef CONFIG_MACB
90 92 static void sbc35_a9g20_macb_hw_init(void)
91 93 {
92   - unsigned long rstc;
  94 + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  95 + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  96 + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
  97 + unsigned long erstl;
93 98  
94   - /* Enable clock */
95   - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
  99 + /* Enable EMAC clock */
  100 + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
96 101  
97 102 /*
98 103 * Disable pull-up on:
99 104  
100 105  
101 106  
102 107  
103 108  
... ... @@ -111,24 +116,23 @@
111 116 pin_to_mask(AT91_PIN_PA25) |
112 117 pin_to_mask(AT91_PIN_PA26) |
113 118 pin_to_mask(AT91_PIN_PA28),
114   - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
  119 + &pioa->pudr);
115 120  
116   - rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
  121 + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
117 122  
118 123 /* Need to reset PHY -> 500ms reset */
119   - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
120   - (AT91_RSTC_ERSTL & (0x0D << 8)) |
121   - AT91_RSTC_URSTEN);
  124 + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
  125 + AT91_RSTC_MR_URSTEN, &rstc->mr);
122 126  
123   - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
  127 + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
124 128  
125 129 /* Wait for end hardware reset */
126   - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
  130 + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
  131 + ;
127 132  
128 133 /* Restore NRST value */
129   - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
130   - (rstc) |
131   - AT91_RSTC_URSTEN);
  134 + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
  135 + &rstc->mr);
132 136  
133 137 /* Re-enable pull-up */
134 138 writel(pin_to_mask(AT91_PIN_PA14) |
... ... @@ -137,7 +141,7 @@
137 141 pin_to_mask(AT91_PIN_PA25) |
138 142 pin_to_mask(AT91_PIN_PA26) |
139 143 pin_to_mask(AT91_PIN_PA28),
140   - pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
  144 + &pioa->puer);
141 145  
142 146 at91_macb_hw_init();
143 147 }
144 148  
... ... @@ -150,9 +154,9 @@
150 154  
151 155 gd->bd->bi_arch_number = MACH_TYPE_SBC35_A9G20;
152 156 /* adress of boot parameters */
153   - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  157 + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
154 158  
155   - at91_serial_hw_init();
  159 + at91_seriald_hw_init();
156 160 sbc35_a9g20_nand_hw_init();
157 161 #ifdef CONFIG_ATMEL_SPI
158 162 at91_spi0_hw_init(1 << 4 | 1 << 5);
... ... @@ -166,11 +170,9 @@
166 170  
167 171 int dram_init(void)
168 172 {
169   - gd->bd->bi_dram[0].start = PHYS_SDRAM;
170   - if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
171   - return -1;
172   -
173   - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
  173 + gd->ram_size = get_ram_size(
  174 + (void *)CONFIG_SYS_SDRAM_BASE,
  175 + CONFIG_SYS_SDRAM_SIZE);
174 176 return 0;
175 177 }
176 178  
... ... @@ -184,7 +186,7 @@
184 186 {
185 187 int rc = 0;
186 188 #ifdef CONFIG_MACB
187   - rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
  189 + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
188 190 #endif
189 191 return rc;
190 192 }
... ... @@ -102,6 +102,8 @@
102 102 at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1
103 103 snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260
104 104 snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20
  105 +sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH
  106 +sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM
105 107 cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260
106 108 cpu9260_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,NANDBOOT
107 109 cpu9260_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M
include/configs/sbc35_a9g20.h
Diff comments   View file @ 6785c7c
... ... @@ -26,54 +26,49 @@
26 26 #ifndef __CONFIG_H
27 27 #define __CONFIG_H
28 28  
29   -#define CONFIG_AT91_LEGACY
  29 +/* SoC type is defined in boards.cfg */
  30 +#include <asm/hardware.h>
  31 +#include <asm/sizes.h>
30 32  
31   -#if defined(CONFIG_SBC35_A9G20_NANDFLASH) || defined(CONFIG_SBC35_A9G20_EEPROM)
32   -#define CONFIG_SBC35_A9G20
33   -#endif
34   -
35   -#define CONFIG_AT91SAM9G20
36   -
37   -#if defined(CONFIG_SBC35_A9G20_NANDFLASH)
  33 +#if defined(CONFIG_SYS_USE_NANDFLASH)
38 34 #define CONFIG_ENV_IS_IN_NAND
39 35 #else
40 36 #define CONFIG_ENV_IS_IN_EEPROM
41 37 #endif
42 38  
43 39 /* ARM asynchronous clock */
  40 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
44 41 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */
45   -#define CONFIG_SYS_HZ 1000
  42 +#define CONFIG_SYS_HZ 1000
46 43  
47   -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
48   -
49 44 #define CONFIG_ARCH_CPU_INIT
50 45 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
51 46  
52   -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
53   -#define CONFIG_SETUP_MEMORY_TAGS 1
54   -#define CONFIG_INITRD_TAG 1
55   -
  47 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  48 +#define CONFIG_SETUP_MEMORY_TAGS
  49 +#define CONFIG_INITRD_TAG
56 50 #define CONFIG_SKIP_LOWLEVEL_INIT
57 51  
58   -/*
59   - * Hardware drivers
60   - */
61   -#define CONFIG_AT91_GPIO 1
  52 +/* GPIO */
  53 +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
  54 +#define CONFIG_AT91_GPIO
  55 +
  56 +/* Serial */
62 57 #define CONFIG_ATMEL_USART
63   -#define CONFIG_USART0
64   -#undef CONFIG_USART1
65   -#undef CONFIG_USART2
66   -#undef CONFIG_USART3
  58 +#define CONFIG_USART_BASE ATMEL_BASE_DBGU
  59 +#define CONFIG_USART_ID ATMEL_ID_SYS
  60 +#define CONFIG_BAUDRATE 115200
  61 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
67 62  
68 63 #define CONFIG_BOOTDELAY 3
69 64  
70 65 /*
71 66 * BOOTP options
72 67 */
73   -#define CONFIG_BOOTP_BOOTFILESIZE 1
74   -#define CONFIG_BOOTP_BOOTPATH 1
75   -#define CONFIG_BOOTP_GATEWAY 1
76   -#define CONFIG_BOOTP_HOSTNAME 1
  68 +#define CONFIG_BOOTP_BOOTFILESIZE
  69 +#define CONFIG_BOOTP_BOOTPATH
  70 +#define CONFIG_BOOTP_GATEWAY
  71 +#define CONFIG_BOOTP_HOSTNAME
77 72  
78 73 /*
79 74 * Command line configuration.
80 75  
... ... @@ -86,14 +81,16 @@
86 81 #undef CONFIG_CMD_LOADS
87 82 #undef CONFIG_CMD_SOURCE
88 83  
89   -#define CONFIG_CMD_PING 1
90   -#define CONFIG_CMD_DHCP 1
91   -#define CONFIG_CMD_USB 1
  84 +#define CONFIG_CMD_PING
  85 +#define CONFIG_CMD_DHCP
  86 +#define CONFIG_CMD_USB
92 87  
93 88 /* SDRAM */
94 89 #define CONFIG_NR_DRAM_BANKS 1
95   -#define PHYS_SDRAM 0x20000000
96   -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
  90 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
  91 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
  92 +#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
  93 + GENERATED_GBL_DATA_SIZE)
97 94  
98 95 /* SPI EEPROM */
99 96 #define CONFIG_SPI
... ... @@ -117,7 +114,7 @@
117 114 #define CONFIG_NAND_ATMEL
118 115 #define CONFIG_SYS_MAX_NAND_DEVICE 1
119 116 #define CONFIG_SYS_NAND_BASE 0x40000000
120   -#define CONFIG_SYS_NAND_DBW_8 1
  117 +#define CONFIG_SYS_NAND_DBW_8
121 118 /* our ALE is AD21 */
122 119 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
123 120 /* our CLE is AD22 */
124 121  
125 122  
126 123  
127 124  
... ... @@ -129,27 +126,27 @@
129 126 #define CONFIG_SYS_NO_FLASH 1
130 127  
131 128 /* Ethernet */
132   -#define CONFIG_MACB 1
133   -#define CONFIG_RMII 1
134   -#define CONFIG_NET_MULTI 1
  129 +#define CONFIG_MACB
  130 +#define CONFIG_RMII
  131 +#define CONFIG_NET_MULTI
135 132 #define CONFIG_NET_RETRY_COUNT 20
136   -#define CONFIG_RESET_PHY_R 1
137   -#define CONFIG_MACB_SEARCH_PHY 1
  133 +#define CONFIG_RESET_PHY_R
  134 +#define CONFIG_MACB_SEARCH_PHY
138 135  
139 136 /* USB */
140 137 #define CONFIG_USB_ATMEL
141   -#define CONFIG_USB_OHCI_NEW 1
142   -#define CONFIG_DOS_PARTITION 1
143   -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
  138 +#define CONFIG_USB_OHCI_NEW
  139 +#define CONFIG_DOS_PARTITION
  140 +#define CONFIG_SYS_USB_OHCI_CPU_INIT
144 141 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
145 142 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
146 143 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
147   -#define CONFIG_USB_STORAGE 1
148   -#define CONFIG_CMD_FAT 1
  144 +#define CONFIG_USB_STORAGE
  145 +#define CONFIG_CMD_FAT
149 146  
150 147 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
151 148  
152   -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  149 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
153 150 #define CONFIG_SYS_MEMTEST_END 0x23e00000
154 151  
155 152 /* Env in EEPROM, bootstrap + u-boot in NAND*/
... ... @@ -172,8 +169,6 @@
172 169 "120M(rootfs),-(other) " \
173 170 "rw rootfstype=jffs2"
174 171  
175   -#define CONFIG_BAUDRATE 115200
176   -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
177 172  
178 173 #define CONFIG_SYS_PROMPT "U-Boot> "
179 174 #define CONFIG_SYS_CBSIZE 256