Commit 67d54c39178aef2ea691c09dc115ed44ea92f46e
Committed by
Stefano Babic
1 parent
3fc4176dc4
Exists in
master
and in
53 other branches
i.MX6: nitrogen6x: Don't bother setting PLL3(480) PFD1 divisor
This clock isn't feeding anything under U-Boot, so there's no point in changing it from power-on default. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Showing 1 changed file with 0 additions and 5 deletions Side-by-side Diff
board/boundary/nitrogen6x/nitrogen6x.c
... | ... | @@ -622,7 +622,6 @@ |
622 | 622 | static void setup_display(void) |
623 | 623 | { |
624 | 624 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
625 | - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; | |
626 | 625 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
627 | 626 | int reg; |
628 | 627 | |
... | ... | @@ -632,10 +631,6 @@ |
632 | 631 | reg = __raw_readl(&mxc_ccm->CCGR3); |
633 | 632 | reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; |
634 | 633 | writel(reg, &mxc_ccm->CCGR3); |
635 | - | |
636 | - /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ | |
637 | - writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); | |
638 | - writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set); | |
639 | 634 | |
640 | 635 | /* set LDB0, LDB1 clk select to 011/011 */ |
641 | 636 | reg = readl(&mxc_ccm->cs2cdr); |