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Commit 67ea78a0d8f7ac124b48c013b81944836c10866e

Authored by Ye Li
1 parent 2fd75c0ce6
Exists in smarc_8mm-imx_v2019.04_4.19.35_1.1.0 and in 1 other branch smarc_8m-imx_v2019.04_4.19.35_1.1.0

MLK-18458-1 DTS: mx6ull_arm2: Add board DTS files for DDR3 ARM2 

Add DTS files to support iMX6ULL 14x14 DDR3 ARM2.
Due to pin conflicts, need specified DTS for eMMC, EPDC, NAND/EIMNOR and tsc enabled.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit a3602fbc7b78bc82eb58160a7c5d94416a91f979)
(cherry picked from commit adc2229ede562689ed889256ce864c592f572b54)

Showing 9 changed files with 1262 additions and 39 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ 67ea78a
... ... @@ -572,6 +572,11 @@
572 572 imx6ul-pico-pi.dtb
573 573  
574 574 dtb-$(CONFIG_MX6ULL) += \
  575 + imx6ull-14x14-ddr3-arm2.dtb \
  576 + imx6ull-14x14-ddr3-arm2-epdc.dtb \
  577 + imx6ull-14x14-ddr3-arm2-emmc.dtb \
  578 + imx6ull-14x14-ddr3-arm2-gpmi-weim.dtb \
  579 + imx6ull-14x14-ddr3-arm2-tsc.dtb \
575 580 imx6ull-14x14-evk.dtb \
576 581 imx6ull-14x14-evk-emmc.dtb \
577 582 imx6ull-14x14-evk-gpmi-weim.dtb \
arch/arm/dts/imx6ul-14x14-ddr3-arm2.dts
Diff comments   View file @ 67ea78a
... ... @@ -143,7 +143,7 @@
143 143 flash: n25q032@0 {
144 144 #address-cells = <1>;
145 145 #size-cells = <1>;
146   - compatible = "st,n25q032";
  146 + compatible = "st,n25q032", "jedec,spi-nor";
147 147 spi-max-frequency = <20000000>;
148 148 reg = <0>;
149 149 };
arch/arm/dts/imx6ull-14x14-ddr3-arm2-emmc.dts
Diff comments   View file @ 67ea78a
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +#include "imx6ull-14x14-ddr3-arm2.dts"
  10 +
  11 +&usdhc1 {
  12 + pinctrl-0 = <&pinctrl_usdhc1>;
  13 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  14 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  15 + cd-gpios = <>;
  16 + wp-gpios = <>;
  17 + vmmc-supply = <>;
  18 + non-removable;
  19 + status = "okay";
  20 +};
arch/arm/dts/imx6ull-14x14-ddr3-arm2-epdc.dts
Diff comments   View file @ 67ea78a
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +#include "imx6ull-14x14-ddr3-arm2.dts"
  10 +
  11 +&epdc {
  12 + status = "okay";
  13 +};
  14 +
  15 +&fec2 {
  16 + status = "disabled";
  17 +};
  18 +
  19 +&lcdif {
  20 + status = "disabled";
  21 +};
  22 +
  23 +&max17135 {
  24 + status = "okay";
  25 +};
arch/arm/dts/imx6ull-14x14-ddr3-arm2-gpmi-weim.dts
Diff comments   View file @ 67ea78a
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +#include "imx6ull-14x14-ddr3-arm2.dts"
  10 +
  11 +&gpmi {
  12 + status ="okay";
  13 +};
  14 +
  15 +&qspi {
  16 + status ="disabled";
  17 +};
  18 +
  19 +&usdhc2{
  20 + status ="disabled";
  21 +};
arch/arm/dts/imx6ull-14x14-ddr3-arm2-lcdif.dts
Diff comments   View file @ 67ea78a
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +/* DTS file for LCDIF at imx6ull ddr3 arm2 board */
  10 +
  11 +#include "imx6ull-14x14-ddr3-arm2.dts"
  12 +
  13 +/ {
  14 + backlight {
  15 + status = "okay";
  16 + };
  17 +};
  18 +
  19 +&fec1 {
  20 + status = "disabled";
  21 +};
  22 +
  23 +&lcdif {
  24 + status = "okay";
  25 +};
  26 +
  27 +&pwm1 {
  28 + status = "okay";
  29 +};
arch/arm/dts/imx6ull-14x14-ddr3-arm2-tsc.dts
Diff comments   View file @ 67ea78a
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +#include "imx6ull-14x14-ddr3-arm2-lcdif.dts"
  10 +
  11 +&csi {
  12 + status = "disabled";
  13 +};
  14 +
  15 +&i2c1 {
  16 + status = "disabled";
  17 +};
  18 +
  19 +&reg_usb_otg1_vbus {
  20 + pinctrl-0 = < >;
  21 + gpio = < >;
  22 +};
  23 +
  24 +&ov5640 {
  25 + status = "disabled";
  26 +};
  27 +
  28 +&usbotg1 {
  29 + status = "disabled";
  30 +};
  31 +
  32 +&tsc {
  33 + pinctrl-names = "default";
  34 + pinctrl-0 = <&pinctrl_tsc>;
  35 + status = "okay";
  36 + xnur-gpio = <&gpio1 3 0>;
  37 + measure_delay_time = <0xfff>;
  38 + pre_charge_time = <0xffff>;
  39 +};
arch/arm/dts/imx6ull-14x14-ddr3-arm2.dts
Diff comments   View file @ 67ea78a
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +/dts-v1/;
  10 +
  11 +#include <dt-bindings/input/input.h>
  12 +#include "imx6ull.dtsi"
  13 +
  14 +/ {
  15 + model = "Freescale i.MX6 ULL DDR3 ARM2 Board";
  16 + compatible = "fsl,imx6ull-ddr3-arm2", "fsl,imx6ull";
  17 +
  18 + chosen {
  19 + stdout-path = &uart1;
  20 + };
  21 +
  22 + memory {
  23 + reg = <0x80000000 0x40000000>;
  24 + };
  25 +
  26 + backlight {
  27 + compatible = "pwm-backlight";
  28 + pwms = <&pwm1 0 5000000>;
  29 + brightness-levels = <0 4 8 16 32 64 128 255>;
  30 + default-brightness-level = <6>;
  31 + status = "disabled";
  32 + };
  33 +
  34 + pxp_v4l2 {
  35 + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
  36 + status = "okay";
  37 + };
  38 +
  39 + regulators {
  40 + compatible = "simple-bus";
  41 + #address-cells = <1>;
  42 + #size-cells = <0>;
  43 +
  44 + reg_sd1_vmmc: sd1_vmmc {
  45 + compatible = "regulator-fixed";
  46 + regulator-name = "SD1_SPWR";
  47 + regulator-min-microvolt = <3000000>;
  48 + regulator-max-microvolt = <3000000>;
  49 + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  50 + off-on-delay = <20000>;
  51 + enable-active-high;
  52 + };
  53 +
  54 + reg_sd2_vmmc: sd2_vmmc {
  55 + compatible = "regulator-fixed";
  56 + regulator-name = "SD2_SPWR";
  57 + regulator-min-microvolt = <3000000>;
  58 + regulator-max-microvolt = <3000000>;
  59 + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
  60 + enable-active-high;
  61 + };
  62 +
  63 + reg_can2_3v3: regulator@0 {
  64 + compatible = "regulator-fixed";
  65 + reg = <0>;
  66 + regulator-name = "can2-3v3";
  67 + regulator-min-microvolt = <3300000>;
  68 + regulator-max-microvolt = <3300000>;
  69 + gpio = <&gpio1 15 GPIO_ACTIVE_LOW>;
  70 + };
  71 +
  72 + reg_vref_3v3: regulator@1 {
  73 + compatible = "regulator-fixed";
  74 + regulator-name = "vref-3v3";
  75 + regulator-min-microvolt = <3300000>;
  76 + regulator-max-microvolt = <3300000>;
  77 + };
  78 +
  79 + reg_usb_otg1_vbus: regulator@2 {
  80 + compatible = "regulator-fixed";
  81 + reg = <2>;
  82 + pinctrl-names = "default";
  83 + pinctrl-0 = <&pinctrl_usb_otg1>;
  84 + regulator-name = "usb_otg1_vbus";
  85 + regulator-min-microvolt = <5000000>;
  86 + regulator-max-microvolt = <5000000>;
  87 + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
  88 + enable-active-high;
  89 + };
  90 + };
  91 +};
  92 +
  93 +&clks {
  94 + /* For bringup, comments this.
  95 + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
  96 + assigned-clock-rates = <786432000>;
  97 + */
  98 +};
  99 +
  100 +&cpu0 {
  101 + /*
  102 + * on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN,
  103 + * to align with other platform and use the same cpufreq
  104 + * driver, still use the seperated OPP define for arm
  105 + * and soc.
  106 + */
  107 + operating-points = <
  108 + /* kHz uV */
  109 + 528000 1175000
  110 + 396000 1175000
  111 + 198000 1175000
  112 + >;
  113 + fsl,soc-operating-points = <
  114 + /* KHz uV */
  115 + 528000 1175000
  116 + 396000 1175000
  117 + 198000 1175000
  118 + >;
  119 + fsl,arm-soc-shared = <1>;
  120 +};
  121 +
  122 +&reg_arm {
  123 + vin-supply = <&sw1a_reg>;
  124 + regulator-allow-bypass;
  125 +};
  126 +
  127 +&reg_soc {
  128 + vin-supply = <&sw1a_reg>;
  129 + regulator-allow-bypass;
  130 +};
  131 +
  132 +&csi {
  133 + status = "okay";
  134 +
  135 + port {
  136 + csi1_ep: endpoint {
  137 + remote-endpoint = <&ov5640_ep>;
  138 + };
  139 + };
  140 +};
  141 +
  142 +&ecspi1 {
  143 + fsl,spi-num-chipselects = <1>;
  144 + cs-gpios = <&gpio4 26 0>;
  145 + pinctrl-names = "default";
  146 + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>;
  147 + status = "disabled";
  148 +
  149 + flash: n25q032@0 {
  150 + #address-cells = <1>;
  151 + #size-cells = <1>;
  152 + compatible = "st,n25q032", "jedec,spi-nor";
  153 + spi-max-frequency = <20000000>;
  154 + reg = <0>;
  155 + };
  156 +};
  157 +
  158 +&epdc {
  159 + pinctrl-names = "default";
  160 + pinctrl-0 = <&pinctrl_epdc0>;
  161 + V3P3-supply = <&V3P3_reg>;
  162 + VCOM-supply = <&VCOM_reg>;
  163 + DISPLAY-supply = <&DISPLAY_reg>;
  164 + status = "disabled";
  165 +};
  166 +
  167 +&fec1 {
  168 + pinctrl-names = "default";
  169 + pinctrl-0 = <&pinctrl_enet1>;
  170 + phy-mode = "rmii";
  171 + phy-handle = <&ethphy0>;
  172 + status = "okay";
  173 +};
  174 +
  175 +&fec2 {
  176 + pinctrl-names = "default";
  177 + pinctrl-0 = <&pinctrl_enet2>;
  178 + phy-mode = "mii";
  179 + phy-handle = <&ethphy1>;
  180 + status = "okay";
  181 +
  182 + mdio {
  183 + #address-cells = <1>;
  184 + #size-cells = <0>;
  185 +
  186 + ethphy0: ethernet-phy@1 {
  187 + compatible = "ethernet-phy-ieee802.3-c22";
  188 + reg = <1>;
  189 + };
  190 +
  191 + ethphy1: ethernet-phy@2 {
  192 + compatible = "ethernet-phy-ieee802.3-c22";
  193 + reg = <2>;
  194 + };
  195 + };
  196 +};
  197 +
  198 +&flexcan2 {
  199 + pinctrl-names = "default";
  200 + pinctrl-0 = <&pinctrl_flexcan2>;
  201 + xceiver-supply = <&reg_can2_3v3>;
  202 + status = "disabled";
  203 +};
  204 +
  205 +&gpc {
  206 + fsl,cpu_pupscr_sw2iso = <0xf>;
  207 + fsl,cpu_pupscr_sw = <0x0>;
  208 + fsl,cpu_pdnscr_iso2sw = <0x1>;
  209 + fsl,cpu_pdnscr_iso = <0x1>;
  210 + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
  211 +};
  212 +
  213 +&gpmi {
  214 + pinctrl-names = "default";
  215 + pinctrl-0 = <&pinctrl_gpmi_nand_1>;
  216 + status = "disabled";
  217 + nand-on-flash-bbt;
  218 +};
  219 +
  220 +&i2c1 {
  221 + clock-frequency = <100000>;
  222 + pinctrl-names = "default", "gpio";
  223 + pinctrl-0 = <&pinctrl_i2c1>;
  224 + pinctrl-1 = <&pinctrl_i2c1_gpio>;
  225 + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  226 + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
  227 + status = "okay";
  228 +
  229 + pmic: pfuze100@08 {
  230 + compatible = "fsl,pfuze200";
  231 + reg = <0x08>;
  232 +
  233 + regulators {
  234 + sw1a_reg: sw1ab {
  235 + regulator-min-microvolt = <300000>;
  236 + regulator-max-microvolt = <1875000>;
  237 + regulator-always-on;
  238 + regulator-ramp-delay = <6250>;
  239 + };
  240 +
  241 + sw2_reg: sw2 {
  242 + regulator-min-microvolt = <800000>;
  243 + regulator-max-microvolt = <3300000>;
  244 + regulator-always-on;
  245 + };
  246 +
  247 + sw3a_reg: sw3a {
  248 + regulator-min-microvolt = <400000>;
  249 + regulator-max-microvolt = <1975000>;
  250 + regulator-always-on;
  251 + };
  252 +
  253 + sw3b_reg: sw3b {
  254 + regulator-min-microvolt = <800000>;
  255 + regulator-max-microvolt = <3300000>;
  256 + regulator-always-on;
  257 + };
  258 +
  259 + swbst_reg: swbst {
  260 + regulator-min-microvolt = <5000000>;
  261 + regulator-max-microvolt = <5150000>;
  262 + };
  263 +
  264 + snvs_reg: vsnvs {
  265 + regulator-min-microvolt = <1000000>;
  266 + regulator-max-microvolt = <3000000>;
  267 + regulator-always-on;
  268 + };
  269 +
  270 + vref_reg: vrefddr {
  271 + regulator-always-on;
  272 + };
  273 +
  274 + vgen1_reg: vgen1 {
  275 + regulator-min-microvolt = <800000>;
  276 + regulator-max-microvolt = <1550000>;
  277 + };
  278 +
  279 + vgen2_reg: vgen2 {
  280 + regulator-min-microvolt = <800000>;
  281 + regulator-max-microvolt = <1550000>;
  282 + };
  283 +
  284 + vgen3_reg: vgen3 {
  285 + regulator-min-microvolt = <1800000>;
  286 + regulator-max-microvolt = <3300000>;
  287 + };
  288 +
  289 + vgen4_reg: vgen4 {
  290 + regulator-min-microvolt = <1800000>;
  291 + regulator-max-microvolt = <3300000>;
  292 + regulator-always-on;
  293 + };
  294 +
  295 + vgen5_reg: vgen5 {
  296 + regulator-min-microvolt = <1800000>;
  297 + regulator-max-microvolt = <3300000>;
  298 + regulator-always-on;
  299 + };
  300 +
  301 + vgen6_reg: vgen6 {
  302 + regulator-min-microvolt = <1800000>;
  303 + regulator-max-microvolt = <3300000>;
  304 + regulator-always-on;
  305 + };
  306 + };
  307 + };
  308 +
  309 +
  310 + ov5640: ov5640@3c {
  311 + compatible = "ovti,ov5640";
  312 + reg = <0x3c>;
  313 + pinctrl-names = "default";
  314 + pinctrl-0 = <&pinctrl_csi1>;
  315 + clocks = <&clks IMX6UL_CLK_CSI>;
  316 + clock-names = "csi_mclk";
  317 + AVDD-supply = <&vgen3_reg>; /* 2.8v */
  318 + DVDD-supply = <&vgen2_reg>; /* 1.5v*/
  319 + pwn-gpios = <&gpio5 8 1>;
  320 + rst-gpios = <&gpio5 7 0>;
  321 + csi_id = <0>;
  322 + mclk = <24000000>;
  323 + mclk_source = <0>;
  324 + status = "okay";
  325 + port {
  326 + ov5640_ep: endpoint {
  327 + remote-endpoint = <&csi1_ep>;
  328 + };
  329 + };
  330 + };
  331 +};
  332 +
  333 +&i2c4 {
  334 + clock-frequency = <100000>;
  335 + pinctrl-names = "default", "gpio";
  336 + pinctrl-0 = <&pinctrl_i2c4>;
  337 + pinctrl-1 = <&pinctrl_i2c4_gpio>;
  338 + scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
  339 + sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
  340 + status = "okay";
  341 +
  342 + max17135: max17135@48 {
  343 + pinctrl-names = "default";
  344 + pinctrl-0 = <&pinctrl_max17135>;
  345 + compatible = "maxim,max17135";
  346 + reg = <0x48>;
  347 + status = "disabled";
  348 +
  349 + vneg_pwrup = <1>;
  350 + gvee_pwrup = <2>;
  351 + vpos_pwrup = <10>;
  352 + gvdd_pwrup = <12>;
  353 + gvdd_pwrdn = <1>;
  354 + vpos_pwrdn = <2>;
  355 + gvee_pwrdn = <8>;
  356 + vneg_pwrdn = <10>;
  357 + gpio_pmic_pwrgood = <&gpio3 16 0>;
  358 + gpio_pmic_vcom_ctrl = <&gpio3 24 0>;
  359 + gpio_pmic_wakeup = <&gpio3 14 0>;
  360 + gpio_pmic_v3p3 = <&gpio3 17 0>;
  361 + gpio_pmic_intr = <&gpio3 13 0>;
  362 +
  363 + regulators {
  364 + DISPLAY_reg: DISPLAY {
  365 + regulator-name = "DISPLAY";
  366 + };
  367 +
  368 + GVDD_reg: GVDD {
  369 + /* 20v */
  370 + regulator-name = "GVDD";
  371 + };
  372 +
  373 + GVEE_reg: GVEE {
  374 + /* -22v */
  375 + regulator-name = "GVEE";
  376 + };
  377 +
  378 + HVINN_reg: HVINN {
  379 + /* -22v */
  380 + regulator-name = "HVINN";
  381 + };
  382 +
  383 + HVINP_reg: HVINP {
  384 + /* 20v */
  385 + regulator-name = "HVINP";
  386 + };
  387 +
  388 + VCOM_reg: VCOM {
  389 + regulator-name = "VCOM";
  390 + /* Real max: -500000 */
  391 + regulator-max-microvolt = <4325000>;
  392 + /* Real min: -4325000 */
  393 + regulator-min-microvolt = <500000>;
  394 + };
  395 +
  396 + VNEG_reg: VNEG {
  397 + /* -15v */
  398 + regulator-name = "VNEG";
  399 + };
  400 +
  401 + VPOS_reg: VPOS {
  402 + /* 15v */
  403 + regulator-name = "VPOS";
  404 + };
  405 +
  406 + V3P3_reg: V3P3 {
  407 + regulator-name = "V3P3";
  408 + };
  409 + };
  410 + };
  411 +};
  412 +
  413 +&iomuxc {
  414 + imx6ul-ddr3-arm2 {
  415 + pinctrl_adc1: adc1grp {
  416 + fsl,pins = <
  417 + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0
  418 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
  419 + >;
  420 + };
  421 +
  422 +
  423 + pinctrl_csi1: csi1grp {
  424 + fsl,pins = <
  425 + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
  426 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
  427 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
  428 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
  429 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
  430 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
  431 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
  432 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
  433 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
  434 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
  435 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
  436 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
  437 + >;
  438 + };
  439 +
  440 + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 {
  441 + fsl,pins = <
  442 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0
  443 + >;
  444 + };
  445 +
  446 + pinctrl_ecspi1_1: ecspi1grp-1 {
  447 + fsl,pins = <
  448 + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0
  449 + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0
  450 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0
  451 + >;
  452 + };
  453 +
  454 + pinctrl_enet1: enet1grp {
  455 + fsl,pins = <
  456 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
  457 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
  458 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
  459 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
  460 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
  461 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
  462 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
  463 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a0
  464 + >;
  465 + };
  466 +
  467 + pinctrl_enet2: enet2grp {
  468 + fsl,pins = <
  469 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b098
  470 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
  471 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0
  472 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0
  473 + MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0a0
  474 + MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0a0
  475 + MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b0a8
  476 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
  477 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
  478 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
  479 + MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x1b0b0
  480 + MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x1b0b0
  481 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
  482 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
  483 + MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8
  484 + MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0
  485 + MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0
  486 + >;
  487 + };
  488 +
  489 + pinctrl_epdc0: epdcgrp0 {
  490 + fsl,pins = <
  491 + MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x10b1
  492 + MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x10b1
  493 + MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x10b1
  494 + MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x10b1
  495 + MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x10b1
  496 + MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x10b1
  497 + MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x10b1
  498 + MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x10b1
  499 + MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x10b1
  500 + MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x10b1
  501 + MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x10b1
  502 + MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x10b1
  503 + MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x10b1
  504 + MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x10b1
  505 + MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x10b1
  506 + MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x10b1
  507 + MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x10b1
  508 + MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x10b1
  509 + MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x10b1
  510 + MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x10b1
  511 + MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x10b1
  512 + MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x10b1
  513 + MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x10b1
  514 + MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x10b1
  515 + MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x10b1
  516 + >;
  517 + };
  518 +
  519 + pinctrl_esai: esaigrp {
  520 + fsl,pins = <
  521 + MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x1b0b0
  522 + MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x1b0b0
  523 + MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x1b0b0
  524 + MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x1b0b0
  525 + MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x1b0b0
  526 + MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x1b0b0
  527 + MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x1b0b0
  528 + MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x1b0b0
  529 + MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x1b0b0
  530 + MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x1b0b0
  531 + MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x1b0b0
  532 + MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x1b0b0
  533 + >;
  534 + };
  535 +
  536 + pinctrl_flexcan2: flexcan2grp{
  537 + fsl,pins = <
  538 + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
  539 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
  540 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */
  541 + >;
  542 + };
  543 +
  544 + pinctrl_gpmi_nand_1: gpmi-nand-1 {
  545 + fsl,pins = <
  546 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
  547 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
  548 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
  549 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
  550 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
  551 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
  552 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
  553 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
  554 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
  555 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
  556 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
  557 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
  558 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
  559 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
  560 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
  561 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
  562 + >;
  563 + };
  564 +
  565 + pinctrl_i2c1: i2c1grp {
  566 + fsl,pins = <
  567 + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1
  568 + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1
  569 + >;
  570 + };
  571 +
  572 + pinctrl_i2c1_gpio: i2c1grp_gpio {
  573 + fsl,pins = <
  574 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x1b8b1
  575 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b8b1
  576 + >;
  577 + };
  578 +
  579 + pinctrl_i2c4: i2c4grp {
  580 + fsl,pins = <
  581 + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0
  582 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0
  583 + >;
  584 + };
  585 +
  586 + pinctrl_i2c4_gpio: i2c4grp_gpio {
  587 + fsl,pins = <
  588 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x1b8b0
  589 + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x1b8b0
  590 + >;
  591 + };
  592 +
  593 + pinctrl_lcdif_dat: lcdifdatgrp {
  594 + fsl,pins = <
  595 + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
  596 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
  597 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
  598 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
  599 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
  600 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
  601 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
  602 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
  603 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
  604 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
  605 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
  606 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
  607 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
  608 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
  609 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
  610 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
  611 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
  612 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
  613 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
  614 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
  615 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
  616 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
  617 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
  618 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
  619 + >;
  620 + };
  621 +
  622 + pinctrl_lcdif_ctrl: lcdifctrlgrp {
  623 + fsl,pins = <
  624 + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
  625 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
  626 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
  627 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
  628 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
  629 + >;
  630 + };
  631 +
  632 + pinctrl_max17135: max17135grp-1 {
  633 + fsl,pins = <
  634 + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x80000000 /* pwrgood */
  635 + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x80000000 /* vcom_ctrl */
  636 + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x80000000 /* wakeup */
  637 + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x80000000 /* v3p3 */
  638 + MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x80000000 /* pwr int */
  639 + >;
  640 + };
  641 +
  642 + pinctrl_mqs: mqsgrp {
  643 + fsl,pins = <
  644 + MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x11088
  645 + MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x11088
  646 + >;
  647 + };
  648 +
  649 + pinctrl_pwm1: pmw1grp {
  650 + fsl,pins = <
  651 + MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x110b0
  652 + >;
  653 + };
  654 +
  655 + pinctrl_qspi: qspigrp {
  656 + fsl,pins = <
  657 + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
  658 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
  659 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
  660 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
  661 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
  662 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
  663 +#ifdef REWORKED_ENABLE_ALL_QSPI
  664 + MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1
  665 + MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1
  666 + MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1
  667 + MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1
  668 + MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1
  669 + MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1
  670 + MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1
  671 + MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1
  672 +#endif
  673 + >;
  674 + };
  675 +
  676 + pinctrl_sai2: sai2grp {
  677 + fsl,pins = <
  678 + MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x1b0b0
  679 + MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x1b0b0
  680 + MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x110b0
  681 + MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x110b0
  682 + MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x1b0b0
  683 + >;
  684 + };
  685 +
  686 + pinctrl_spdif: spdifgrp {
  687 + fsl,pins = <
  688 + MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x1b0b0
  689 + MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x1b0b0
  690 + >;
  691 + };
  692 +
  693 + pinctrl_tsc: tscgrp {
  694 + fsl,pins = <
  695 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
  696 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
  697 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
  698 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
  699 + >;
  700 + };
  701 +
  702 + pinctrl_uart1: uart1grp {
  703 + fsl,pins = <
  704 + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
  705 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
  706 + >;
  707 + };
  708 +
  709 + pinctrl_uart2: uart2grp {
  710 + fsl,pins = <
  711 + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
  712 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
  713 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
  714 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
  715 + >;
  716 + };
  717 +
  718 + pinctrl_uart2dte: uart2dtegrp {
  719 + fsl,pins = <
  720 + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
  721 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
  722 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1
  723 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1
  724 + >;
  725 + };
  726 +
  727 + pinctrl_usb_otg1_id: usbotg1idgrp {
  728 + fsl,pins = <
  729 + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
  730 + >;
  731 + };
  732 +
  733 + pinctrl_usb_otg1: usbotg1grp {
  734 + fsl,pins = <
  735 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0
  736 + >;
  737 + };
  738 +
  739 + pinctrl_usdhc1: usdhc1grp {
  740 + fsl,pins = <
  741 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
  742 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
  743 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
  744 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
  745 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
  746 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
  747 + >;
  748 + };
  749 +
  750 + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
  751 + fsl,pins = <
  752 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
  753 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
  754 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
  755 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
  756 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
  757 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
  758 + >;
  759 + };
  760 +
  761 + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  762 + fsl,pins = <
  763 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
  764 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
  765 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
  766 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
  767 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
  768 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
  769 + >;
  770 + };
  771 +
  772 + pinctrl_usdhc1_8bit: usdhc1_8bit_grp {
  773 + fsl,pins = <
  774 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
  775 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
  776 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
  777 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
  778 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
  779 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
  780 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
  781 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
  782 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
  783 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
  784 + >;
  785 + };
  786 +
  787 + pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp {
  788 + fsl,pins = <
  789 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
  790 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
  791 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
  792 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
  793 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
  794 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
  795 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9
  796 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9
  797 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9
  798 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9
  799 + >;
  800 + };
  801 +
  802 + pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp {
  803 + fsl,pins = <
  804 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
  805 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
  806 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
  807 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
  808 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
  809 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
  810 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9
  811 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9
  812 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9
  813 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9
  814 + >;
  815 + };
  816 +
  817 + pinctrl_usdhc1_cd_wp: usdhc1_cd_wp_grp {
  818 + fsl,pins = <
  819 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
  820 + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* SD1 WP */
  821 + >;
  822 + };
  823 +
  824 + pinctrl_usdhc1_rst: usdhc1_rst_grp {
  825 + fsl,pins = <
  826 + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
  827 + >;
  828 + };
  829 +
  830 + pinctrl_usdhc1_vselect: usdhc1_vselect_grp {
  831 + fsl,pins = <
  832 + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
  833 + >;
  834 + };
  835 +
  836 + pinctrl_usdhc2: usdhc2grp {
  837 + fsl,pins = <
  838 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
  839 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
  840 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
  841 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
  842 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
  843 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
  844 + >;
  845 + };
  846 +
  847 + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  848 + fsl,pins = <
  849 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
  850 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100a9
  851 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170a9
  852 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170a9
  853 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170a9
  854 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170a9
  855 + >;
  856 + };
  857 +
  858 + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  859 + fsl,pins = <
  860 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
  861 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
  862 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
  863 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
  864 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
  865 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
  866 + >;
  867 + };
  868 +
  869 + pinctrl_usdhc2_rst: usdhc2_rst_grp {
  870 + fsl,pins = <
  871 + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESET */
  872 + >;
  873 + };
  874 +
  875 + pinctrl_wdog: wdoggrp {
  876 + fsl,pins = <
  877 + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x30b0
  878 + >;
  879 + };
  880 + };
  881 +};
  882 +
  883 +&iomuxc_snvs {
  884 + imx6ul-ddr3-arm2 {
  885 + pinctrl_bt: btgrp {
  886 + fsl,pins = <
  887 + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000
  888 + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000
  889 + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000
  890 + >;
  891 + };
  892 +
  893 + pinctrl_sai2_hp_det_b: sai2_hp_det_grp {
  894 + fsl,pins = <
  895 + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
  896 + >;
  897 + };
  898 + };
  899 +};
  900 +
  901 +&lcdif {
  902 + pinctrl-names = "default";
  903 + pinctrl-0 = <&pinctrl_lcdif_dat
  904 + &pinctrl_lcdif_ctrl>;
  905 + display = <&display0>;
  906 + status = "disabled";
  907 +
  908 + display0: display {
  909 + bits-per-pixel = <16>;
  910 + bus-width = <24>;
  911 +
  912 + display-timings {
  913 + native-mode = <&timing0>;
  914 + timing0: timing0 {
  915 + clock-frequency = <33500000>;
  916 + hactive = <800>;
  917 + vactive = <480>;
  918 + hback-porch = <89>;
  919 + hfront-porch = <164>;
  920 + vback-porch = <23>;
  921 + vfront-porch = <10>;
  922 + hsync-len = <10>;
  923 + vsync-len = <10>;
  924 + hsync-active = <0>;
  925 + vsync-active = <0>;
  926 + de-active = <1>;
  927 + pixelclk-active = <0>;
  928 + };
  929 + };
  930 + };
  931 +};
  932 +
  933 +&pwm1 {
  934 + pinctrl-names = "default";
  935 + pinctrl-0 = <&pinctrl_pwm1>;
  936 + status = "disabled";
  937 +};
  938 +
  939 +&pxp {
  940 + status = "okay";
  941 +};
  942 +
  943 +&qspi {
  944 + pinctrl-names = "default";
  945 + pinctrl-0 = <&pinctrl_qspi>;
  946 + status = "okay";
  947 +#ifdef REWORKED_ENABLE_ALL_QSPI
  948 + fsl,qspi-has-second-chip = <1>;
  949 +#endif
  950 + ddrsmp=<0>;
  951 +
  952 + flash0: n25q256a@0 {
  953 + #address-cells = <1>;
  954 + #size-cells = <1>;
  955 + compatible = "micron,n25q256a", "jedec,spi-nor";
  956 + spi-max-frequency = <29000000>;
  957 + spi-nor,ddr-quad-read-dummy = <6>;
  958 + reg = <0>;
  959 + };
  960 +
  961 +#ifdef REWORKED_ENABLE_ALL_QSPI
  962 +
  963 + flash1: n25q256a@1 {
  964 + #address-cells = <1>;
  965 + #size-cells = <1>;
  966 + compatible = "micron,n25q256a", "jedec,spi-nor";
  967 + spi-max-frequency = <29000000>;
  968 + spi-nor,ddr-quad-read-dummy = <6>;
  969 + reg = <1>;
  970 + };
  971 +
  972 + flash2: n25q256a@2 {
  973 + #address-cells = <1>;
  974 + #size-cells = <1>;
  975 + compatible = "micron,n25q256a", "jedec,spi-nor";
  976 + spi-max-frequency = <29000000>;
  977 + spi-nor,ddr-quad-read-dummy = <6>;
  978 + reg = <2>;
  979 + };
  980 +
  981 + flash3: n25q256a@3 {
  982 + #address-cells = <1>;
  983 + #size-cells = <1>;
  984 + compatible = "micron,n25q256a", "jedec,spi-nor";
  985 + spi-max-frequency = <29000000>;
  986 + spi-nor,ddr-quad-read-dummy = <6>;
  987 + reg = <3>;
  988 + };
  989 +#endif
  990 +};
  991 +
  992 +&uart1 {
  993 + pinctrl-names = "default";
  994 + pinctrl-0 = <&pinctrl_uart1>;
  995 + status = "okay";
  996 +};
  997 +
  998 +&uart2 {
  999 + pinctrl-names = "default";
  1000 + pinctrl-0 = <&pinctrl_uart2
  1001 + &pinctrl_bt>;
  1002 + fsl,uart-has-rtscts;
  1003 + /* for DTE mode, add below change */
  1004 + /* fsl,dte-mode; */
  1005 + /* pinctrl-0 = <&pinctrl_uart2dte>; */
  1006 + status = "disabled";
  1007 +};
  1008 +
  1009 +&usbotg1 {
  1010 + vbus-supply = <&reg_usb_otg1_vbus>;
  1011 + pinctrl-names = "default";
  1012 + pinctrl-0 = <&pinctrl_usb_otg1_id>;
  1013 + srp-disable;
  1014 + hnp-disable;
  1015 + adp-disable;
  1016 + status = "okay";
  1017 +};
  1018 +
  1019 +&usdhc1 {
  1020 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  1021 + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>;
  1022 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>;
  1023 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>;
  1024 + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  1025 + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
  1026 + keep-power-in-suspend;
  1027 + enable-sdio-wakeup;
  1028 + vmmc-supply = <&reg_sd1_vmmc>;
  1029 + status = "okay";
  1030 +};
  1031 +
  1032 +&usdhc2 {
  1033 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  1034 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_rst>;
  1035 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_rst>;
  1036 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_rst>;
  1037 + non-removable;
  1038 + no-1-8-v; /* VSELECT not connected by default */
  1039 + keep-power-in-suspend;
  1040 + enable-sdio-wakeup;
  1041 + vmmc-supply = <&reg_sd2_vmmc>;
  1042 + status = "okay";
  1043 +};
  1044 +
  1045 +&wdog1 {
  1046 + pinctrl-names = "default";
  1047 + pinctrl-0 = <&pinctrl_wdog>;
  1048 + fsl,ext-reset-output;
  1049 +};
arch/arm/dts/imx6ull-pinfunc.h
Diff comments   View file @ 67ea78a
... ... @@ -14,45 +14,80 @@
14 14 * The pin function ID is a tuple of
15 15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 16 */
17   -#define MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
18   -#define MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
19   -#define MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
20   -#define MX6UL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0
21   -#define MX6UL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0
22   -#define MX6UL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0
23   -#define MX6UL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0
24   -#define MX6UL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0
25   -#define MX6UL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0
26   -#define MX6UL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0
27   -#define MX6UL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0
28   -#define MX6UL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0
29   -#define MX6UL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0
30   -#define MX6UL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0
31   -#define MX6UL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0
32   -#define MX6UL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0
33   -#define MX6UL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0
34   -#define MX6UL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0
35   -#define MX6UL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0
36   -#define MX6UL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0
37   -#define MX6UL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0
38   -#define MX6UL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0
39   -#define MX6UL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0
40   -#define MX6UL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0
41   -#define MX6UL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0
42   -#define MX6UL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0
  17 +#define MX6ULL_PAD_ENET1_RX_DATA0__EPDC_SDCE04 0x00C4 0x0350 0x0000 0x9 0x0
  18 +#define MX6ULL_PAD_ENET1_RX_DATA1__EPDC_SDCE05 0x00C8 0x0354 0x0000 0x9 0x0
  19 +#define MX6ULL_PAD_ENET1_RX_EN__EPDC_SDCE06 0x00CC 0x0358 0x0000 0x9 0x0
  20 +#define MX6ULL_PAD_ENET1_TX_DATA0__EPDC_SDCE07 0x00D0 0x035C 0x0000 0x9 0x0
  21 +#define MX6ULL_PAD_ENET1_TX_DATA1__EPDC_SDCE08 0x00D4 0x0360 0x0000 0x9 0x0
  22 +#define MX6ULL_PAD_ENET1_TX_EN__EPDC_SDCE09 0x00D8 0x0364 0x0000 0x9 0x0
  23 +#define MX6ULL_PAD_ENET1_TX_CLK__EPDC_SDOED 0x00DC 0x0368 0x0000 0x9 0x0
  24 +#define MX6ULL_PAD_ENET1_RX_ER__EPDC_SDOEZ 0x00E0 0x036C 0x0000 0x9 0x0
  25 +#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
  26 +#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
  27 +#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
  28 +#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0
  29 +#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0
  30 +#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0
  31 +#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0
  32 +#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0
  33 +#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0
  34 +#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0
  35 +#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0
  36 +#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0
  37 +#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0
  38 +#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0
  39 +#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0
  40 +#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0
  41 +#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0
  42 +#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0
  43 +#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0
  44 +#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0
  45 +#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0
  46 +#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0
  47 +#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0
  48 +#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0
  49 +#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0
  50 +#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0
  51 +#define MX6ULL_PAD_LCD_DATA22__EPDC_SDCE02 0x0170 0x03FC 0x0000 0x9 0x0
  52 +#define MX6ULL_PAD_LCD_DATA23__EPDC_SDCE03 0x0174 0x0400 0x0000 0x9 0x0
  53 +#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0
  54 +#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0
  55 +#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0
  56 +#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0
  57 +#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
  58 +#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
  59 +#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
  60 +#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
  61 +#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
  62 +#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
  63 +#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0
  64 +#define MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0
43 65  
44   -#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0
45   -#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0
46   -#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0
47   -#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0
48   -#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
49   -#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
50   -#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
51   -#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
52   -#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
53   -#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
54   -#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0
55   -#define MX6UL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0
  66 +#define MX6UL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0
  67 +#define MX6UL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
  68 +#define MX6UL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
  69 +#define MX6UL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0
  70 +#define MX6UL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0
  71 +#define MX6UL_PAD_UART1_CTS_B__UART5_DTE_RTS 0x008C 0x0318 0x0640 0x9 0x3
  72 +#define MX6UL_PAD_UART1_RTS_B__UART5_DCE_RTS 0x0090 0x031C 0x0640 0x9 0x4
  73 +#define MX6UL_PAD_UART1_RTS_B__UART5_DTE_CTS 0x0090 0x031C 0x0000 0x9 0x0
  74 +#define MX6UL_PAD_UART4_RX_DATA__EPDC_PWRCTRL01 0x00B8 0x0344 0x0000 0x9 0x0
  75 +#define MX6UL_PAD_UART5_TX_DATA__EPDC_PWRCTRL02 0x00BC 0x0348 0x0000 0x9 0x0
  76 +#define MX6UL_PAD_UART5_RX_DATA__EPDC_PWRCTRL03 0x00C0 0x034C 0x0000 0x9 0x0
  77 +
  78 +/* Below pinfunc are different with i.MX6UL, so override them in here
  79 + * To avoid build warning, firstly undef them.
  80 + */
  81 +#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX
  82 +#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX
  83 +#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS
  84 +#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS
  85 +#undef MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS
  86 +#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
  87 +#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
  88 +#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
  89 +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
  90 +#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
56 91  
57 92 #endif /* __DTS_IMX6ULL_PINFUNC_H */