Eric Lee / smarc-uboot | Embedian Git Server

Commit 68432c27438360aa3bc27c0c73bf3c12a8c6ffa7

Authored by Lei Wen 2011-04-14 02:18:16 +0800

Committed by Albert ARIBAUD 2011-04-28 01:38:07 +0800

Exists in master and in 55 other branches

pxa: move i2c driver to the common place

For better sharing with other platform other than pxa's,
it is more convenient to put the driver to the common place.

Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Lei Wen <leiwen@marvell.com>

Showing 6 changed files with 455 additions and 470 deletions Inline Diff

arch/arm/cpu/pxa/Makefile
arch/arm/cpu/pxa/i2c.c
drivers/i2c/Makefile
drivers/i2c/mv_i2c.c
include/configs/innokom.h
include/configs/xm250.h

arch/arm/cpu/pxa/Makefile

Diff comments View file @ 68432c2

 #
 # (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
 # published by the Free Software Foundation; either version 2 of
 # the License, or (at your option) any later version.
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
 include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).o
 START	= start.o
 COBJS	+= cpu.o
-COBJS	+= i2c.o
 COBJS	+= pxafb.o
 COBJS	+= timer.o
 COBJS	+= usb.o
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 START	:= $(addprefix $(obj),$(START))
 all:	$(obj).depend $(START) $(LIB)
 $(LIB):	$(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 #########################################################################
 # defines $(obj).depend target
 include $(SRCTREE)/rules.mk
 sinclude $(obj).depend
 #########################################################################

arch/arm/cpu/pxa/i2c.c

View file @ 68432c2

1	/*		File was deleted
2	* (C) Copyright 2000
3	* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
4	*
5	* (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6	* Marius Groeger <mgroeger@sysgo.de>
7	*
8	* (C) Copyright 2003 Pengutronix e.K.
9	* Robert Schwebel <r.schwebel@pengutronix.de>
10	*
11	* See file CREDITS for list of people who contributed to this
12	* project.
13	*
14	* This program is free software; you can redistribute it and/or
15	* modify it under the terms of the GNU General Public License as
16	* published by the Free Software Foundation; either version 2 of
17	* the License, or (at your option) any later version.
18	*
19	* This program is distributed in the hope that it will be useful,
20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22	* GNU General Public License for more details.
23	*
24	* You should have received a copy of the GNU General Public License
25	* along with this program; if not, write to the Free Software
26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27	* MA 02111-1307 USA
28	*
29	* Back ported to the 8xx platform (from the 8260 platform) by
30	* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
31	*/
32
33	/* FIXME: this file is PXA255 specific! What about other XScales? */
34
35	#include <common.h>
36	#include <asm/io.h>
37
38	#ifdef CONFIG_HARD_I2C
39
40	/*
41	* - CONFIG_SYS_I2C_SPEED
42	* - I2C_PXA_SLAVE_ADDR
43	*/
44
45	#include <asm/arch/hardware.h>
46	#include <asm/arch/pxa-regs.h>
47	#include <i2c.h>
48
49	/#define DEBUG_I2C 1 /### activate local debugging output */
50	#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */
51
52	#if (CONFIG_SYS_I2C_SPEED == 400000)
53	#define I2C_ICR_INIT (ICR_FM \| ICR_BEIE \| ICR_IRFIE \| ICR_ITEIE \| ICR_GCD \| ICR_SCLE)
54	#else
55	#define I2C_ICR_INIT (ICR_BEIE \| ICR_IRFIE \| ICR_ITEIE \| ICR_GCD \| ICR_SCLE)
56	#endif
57
58	#define I2C_ISR_INIT 0x7FF
59
60	#ifdef DEBUG_I2C
61	#define PRINTD(x) printf x
62	#else
63	#define PRINTD(x)
64	#endif
65
66
67	/* Shall the current transfer have a start/stop condition? */
68	#define I2C_COND_NORMAL 0
69	#define I2C_COND_START 1
70	#define I2C_COND_STOP 2
71
72	/* Shall the current transfer be ack/nacked or being waited for it? */
73	#define I2C_ACKNAK_WAITACK 1
74	#define I2C_ACKNAK_SENDACK 2
75	#define I2C_ACKNAK_SENDNAK 4
76
77	/* Specify who shall transfer the data (master or slave) */
78	#define I2C_READ 0
79	#define I2C_WRITE 1
80
81	/* All transfers are described by this data structure */
82	struct i2c_msg {
83	u8 condition;
84	u8 acknack;
85	u8 direction;
86	u8 data;
87	};
88
89
90	/**
91	* i2c_pxa_reset: - reset the host controller
92	*
93	*/
94
95	static void i2c_reset( void )
96	{
97	writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
98	writel(readl(ICR) \| ICR_UR, ICR); /* reset the unit */
99	udelay(100);
100	writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
101	#ifdef CONFIG_CPU_MONAHANS
102	/* \| CKENB_1_PWM1 \| CKENB_0_PWM0); */
103	writel(readl(CKENB) \| (CKENB_4_I2C), CKENB);
104	#else /* CONFIG_CPU_MONAHANS */
105	/* set the global I2C clock on */
106	writel(readl(CKEN) \| CKEN14_I2C, CKEN);
107	#endif
108	writel(I2C_PXA_SLAVE_ADDR, ISAR); /* set our slave address */
109	writel(I2C_ICR_INIT, ICR); /* set control reg values */
110	writel(I2C_ISR_INIT, ISR); /* set clear interrupt bits */
111	writel(readl(ICR) \| ICR_IUE, ICR); /* enable unit */
112	udelay(100);
113	}
114
115
116	/**
117	* i2c_isr_set_cleared: - wait until certain bits of the I2C status register
118	* are set and cleared
119	*
120	* @return: 1 in case of success, 0 means timeout (no match within 10 ms).
121	*/
122	static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask )
123	{
124	int timeout = 10000;
125
126	while( ((ISR & set_mask)!=set_mask) \|\| ((ISR & cleared_mask)!=0) ){
127	udelay( 10 );
128	if( timeout-- < 0 ) return 0;
129	}
130
131	return 1;
132	}
133
134
135	/**
136	* i2c_transfer: - Transfer one byte over the i2c bus
137	*
138	* This function can tranfer a byte over the i2c bus in both directions.
139	* It is used by the public API functions.
140	*
141	* @return: 0: transfer successful
142	* -1: message is empty
143	* -2: transmit timeout
144	* -3: ACK missing
145	* -4: receive timeout
146	* -5: illegal parameters
147	* -6: bus is busy and couldn't be aquired
148	*/
149	int i2c_transfer(struct i2c_msg *msg)
150	{
151	int ret;
152
153	if (!msg)
154	goto transfer_error_msg_empty;
155
156	switch(msg->direction) {
157
158	case I2C_WRITE:
159
160	/* check if bus is not busy */
161	if (!i2c_isr_set_cleared(0,ISR_IBB))
162	goto transfer_error_bus_busy;
163
164	/* start transmission */
165	writel(readl(ICR) & ~ICR_START, ICR);
166	writel(readl(ICR) & ~ICR_STOP, ICR);
167	writel(msg->data, IDBR);
168	if (msg->condition == I2C_COND_START)
169	writel(readl(ICR) \| ICR_START, ICR);
170	if (msg->condition == I2C_COND_STOP)
171	writel(readl(ICR) \| ICR_STOP, ICR);
172	if (msg->acknack == I2C_ACKNAK_SENDNAK)
173	writel(readl(ICR) \| ICR_ACKNAK, ICR);
174	if (msg->acknack == I2C_ACKNAK_SENDACK)
175	writel(readl(ICR) & ~ICR_ACKNAK, ICR);
176	writel(readl(ICR) & ~ICR_ALDIE, ICR);
177	writel(readl(ICR) \| ICR_TB, ICR);
178
179	/* transmit register empty? */
180	if (!i2c_isr_set_cleared(ISR_ITE,0))
181	goto transfer_error_transmit_timeout;
182
183	/* clear 'transmit empty' state */
184	writel(readl(ISR) \| ISR_ITE, ISR);
185
186	/* wait for ACK from slave */
187	if (msg->acknack == I2C_ACKNAK_WAITACK)
188	if (!i2c_isr_set_cleared(0,ISR_ACKNAK))
189	goto transfer_error_ack_missing;
190	break;
191
192	case I2C_READ:
193
194	/* check if bus is not busy */
195	if (!i2c_isr_set_cleared(0,ISR_IBB))
196	goto transfer_error_bus_busy;
197
198	/* start receive */
199	writel(readl(ICR) & ~ICR_START, ICR);
200	writel(readl(ICR) & ~ICR_STOP, ICR);
201	if (msg->condition == I2C_COND_START)
202	writel(readl(ICR) \| ICR_START, ICR);
203	if (msg->condition == I2C_COND_STOP)
204	writel(readl(ICR) \| ICR_STOP, ICR);
205	if (msg->acknack == I2C_ACKNAK_SENDNAK)
206	writel(readl(ICR) \| ICR_ACKNAK, ICR);
207	if (msg->acknack == I2C_ACKNAK_SENDACK)
208	writel(readl(ICR) & ~ICR_ACKNAK, ICR);
209	writel(readl(ICR) & ~ICR_ALDIE, ICR);
210	writel(readl(ICR) \| ICR_TB, ICR);
211
212	/* receive register full? */
213	if (!i2c_isr_set_cleared(ISR_IRF,0))
214	goto transfer_error_receive_timeout;
215
216	msg->data = readl(IDBR);
217
218	/* clear 'receive empty' state */
219	writel(readl(ISR) \| ISR_IRF, ISR);
220
221	break;
222
223	default:
224
225	goto transfer_error_illegal_param;
226
227	}
228
229	return 0;
230
231	transfer_error_msg_empty:
232	PRINTD(("i2c_transfer: error: 'msg' is empty\n"));
233	ret = -1; goto i2c_transfer_finish;
234
235	transfer_error_transmit_timeout:
236	PRINTD(("i2c_transfer: error: transmit timeout\n"));
237	ret = -2; goto i2c_transfer_finish;
238
239	transfer_error_ack_missing:
240	PRINTD(("i2c_transfer: error: ACK missing\n"));
241	ret = -3; goto i2c_transfer_finish;
242
243	transfer_error_receive_timeout:
244	PRINTD(("i2c_transfer: error: receive timeout\n"));
245	ret = -4; goto i2c_transfer_finish;
246
247	transfer_error_illegal_param:
248	PRINTD(("i2c_transfer: error: illegal parameters\n"));
249	ret = -5; goto i2c_transfer_finish;
250
251	transfer_error_bus_busy:
252	PRINTD(("i2c_transfer: error: bus is busy\n"));
253	ret = -6; goto i2c_transfer_finish;
254
255	i2c_transfer_finish:
256	PRINTD(("i2c_transfer: ISR: 0x%04x\n",ISR));
257	i2c_reset();
258	return ret;
259
260	}
261
262	/* ------------------------------------------------------------------------ */
263	/* API Functions */
264	/* ------------------------------------------------------------------------ */
265
266	void i2c_init(int speed, int slaveaddr)
267	{
268	#ifdef CONFIG_SYS_I2C_INIT_BOARD
269	/* call board specific i2c bus reset routine before accessing the */
270	/* environment, which might be in a chip on that bus. For details */
271	/* about this problem see doc/I2C_Edge_Conditions. */
272	i2c_init_board();
273	#endif
274	}
275
276
277	/**
278	* i2c_probe: - Test if a chip answers for a given i2c address
279	*
280	* @chip: address of the chip which is searched for
281	* @return: 0 if a chip was found, -1 otherwhise
282	*/
283
284	int i2c_probe(uchar chip)
285	{
286	struct i2c_msg msg;
287
288	i2c_reset();
289
290	msg.condition = I2C_COND_START;
291	msg.acknack = I2C_ACKNAK_WAITACK;
292	msg.direction = I2C_WRITE;
293	msg.data = (chip << 1) + 1;
294	if (i2c_transfer(&msg)) return -1;
295
296	msg.condition = I2C_COND_STOP;
297	msg.acknack = I2C_ACKNAK_SENDNAK;
298	msg.direction = I2C_READ;
299	msg.data = 0x00;
300	if (i2c_transfer(&msg)) return -1;
301
302	return 0;
303	}
304
305
306	/**
307	* i2c_read: - Read multiple bytes from an i2c device
308	*
309	* The higher level routines take into account that this function is only
310	* called with len < page length of the device (see configuration file)
311	*
312	* @chip: address of the chip which is to be read
313	* @addr: i2c data address within the chip
314	* @alen: length of the i2c data address (1..2 bytes)
315	* @buffer: where to write the data
316	* @len: how much byte do we want to read
317	* @return: 0 in case of success
318	*/
319
320	int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
321	{
322	struct i2c_msg msg;
323	u8 addr_bytes[3]; /* lowest...highest byte of data address */
324	int ret;
325
326	PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len));
327
328	i2c_reset();
329
330	/* dummy chip address write */
331	PRINTD(("i2c_read: dummy chip address write\n"));
332	msg.condition = I2C_COND_START;
333	msg.acknack = I2C_ACKNAK_WAITACK;
334	msg.direction = I2C_WRITE;
335	msg.data = (chip << 1);
336	msg.data &= 0xFE;
337	if ((ret=i2c_transfer(&msg))) return -1;
338
339	/*
340	* send memory address bytes;
341	* alen defines how much bytes we have to send.
342	*/
343	/addr &= ((1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)-1); /
344	addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
345	addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
346	addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
347
348	while (--alen >= 0) {
349
350	PRINTD(("i2c_read: send memory word address byte %1d\n",alen));
351	msg.condition = I2C_COND_NORMAL;
352	msg.acknack = I2C_ACKNAK_WAITACK;
353	msg.direction = I2C_WRITE;
354	msg.data = addr_bytes[alen];
355	if ((ret=i2c_transfer(&msg))) return -1;
356	}
357
358
359	/* start read sequence */
360	PRINTD(("i2c_read: start read sequence\n"));
361	msg.condition = I2C_COND_START;
362	msg.acknack = I2C_ACKNAK_WAITACK;
363	msg.direction = I2C_WRITE;
364	msg.data = (chip << 1);
365	msg.data \|= 0x01;
366	if ((ret=i2c_transfer(&msg))) return -1;
367
368	/* read bytes; send NACK at last byte */
369	while (len--) {
370
371	if (len==0) {
372	msg.condition = I2C_COND_STOP;
373	msg.acknack = I2C_ACKNAK_SENDNAK;
374	} else {
375	msg.condition = I2C_COND_NORMAL;
376	msg.acknack = I2C_ACKNAK_SENDACK;
377	}
378
379	msg.direction = I2C_READ;
380	msg.data = 0x00;
381	if ((ret=i2c_transfer(&msg))) return -1;
382
383	*buffer = msg.data;
384	PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer));
385	buffer++;
386
387	}
388
389	i2c_reset();
390
391	return 0;
392	}
393
394
395	/**
396	* i2c_write: - Write multiple bytes to an i2c device
397	*
398	* The higher level routines take into account that this function is only
399	* called with len < page length of the device (see configuration file)
400	*
401	* @chip: address of the chip which is to be written
402	* @addr: i2c data address within the chip
403	* @alen: length of the i2c data address (1..2 bytes)
404	* @buffer: where to find the data to be written
405	* @len: how much byte do we want to read
406	* @return: 0 in case of success
407	*/
408
409	int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
410	{
411	struct i2c_msg msg;
412	u8 addr_bytes[3]; /* lowest...highest byte of data address */
413
414	PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len));
415
416	i2c_reset();
417
418	/* chip address write */
419	PRINTD(("i2c_write: chip address write\n"));
420	msg.condition = I2C_COND_START;
421	msg.acknack = I2C_ACKNAK_WAITACK;
422	msg.direction = I2C_WRITE;
423	msg.data = (chip << 1);
424	msg.data &= 0xFE;
425	if (i2c_transfer(&msg)) return -1;
426
427	/*
428	* send memory address bytes;
429	* alen defines how much bytes we have to send.
430	*/
431	addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
432	addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
433	addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
434
435	while (--alen >= 0) {
436
437	PRINTD(("i2c_write: send memory word address\n"));
438	msg.condition = I2C_COND_NORMAL;
439	msg.acknack = I2C_ACKNAK_WAITACK;
440	msg.direction = I2C_WRITE;
441	msg.data = addr_bytes[alen];
442	if (i2c_transfer(&msg)) return -1;
443	}
444
445	/* write bytes; send NACK at last byte */
446	while (len--) {
447
448	PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer));
449
450	if (len==0)
451	msg.condition = I2C_COND_STOP;
452	else
453	msg.condition = I2C_COND_NORMAL;
454
455	msg.acknack = I2C_ACKNAK_WAITACK;
456	msg.direction = I2C_WRITE;
457	msg.data = *(buffer++);
458
459	if (i2c_transfer(&msg)) return -1;
460
461	}
462
463	i2c_reset();
464
465	return 0;
466
467	}
468
469	#endif /* CONFIG_HARD_I2C */
470		1	/*

drivers/i2c/Makefile

Diff comments View file @ 68432c2

 #
 # (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
 # published by the Free Software Foundation; either version 2 of
 # the License, or (at your option) any later version.
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
 include $(TOPDIR)/config.mk
 LIB	:= $(obj)libi2c.o
 COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
 COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
 COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
 COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
+COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
 COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
 COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
 COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
 COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
 COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
 COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o
 COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
 COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
 COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
 COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o
 COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 all:	$(LIB)
 $(LIB):	$(obj).depend $(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 #########################################################################
 # defines $(obj).depend target
 include $(SRCTREE)/rules.mk
 sinclude $(obj).depend
 #########################################################################

drivers/i2c/mv_i2c.c

Diff comments View file @ 68432c2

File was created	1	/*
	2	* (C) Copyright 2000
	3	* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
	4	*
	5	* (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	6	* Marius Groeger <mgroeger@sysgo.de>
	7	*
	8	* (C) Copyright 2003 Pengutronix e.K.
	9	* Robert Schwebel <r.schwebel@pengutronix.de>
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*
	29	* Back ported to the 8xx platform (from the 8260 platform) by
	30	* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
	31	*/
	32
	33	#include <common.h>
	34	#include <asm/io.h>
	35
	36	#ifdef CONFIG_HARD_I2C
	37
	38	/*
	39	* - CONFIG_SYS_I2C_SPEED
	40	* - I2C_PXA_SLAVE_ADDR
	41	*/
	42
	43	#include <asm/arch/hardware.h>
	44	#include <asm/arch/pxa-regs.h>
	45	#include <i2c.h>
	46
	47	#if (CONFIG_SYS_I2C_SPEED == 400000)
	48	#define I2C_ICR_INIT (ICR_FM \| ICR_BEIE \| ICR_IRFIE \| ICR_ITEIE \| ICR_GCD \
	49	\| ICR_SCLE)
	50	#else
	51	#define I2C_ICR_INIT (ICR_BEIE \| ICR_IRFIE \| ICR_ITEIE \| ICR_GCD \| ICR_SCLE)
	52	#endif
	53
	54	#define I2C_ISR_INIT 0x7FF
	55
	56	#ifdef DEBUG_I2C
	57	#define PRINTD(x) printf x
	58	#else
	59	#define PRINTD(x)
	60	#endif
	61
	62	/* Shall the current transfer have a start/stop condition? */
	63	#define I2C_COND_NORMAL 0
	64	#define I2C_COND_START 1
	65	#define I2C_COND_STOP 2
	66
	67	/* Shall the current transfer be ack/nacked or being waited for it? */
	68	#define I2C_ACKNAK_WAITACK 1
	69	#define I2C_ACKNAK_SENDACK 2
	70	#define I2C_ACKNAK_SENDNAK 4
	71
	72	/* Specify who shall transfer the data (master or slave) */
	73	#define I2C_READ 0
	74	#define I2C_WRITE 1
	75
	76	/* All transfers are described by this data structure */
	77	struct i2c_msg {
	78	u8 condition;
	79	u8 acknack;
	80	u8 direction;
	81	u8 data;
	82	};
	83
	84	/*
	85	* i2c_pxa_reset: - reset the host controller
	86	*
	87	*/
	88	static void i2c_reset(void)
	89	{
	90	writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
	91	writel(readl(ICR) \| ICR_UR, ICR); /* reset the unit */
	92	udelay(100);
	93	writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
	94	#ifdef CONFIG_CPU_MONAHANS
	95	/* \| CKENB_1_PWM1 \| CKENB_0_PWM0); */
	96	writel(readl(CKENB) \| (CKENB_4_I2C), CKENB);
	97	#else /* CONFIG_CPU_MONAHANS */
	98	/* set the global I2C clock on */
	99	writel(readl(CKEN) \| CKEN14_I2C, CKEN);
	100	#endif
	101	writel(I2C_PXA_SLAVE_ADDR, ISAR); /* set our slave address */
	102	writel(I2C_ICR_INIT, ICR); /* set control reg values */
	103	writel(I2C_ISR_INIT, ISR); /* set clear interrupt bits */
	104	writel(readl(ICR) \| ICR_IUE, ICR); /* enable unit */
	105	udelay(100);
	106	}
	107
	108	/*
	109	* i2c_isr_set_cleared: - wait until certain bits of the I2C status register
	110	* are set and cleared
	111	*
	112	* @return: 1 in case of success, 0 means timeout (no match within 10 ms).
	113	*/
	114	static int i2c_isr_set_cleared(unsigned long set_mask,
	115	unsigned long cleared_mask)
	116	{
	117	int timeout = 10000;
	118
	119	while (((ISR & set_mask) != set_mask) \|\| ((ISR & cleared_mask) != 0)) {
	120	udelay(10);
	121	if (timeout-- < 0)
	122	return 0;
	123	}
	124
	125	return 1;
	126	}
	127
	128	/*
	129	* i2c_transfer: - Transfer one byte over the i2c bus
	130	*
	131	* This function can tranfer a byte over the i2c bus in both directions.
	132	* It is used by the public API functions.
	133	*
	134	* @return: 0: transfer successful
	135	* -1: message is empty
	136	* -2: transmit timeout
	137	* -3: ACK missing
	138	* -4: receive timeout
	139	* -5: illegal parameters
	140	* -6: bus is busy and couldn't be aquired
	141	*/
	142	int i2c_transfer(struct i2c_msg *msg)
	143	{
	144	int ret;
	145
	146	if (!msg)
	147	goto transfer_error_msg_empty;
	148
	149	switch (msg->direction) {
	150	case I2C_WRITE:
	151	/* check if bus is not busy */
	152	if (!i2c_isr_set_cleared(0, ISR_IBB))
	153	goto transfer_error_bus_busy;
	154
	155	/* start transmission */
	156	writel(readl(ICR) & ~ICR_START, ICR);
	157	writel(readl(ICR) & ~ICR_STOP, ICR);
	158	writel(msg->data, IDBR);
	159	if (msg->condition == I2C_COND_START)
	160	writel(readl(ICR) \| ICR_START, ICR);
	161	if (msg->condition == I2C_COND_STOP)
	162	writel(readl(ICR) \| ICR_STOP, ICR);
	163	if (msg->acknack == I2C_ACKNAK_SENDNAK)
	164	writel(readl(ICR) \| ICR_ACKNAK, ICR);
	165	if (msg->acknack == I2C_ACKNAK_SENDACK)
	166	writel(readl(ICR) & ~ICR_ACKNAK, ICR);
	167	writel(readl(ICR) & ~ICR_ALDIE, ICR);
	168	writel(readl(ICR) \| ICR_TB, ICR);
	169
	170	/* transmit register empty? */
	171	if (!i2c_isr_set_cleared(ISR_ITE, 0))
	172	goto transfer_error_transmit_timeout;
	173
	174	/* clear 'transmit empty' state */
	175	writel(readl(ISR) \| ISR_ITE, ISR);
	176
	177	/* wait for ACK from slave */
	178	if (msg->acknack == I2C_ACKNAK_WAITACK)
	179	if (!i2c_isr_set_cleared(0, ISR_ACKNAK))
	180	goto transfer_error_ack_missing;
	181	break;
	182
	183	case I2C_READ:
	184
	185	/* check if bus is not busy */
	186	if (!i2c_isr_set_cleared(0, ISR_IBB))
	187	goto transfer_error_bus_busy;
	188
	189	/* start receive */
	190	writel(readl(ICR) & ~ICR_START, ICR);
	191	writel(readl(ICR) & ~ICR_STOP, ICR);
	192	if (msg->condition == I2C_COND_START)
	193	writel(readl(ICR) \| ICR_START, ICR);
	194	if (msg->condition == I2C_COND_STOP)
	195	writel(readl(ICR) \| ICR_STOP, ICR);
	196	if (msg->acknack == I2C_ACKNAK_SENDNAK)
	197	writel(readl(ICR) \| ICR_ACKNAK, ICR);
	198	if (msg->acknack == I2C_ACKNAK_SENDACK)
	199	writel(readl(ICR) & ~ICR_ACKNAK, ICR);
	200	writel(readl(ICR) & ~ICR_ALDIE, ICR);
	201	writel(readl(ICR) \| ICR_TB, ICR);
	202
	203	/* receive register full? */
	204	if (!i2c_isr_set_cleared(ISR_IRF, 0))
	205	goto transfer_error_receive_timeout;
	206
	207	msg->data = readl(IDBR);
	208
	209	/* clear 'receive empty' state */
	210	writel(readl(ISR) \| ISR_IRF, ISR);
	211
	212	break;
	213	default:
	214	goto transfer_error_illegal_param;
	215	}
	216
	217	return 0;
	218
	219	transfer_error_msg_empty:
	220	PRINTD(("i2c_transfer: error: 'msg' is empty\n"));
	221	ret = -1; goto i2c_transfer_finish;
	222
	223	transfer_error_transmit_timeout:
	224	PRINTD(("i2c_transfer: error: transmit timeout\n"));
	225	ret = -2; goto i2c_transfer_finish;
	226
	227	transfer_error_ack_missing:
	228	PRINTD(("i2c_transfer: error: ACK missing\n"));
	229	ret = -3; goto i2c_transfer_finish;
	230
	231	transfer_error_receive_timeout:
	232	PRINTD(("i2c_transfer: error: receive timeout\n"));
	233	ret = -4; goto i2c_transfer_finish;
	234
	235	transfer_error_illegal_param:
	236	PRINTD(("i2c_transfer: error: illegal parameters\n"));
	237	ret = -5; goto i2c_transfer_finish;
	238
	239	transfer_error_bus_busy:
	240	PRINTD(("i2c_transfer: error: bus is busy\n"));
	241	ret = -6; goto i2c_transfer_finish;
	242
	243	i2c_transfer_finish:
	244	PRINTD(("i2c_transfer: ISR: 0x%04x\n", ISR));
	245	i2c_reset();
	246	return ret;
	247	}
	248
	249	/* ------------------------------------------------------------------------ */
	250	/* API Functions */
	251	/* ------------------------------------------------------------------------ */
	252	void i2c_init(int speed, int slaveaddr)
	253	{
	254	#ifdef CONFIG_SYS_I2C_INIT_BOARD
	255	/* call board specific i2c bus reset routine before accessing the */
	256	/* environment, which might be in a chip on that bus. For details */
	257	/* about this problem see doc/I2C_Edge_Conditions. */
	258	i2c_init_board();
	259	#endif
	260	}
	261
	262	/*
	263	* i2c_probe: - Test if a chip answers for a given i2c address
	264	*
	265	* @chip: address of the chip which is searched for
	266	* @return: 0 if a chip was found, -1 otherwhise
	267	*/
	268	int i2c_probe(uchar chip)
	269	{
	270	struct i2c_msg msg;
	271
	272	i2c_reset();
	273
	274	msg.condition = I2C_COND_START;
	275	msg.acknack = I2C_ACKNAK_WAITACK;
	276	msg.direction = I2C_WRITE;
	277	msg.data = (chip << 1) + 1;
	278	if (i2c_transfer(&msg))
	279	return -1;
	280
	281	msg.condition = I2C_COND_STOP;
	282	msg.acknack = I2C_ACKNAK_SENDNAK;
	283	msg.direction = I2C_READ;
	284	msg.data = 0x00;
	285	if (i2c_transfer(&msg))
	286	return -1;
	287
	288	return 0;
	289	}
	290
	291	/*
	292	* i2c_read: - Read multiple bytes from an i2c device
	293	*
	294	* The higher level routines take into account that this function is only
	295	* called with len < page length of the device (see configuration file)
	296	*
	297	* @chip: address of the chip which is to be read
	298	* @addr: i2c data address within the chip
	299	* @alen: length of the i2c data address (1..2 bytes)
	300	* @buffer: where to write the data
	301	* @len: how much byte do we want to read
	302	* @return: 0 in case of success
	303	*/
	304	int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
	305	{
	306	struct i2c_msg msg;
	307	u8 addr_bytes[3]; /* lowest...highest byte of data address */
	308
	309	PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
	310	"len=0x%02x)\n", chip, addr, alen, len));
	311
	312	i2c_reset();
	313
	314	/* dummy chip address write */
	315	PRINTD(("i2c_read: dummy chip address write\n"));
	316	msg.condition = I2C_COND_START;
	317	msg.acknack = I2C_ACKNAK_WAITACK;
	318	msg.direction = I2C_WRITE;
	319	msg.data = (chip << 1);
	320	msg.data &= 0xFE;
	321	if (i2c_transfer(&msg))
	322	return -1;
	323
	324	/*
	325	* send memory address bytes;
	326	* alen defines how much bytes we have to send.
	327	*/
	328	/addr &= ((1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)-1); /
	329	addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
	330	addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
	331	addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
	332
	333	while (--alen >= 0) {
	334	PRINTD(("i2c_read: send memory word address byte %1d\n", alen));
	335	msg.condition = I2C_COND_NORMAL;
	336	msg.acknack = I2C_ACKNAK_WAITACK;
	337	msg.direction = I2C_WRITE;
	338	msg.data = addr_bytes[alen];
	339	if (i2c_transfer(&msg))
	340	return -1;
	341	}
	342
	343	/* start read sequence */
	344	PRINTD(("i2c_read: start read sequence\n"));
	345	msg.condition = I2C_COND_START;
	346	msg.acknack = I2C_ACKNAK_WAITACK;
	347	msg.direction = I2C_WRITE;
	348	msg.data = (chip << 1);
	349	msg.data \|= 0x01;
	350	if (i2c_transfer(&msg))
	351	return -1;
	352
	353	/* read bytes; send NACK at last byte */
	354	while (len--) {
	355	if (len == 0) {
	356	msg.condition = I2C_COND_STOP;
	357	msg.acknack = I2C_ACKNAK_SENDNAK;
	358	} else {
	359	msg.condition = I2C_COND_NORMAL;
	360	msg.acknack = I2C_ACKNAK_SENDACK;
	361	}
	362
	363	msg.direction = I2C_READ;
	364	msg.data = 0x00;
	365	if (i2c_transfer(&msg))
	366	return -1;
	367
	368	*buffer = msg.data;
	369	PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",
	370	(unsigned int)buffer, *buffer));
	371	buffer++;
	372	}
	373
	374	i2c_reset();
	375
	376	return 0;
	377	}
	378
	379	/*
	380	* i2c_write: - Write multiple bytes to an i2c device
	381	*
	382	* The higher level routines take into account that this function is only
	383	* called with len < page length of the device (see configuration file)
	384	*
	385	* @chip: address of the chip which is to be written
	386	* @addr: i2c data address within the chip
	387	* @alen: length of the i2c data address (1..2 bytes)
	388	* @buffer: where to find the data to be written
	389	* @len: how much byte do we want to read
	390	* @return: 0 in case of success
	391	*/
	392	int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
	393	{
	394	struct i2c_msg msg;
	395	u8 addr_bytes[3]; /* lowest...highest byte of data address */
	396
	397	PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
	398	"len=0x%02x)\n", chip, addr, alen, len));
	399
	400	i2c_reset();
	401
	402	/* chip address write */
	403	PRINTD(("i2c_write: chip address write\n"));
	404	msg.condition = I2C_COND_START;
	405	msg.acknack = I2C_ACKNAK_WAITACK;
	406	msg.direction = I2C_WRITE;
	407	msg.data = (chip << 1);
	408	msg.data &= 0xFE;
	409	if (i2c_transfer(&msg))
	410	return -1;
	411
	412	/*
	413	* send memory address bytes;
	414	* alen defines how much bytes we have to send.
	415	*/
	416	addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
	417	addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
	418	addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
	419
	420	while (--alen >= 0) {
	421	PRINTD(("i2c_write: send memory word address\n"));
	422	msg.condition = I2C_COND_NORMAL;
	423	msg.acknack = I2C_ACKNAK_WAITACK;
	424	msg.direction = I2C_WRITE;
	425	msg.data = addr_bytes[alen];
	426	if (i2c_transfer(&msg))
	427	return -1;
	428	}
	429
	430	/* write bytes; send NACK at last byte */
	431	while (len--) {
	432	PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",
	433	(unsigned int)buffer, *buffer));
	434
	435	if (len == 0)
	436	msg.condition = I2C_COND_STOP;
	437	else
	438	msg.condition = I2C_COND_NORMAL;
	439
	440	msg.acknack = I2C_ACKNAK_WAITACK;
	441	msg.direction = I2C_WRITE;
	442	msg.data = *(buffer++);
	443
	444	if (i2c_transfer(&msg))
	445	return -1;
	446	}
	447
	448	i2c_reset();
	449
	450	return 0;
	451	}
	452	#endif /* CONFIG_HARD_I2C */
	453

include/configs/innokom.h

Diff comments View file @ 68432c2

 /*
  * (C) Copyright 2000, 2001, 2002
  * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
  *
  * Configuration for the Auerswald Innokom CPU board.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  * include/configs/innokom.h - configuration options, board specific
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  * (easy to change)
  */
 #define CONFIG_PXA250		1	/* This is an PXA250 CPU            */
 #define CONFIG_INNOKOM		1	/* on an Auerswald Innokom board    */
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
 					/* for timer/console/ethernet       */
 #define	CONFIG_SYS_TEXT_BASE	0x0
 /* we will never enable dcache, because we have to setup MMU first */
 #define CONFIG_SYS_NO_DCACHE
 /*
  * Hardware drivers
  */
 /*
  * select serial console configuration
  */
 #define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART		1	/* we use FFUART on CSB226 */
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_BAUDRATE		19200
 #define CONFIG_MISC_INIT_R	1	/* we have a misc_init_r() function */
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ECHO
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_RUN
 #define CONFIG_BOOTDELAY	3
 /* #define CONFIG_BOOTARGS	"root=/dev/nfs ip=bootp console=ttyS0,19200" */
 #define CONFIG_BOOTARGS		"console=ttyS0,19200"
 #define CONFIG_ETHADDR		FF:FF:FF:FF:FF:FF
 #define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_IPADDR		192.168.1.56
 #define CONFIG_SERVERIP		192.168.1.2
 #define CONFIG_BOOTCOMMAND	"bootm 0x40000"
 #define CONFIG_SHOW_BOOT_PROGRESS
 #define CONFIG_CMDLINE_TAG	1
 /*
  * Miscellaneous configurable options
  */
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(256*1024)
 #define CONFIG_SYS_LONGHELP				/* undef to save memory         */
 #define CONFIG_SYS_PROMPT		"uboot> "	/* Monitor Command Prompt       */
 #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size      */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS		16		/* max number of command args   */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 #define CONFIG_SYS_MEMTEST_START	0xa0400000      /* memtest works on     */
 #define CONFIG_SYS_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
 #define CONFIG_SYS_LOAD_ADDR           0xa3000000      /* load kernel to this address   */
 #define CONFIG_SYS_HZ			1000
 						/* RS: the oscillator is actually 3680130?? */
 #define CONFIG_SYS_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
 						/* 0101000001 */
 						/*      ^^^^^ Memory Speed 99.53 MHz         */
 						/*    ^^      Run Mode Speed = 2x Mem Speed  */
 						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
 #define CONFIG_SYS_MONITOR_LEN		0x20000		/* 128 KiB */
 						/* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 /*
  * I2C bus
  */
+#define CONFIG_I2C_MV			1
 #define CONFIG_HARD_I2C			1
 #define CONFIG_SYS_I2C_SPEED			50000
 #define CONFIG_SYS_I2C_SLAVE			0xfe
 #define CONFIG_ENV_IS_IN_EEPROM		1
 #define CONFIG_ENV_OFFSET			0x00	/* environment starts here  */
 #define CONFIG_ENV_SIZE			1024	/* 1 KiB                    */
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* A0 = 0 (hardwired)       */
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets       */
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	15	/* between stop and start   */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* length of address        */
 #define CONFIG_SYS_EEPROM_SIZE			4096	/* size in bytes            */
 #define CONFIG_SYS_I2C_INIT_BOARD		1	/* board has it's own init  */
 /*
  * SMSC91C111 Network Card
  */
 #define CONFIG_NET_MULTI
 #define CONFIG_SMC91111		1
 #define CONFIG_SMC91111_BASE		0x14000000 /* chip select 5         */
 #undef  CONFIG_SMC_USE_32_BIT		           /* 16 bit bus access     */
 #undef  CONFIG_SMC_91111_EXT_PHY		   /* we use internal phy   */
 #define CONFIG_SMC_AUTONEG_TIMEOUT	10	   /* timeout 10 seconds    */
 #undef  CONFIG_SHOW_ACTIVITY
 #define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */
 /*
  * Stack sizes
  *
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 #ifdef  CONFIG_USE_IRQ
 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 #endif
 /*
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM   */
 #define PHYS_SDRAM_1		0xa0000000	/* SDRAM Bank #1            */
 #define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB                    */
 #define PHYS_FLASH_1		0x00000000	/* Flash Bank #1            */
 #define PHYS_FLASH_SIZE		0x01000000	/* 16 MB                    */
 #define CONFIG_SYS_DRAM_BASE		0xa0000000	/* RAM starts here          */
 #define CONFIG_SYS_DRAM_SIZE		0x04000000
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 /*
  * JFFS2 partitions
  *
  */
 /* development flash */
 #define CONFIG_MTD_INNOKOM_16MB	1
 #undef CONFIG_MTD_INNOKOM_64MB
 /* production flash */
 /*
 #define CONFIG_MTD_INNOKOM_64MB	1
 #undef CONFIG_MTD_INNOKOM_16MB
 */
 /* No command line, one static partition, whole device */
 #undef CONFIG_CMD_MTDPARTS
 #define CONFIG_JFFS2_DEV		"nor0"
 #define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
 #define CONFIG_JFFS2_PART_OFFSET	0x00000000
 /* mtdparts command line support */
 /* Note: fake mtd_id used, no linux mtd map file */
 /*
 #define CONFIG_CMD_MTDPARTS
 #define MTDIDS_DEFAULT		"nor0=innokom-0"
 */
 /* development flash */
 /*
 #define MTDPARTS_DEFAULT	"mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
 */
 /* production flash */
 /*
 #define MTDPARTS_DEFAULT	"mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
 */
 /*
  * GPIO settings
  *
  * GP15 == nCS1      is 1
  * GP24 == SFRM      is 1
  * GP25 == TXD       is 1
  * GP33 == nCS5      is 1
  * GP39 == FFTXD     is 1
  * GP41 == RTS       is 1
  * GP47 == TXD       is 1
  * GP49 == nPWE      is 1
  * GP62 == LED_B     is 1
  * GP63 == TDM_OE    is 1
  * GP78 == nCS2      is 1
  * GP79 == nCS3      is 1
  * GP80 == nCS4      is 1
  */
 #define CONFIG_SYS_GPSR0_VAL       0x03008000
 #define CONFIG_SYS_GPSR1_VAL       0xC0028282
 #define CONFIG_SYS_GPSR2_VAL       0x0001C000
 /* GP02 == DON_RST   is 0
  * GP23 == SCLK      is 0
  * GP45 == USB_ACT   is 0
  * GP60 == PLLEN     is 0
  * GP61 == LED_A     is 0
  * GP73 == SWUPD_LED is 0
  */
 #define CONFIG_SYS_GPCR0_VAL       0x00800004
 #define CONFIG_SYS_GPCR1_VAL       0x30002000
 #define CONFIG_SYS_GPCR2_VAL       0x00000100
 /* GP00 == DON_READY is input
  * GP01 == DON_OK    is input
  * GP02 == DON_RST   is output
  * GP03 == RESET_IND is input
  * GP07 == RES11     is input
  * GP09 == RES12     is input
  * GP11 == SWUPDATE  is input
  * GP14 == nPOWEROK  is input
  * GP15 == nCS1      is output
  * GP17 == RES22     is input
  * GP18 == RDY       is input
  * GP23 == SCLK      is output
  * GP24 == SFRM      is output
  * GP25 == TXD       is output
  * GP26 == RXD       is input
  * GP32 == RES21     is input
  * GP33 == nCS5      is output
  * GP34 == FFRXD     is input
  * GP35 == CTS       is input
  * GP39 == FFTXD     is output
  * GP41 == RTS       is output
  * GP42 == USB_OK    is input
  * GP45 == USB_ACT   is output
  * GP46 == RXD       is input
  * GP47 == TXD       is output
  * GP49 == nPWE      is output
  * GP58 == nCPUBUSINT is input
  * GP59 == LANINT    is input
  * GP60 == PLLEN     is output
  * GP61 == LED_A     is output
  * GP62 == LED_B     is output
  * GP63 == TDM_OE    is output
  * GP64 == nDSPINT   is input
  * GP65 == STRAP0    is input
  * GP67 == STRAP1    is input
  * GP69 == STRAP2    is input
  * GP70 == STRAP3    is input
  * GP71 == STRAP4    is input
  * GP73 == SWUPD_LED is output
  * GP78 == nCS2      is output
  * GP79 == nCS3      is output
  * GP80 == nCS4      is output
  */
 #define CONFIG_SYS_GPDR0_VAL       0x03808004
 #define CONFIG_SYS_GPDR1_VAL       0xF002A282
 #define CONFIG_SYS_GPDR2_VAL       0x0001C200
 /* GP15 == nCS1  is AF10
  * GP18 == RDY   is AF01
  * GP23 == SCLK  is AF10
  * GP24 == SFRM  is AF10
  * GP25 == TXD   is AF10
  * GP26 == RXD   is AF01
  * GP33 == nCS5  is AF10
  * GP34 == FFRXD is AF01
  * GP35 == CTS   is AF01
  * GP39 == FFTXD is AF10
  * GP41 == RTS   is AF10
  * GP46 == RXD   is AF10
  * GP47 == TXD   is AF01
  * GP49 == nPWE  is AF10
  * GP78 == nCS2  is AF10
  * GP79 == nCS3  is AF10
  * GP80 == nCS4  is AF10
  */
 #define CONFIG_SYS_GAFR0_L_VAL     0x80000000
 #define CONFIG_SYS_GAFR0_U_VAL     0x001A8010
 #define CONFIG_SYS_GAFR1_L_VAL     0x60088058
 #define CONFIG_SYS_GAFR1_U_VAL     0x00000008
 #define CONFIG_SYS_GAFR2_L_VAL     0xA0000000
 #define CONFIG_SYS_GAFR2_U_VAL     0x00000002
 /* FIXME: set GPIO_RER/FER */
 /* RDH = 1
  * PH  = 1
  * VFS = 1
  * BFS = 1
  * SSS = 1
  */
 #define CONFIG_SYS_PSSR_VAL		0x37
 #define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
 #define	CONFIG_SYS_CKEN			0x0
 /*
  * Memory settings
  *
  * This is the configuration for nCS0/1 -> flash banks
  * configuration for nCS1:
  * [31]    0    - Slower Device
  * [30:28] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
  * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
  * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
  * [19]    1    - 16 Bit bus width
  * [18:16] 000  - nonburst RAM or FLASH
  * configuration for nCS0:
  * [15]    0    - Slower Device
  * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
  * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
  * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
  * [03]    1    - 16 Bit bus width
  * [02:00] 000  - nonburst RAM or FLASH
  */
 #define CONFIG_SYS_MSC0_VAL		0x25b825b8 /* flash banks                   */
 /* This is the configuration for nCS2/3 -> TDM-Switch, DSP
  * configuration for nCS3: DSP
  * [31]    0    - Slower Device
  * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
  * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
  * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
  * [19]    1    - 16 Bit bus width
  * [18:16] 100  - variable latency I/O
  * configuration for nCS2: TDM-Switch
  * [15]    0    - Slower Device
  * [14:12] 101  - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
  * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
  * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
  * [03]    1    - 16 Bit bus width
  * [02:00] 100  - variable latency I/O
  */
 #define CONFIG_SYS_MSC1_VAL		0x123C593C /* TDM switch, DSP               */
 /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
  *
  * configuration for nCS5: LAN Controller
  * [31]    0    - Slower Device
  * [30:28] 001  - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
  * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
  * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
  * [19]    1    - 16 Bit bus width
  * [18:16] 100  - variable latency I/O
  * configuration for nCS4: ExtBus
  * [15]    0    - Slower Device
  * [14:12] 110  - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
  * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
  * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
  * [03]    1    - 16 Bit bus width
  * [02:00] 100  - variable latency I/O
  */
 #define CONFIG_SYS_MSC2_VAL		0x123C6CDC /* extra bus, LAN controller     */
 /* MDCNFG: SDRAM Configuration Register
  *
  * [31:29]   000 - reserved
  * [28]      0	 - no SA1111 compatiblity mode
  * [27]      0   - latch return data with return clock
  * [26]      0   - alternate addressing for pair 2/3
  * [25:24]   00  - timings
  * [23]      0   - internal banks in lower partition 2/3 (not used)
  * [22:21]   00  - row address bits for partition 2/3 (not used)
  * [20:19]   00  - column address bits for partition 2/3 (not used)
  * [18]      0   - SDRAM partition 2/3 width is 32 bit
  * [17]      0   - SDRAM partition 3 disabled
  * [16]      0   - SDRAM partition 2 disabled
  * [15:13]   000 - reserved
  * [12]      1	 - SA1111 compatiblity mode
  * [11]      1   - latch return data with return clock
  * [10]      0   - no alternate addressing for pair 0/1
  * [09:08]   01  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
  * [7]       1   - 4 internal banks in lower partition pair
  * [06:05]   10  - 13 row address bits for partition 0/1
  * [04:03]   01  - 9 column address bits for partition 0/1
  * [02]      0   - SDRAM partition 0/1 width is 32 bit
  * [01]      0   - disable SDRAM partition 1
  * [00]      1   - enable  SDRAM partition 0
  */
 /* use the configuration above but disable partition 0 */
 #define CONFIG_SYS_MDCNFG_VAL		0x000019c8
 /* MDREFR: SDRAM Refresh Control Register
  *
  * [32:26] 0     - reserved
  * [25]    0     - K2FREE: not free running
  * [24]    0     - K1FREE: not free running
  * [23]    1     - K0FREE: not free running
  * [22]    0     - SLFRSH: self refresh disabled
  * [21]    0     - reserved
  * [20]    0     - APD: no auto power down
  * [19]    0     - K2DB2: SDCLK2 is MemClk
  * [18]    0     - K2RUN: disable SDCLK2
  * [17]    0     - K1DB2: SDCLK1 is MemClk
  * [16]    1     - K1RUN: enable SDCLK1
  * [15]    1     - E1PIN: SDRAM clock enable
  * [14]    1     - K0DB2: SDCLK0 is MemClk
  * [13]    0     - K0RUN: disable SDCLK0
  * [12]    1     - E0PIN: disable SDCKE0
  * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
  */
 #define CONFIG_SYS_MDREFR_VAL		0x0081D018
 /* MDMRS: Mode Register Set Configuration Register
  *
  * [31]      0       - reserved
  * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
  * [22:20]   000     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
  * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
  * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
  * [15]      0       - reserved
  * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
  * [06:04]   010     - MDCL0:  SDRAM0/1 Cas Latency.
  * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
  * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
  */
 #define CONFIG_SYS_MDMRS_VAL		0x00020022
 /*
  * PCMCIA and CF Interfaces
  */
 #define CONFIG_SYS_MECR_VAL		0x00000000
 #define CONFIG_SYS_MCMEM0_VAL		0x00000000
 #define CONFIG_SYS_MCMEM1_VAL		0x00000000
 #define CONFIG_SYS_MCATT0_VAL		0x00000000
 #define CONFIG_SYS_MCATT1_VAL		0x00000000
 #define CONFIG_SYS_MCIO0_VAL		0x00000000
 #define CONFIG_SYS_MCIO1_VAL		0x00000000
 #define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
 #define	CONFIG_SYS_SXCNFG_VAL		0x00000000
 /*
 #define CSB226_USER_LED0	0x00000008
 #define CSB226_USER_LED1	0x00000010
 #define CSB226_USER_LED2	0x00000020
 */
 /*
  * FLASH and environment organization
  */
 #define CONFIG_SYS_MAX_FLASH_BANKS     1	/* max number of memory banks       */
 #define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sect. on one chip  */
 /* timeout values are in ticks */
 #define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase       */
 #define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Write       */
 #endif  /* __CONFIG_H */

include/configs/xm250.h

Diff comments View file @ 68432c2

 /*
  * (C) Copyright 2002
  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  *
  * (C) Copyright 2002
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Marius Groeger <mgroeger@sysgo.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  * (easy to change)
  */
 #define CONFIG_PXA250	       1	/* This is an PXA250 CPU	*/
 #define CONFIG_XM250	       1	/* on a MicroSys XM250 Board	*/
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 #define	CONFIG_SYS_TEXT_BASE	0x0
 /* we will never enable dcache, because we have to setup MMU first */
 #define CONFIG_SYS_NO_DCACHE
 /*
  * Size of malloc() pool; this lives below the uppermost 128 KiB which are
  * used for the RAM copy of the uboot code
  *
  */
 #define CONFIG_SYS_MALLOC_LEN		(256*1024)
 /*
  * Hardware drivers
  */
 #define CONFIG_NET_MULTI
 #define CONFIG_SMC91111
 #define CONFIG_SMC91111_BASE		0x04000300
 #undef	CONFIG_SMC91111_EXT_PHY
 #define CONFIG_SMC_USE_32_BIT
 #undef	CONFIG_SHOW_ACTIVITY
 #define CONFIG_NET_RETRY_COUNT		10	   /* # of retries		*/
 /*
  * I2C bus
  */
+#define CONFIG_I2C_MV			1
 #define CONFIG_HARD_I2C			1
 #define CONFIG_SYS_I2C_SPEED			50000
 #define CONFIG_SYS_I2C_SLAVE			0xfe
 #define CONFIG_RTC_PCF8563		1
 #define CONFIG_SYS_I2C_RTC_ADDR		0x51
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x58	/* A0 = 0 (hardwired)		*/
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 4 bits = 16 octets		*/
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* between stop and start	*/
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* length of address		*/
 #define CONFIG_SYS_EEPROM_SIZE			2048	/* size in bytes		*/
 #undef	CONFIG_SYS_I2C_INIT_BOARD			/* board has no own init	*/
 /*
  * select serial console configuration
  */
 #define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART	       1       /* we use FFUART */
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_BAUDRATE		115200
 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_I2C
 #define CONFIG_BOOTDELAY	3
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
 #define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
 #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on		*/
 #define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM		*/
 #define CONFIG_SYS_LOAD_ADDR		0xa3000000	/* default load address */
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CPUSPEED		0x161		/* set core clock to 400/400/100 MHz */
 						/* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 /*
  * Definitions related to passing arguments to kernel.
  */
 #define CONFIG_CMDLINE_TAG	 1	 /* send commandline to Kernel		*/
 #define CONFIG_SETUP_MEMORY_TAGS 1	 /* send memory definition to kernel	*/
 #define	CONFIG_INITRD_TAG	 1	 /* do not send initrd params		*/
 #undef	CONFIG_VFD			 /* do not send framebuffer setup	*/
 /*
  * Stack sizes
  *
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
 #ifdef CONFIG_USE_IRQ
 #define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
 #define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
 #endif
 /*
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS	4
 #define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1	*/
 #define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB		*/
 #define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2	*/
 #define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB		*/
 #define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3	*/
 #define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB		*/
 #define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4	*/
 #define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB		*/
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1	*/
 #define PHYS_FLASH_2		0x04000000 /* Flash Bank #1	*/
 #define PHYS_FLASH_SIZE		0x01000000 /* 16 MB		*/
 #define PHYS_FLASH_BANK_SIZE	0x01000000 /* 16 MB Banks	*/
 #define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
 #define CONFIG_SYS_DRAM_BASE		0xa0000000
 #define CONFIG_SYS_DRAM_SIZE		0x04000000
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 /*
  * FLASH and environment organization
  */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1     /* max number of memory banks		*/
 #define CONFIG_SYS_MAX_FLASH_SECT	128   /* max number of sectors on one chip	*/
 /* timeout values are in ticks */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Erase	*/
 #define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Write	*/
 #define CONFIG_SYS_FLASH_LOCK_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Set Lock Bit */
 #define CONFIG_SYS_FLASH_UNLOCK_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Clear Lock Bits */
 #define CONFIG_SYS_FLASH_PROTECTION			/* "Real" (hardware) sectors protection */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)	/* Addr of Environment Sector	*/
 #define CONFIG_ENV_SIZE		0x4000
 #define CONFIG_ENV_SECT_SIZE	0x40000				/* Size of the Environment Sector	*/
 #define CONFIG_SYS_MONITOR_LEN		0x20000				/* 128 KiB */
 /******************************************************************************
  *
  * CPU specific defines
  *
  ******************************************************************************/
 /*
  * GPIO settings
  *
  * GPIO pin assignments
  * GPIO	    Name	Dir Out AF
  * 0	    NC
  * 1	    NC
  * 2	    SIRQ1	I
  * 3	    SIRQ2	I
  * 4	    SIRQ3	I
  * 5	    DMAACK1	O   0
  * 6	    DMAACK2	O   0
  * 7	    DMAACK3	O   0
  * 8	    TC1		O   0
  * 9	    TC2		O   0
  * 10	    TC3		O   0
  * 11	    nDMAEN	O   1
  * 12	    AENCTRL	O   0
  * 13	    PLDTC	O   0
  * 14	    ETHIRQ	I
  * 15	    NC
  * 16	    NC
  * 17	    NC
  * 18	    RDY		I
  * 19	    DMASIO	I
  * 20	    ETHIRQ	NC
  * 21	    NC
  * 22	    PGMEN	O   1	 FIXME for debug only enable flash
  * 23	    NC
  * 24	    NC
  * 25	    NC
  * 26	    NC
  * 27	    NC
  * 28	    NC
  * 29	    NC
  * 30	    NC
  * 31	    NC
  * 32	    NC
  * 33	    NC
  * 34	    FFRXD	I	01
  * 35	    FFCTS	I	01
  * 36	    FFDCD	I	01
  * 37	    FFDSR	I	01
  * 38	    FFRI	I	01
  * 39	    FFTXD	O   1	10
  * 40	    FFDTR	O   0	10
  * 41	    FFRTS	O   0	10
  * 42	    RS232FOFF	O   0	00
  * 43	    NC
  * 44	    NC
  * 45	    IRSL0	O   0
  * 46	    IRRX0	I	01
  * 47	    IRTX0	O   0	10
  * 48	    NC
  * 49	    nIOWE	O   0
  * 50	    NC
  * 51	    NC
  * 52	    NC
  * 53	    NC
  * 54	    NC
  * 55	    NC
  * 56	    NC
  * 57	    NC
  * 58	    DKDIRQ	I
  * 59	    NC
  * 60	    NC
  * 61	    NC
  * 62	    NC
  * 63	    NC
  * 64	    COMLED	O   0
  * 65	    COMLED	O   0
  * 66	    COMLED	O   0
  * 67	    COMLED	O   0
  * 68	    COMLED	O   0
  * 69	    COMLED	O   0
  * 70	    COMLED	O   0
  * 71	    COMLED	O   0
  * 72	    NC
  * 73	    NC
  * 74	    NC
  * 75	    NC
  * 76	    NC
  * 77	    NC
  * 78	    CSIO	O   1
  * 79	    NC
  * 80	    CSETH	O   1
  *
  * NOTE: All NC's are defined to be outputs
  *
  */
 /* Pin direction control */
 #define CONFIG_SYS_GPDR0_VAL	    0xd3808000
 #define CONFIG_SYS_GPDR1_VAL	    0xfcffab83
 #define CONFIG_SYS_GPDR2_VAL	    0x0001ffff
 /* Set and Clear registers */
 #define CONFIG_SYS_GPSR0_VAL	    0x00008000
 #define CONFIG_SYS_GPSR1_VAL	    0x00ff0002
 #define CONFIG_SYS_GPSR2_VAL	    0x0001c000
 #define CONFIG_SYS_GPCR0_VAL	    0x00000000
 #define CONFIG_SYS_GPCR1_VAL	    0x00000000
 #define CONFIG_SYS_GPCR2_VAL	    0x00000000
 /* Edge detect registers (these are set by the kernel) */
 #define CONFIG_SYS_GRER0_VAL	    0x00002180
 #define CONFIG_SYS_GRER1_VAL	    0x00000000
 #define CONFIG_SYS_GRER2_VAL	    0x00000000
 #define CONFIG_SYS_GFER0_VAL	    0x000043e0
 #define CONFIG_SYS_GFER1_VAL	    0x00000000
 #define CONFIG_SYS_GFER2_VAL	    0x00000000
 /* Alternate function registers */
 #define CONFIG_SYS_GAFR0_L_VAL	    0x80000004
 #define CONFIG_SYS_GAFR0_U_VAL	    0x595a8010
 #define CONFIG_SYS_GAFR1_L_VAL	    0x699a9559
 #define CONFIG_SYS_GAFR1_U_VAL	    0xaaa5aaaa
 #define CONFIG_SYS_GAFR2_L_VAL	    0xaaaaaaaa
 #define CONFIG_SYS_GAFR2_U_VAL	    0x00000002
 /*
  * Clocks, power control and interrupts
  */
 #define CONFIG_SYS_PSSR_VAL	    0x00000030
 #define CONFIG_SYS_CCCR		    0x00000161	/* 100 MHz memory, 400 MHz CPU, 400 Turbo  */
 #define CONFIG_SYS_CKEN		    0x000141ec	/* FFUART and STUART enabled	*/
 #define CONFIG_SYS_ICMR		    0x00000000	/* No interrupts enabled	*/
 /* FIXME
  *
  * RTC settings
  * Watchdog
  *
  */
 /*
  * Memory settings
  *
  */
 #define CONFIG_SYS_MSC0_VAL	    0x122423f0	/* FLASH   / LAN	    (cs0)/(cS1)	  */
 #define CONFIG_SYS_MSC1_VAL	    0x35f4aa4c	/* USB	   / ST3+ST5	    (cs2)/(cS3)	  */
 #define CONFIG_SYS_MSC2_VAL	    0x35f435fc	/* IDE	   / BCR + WatchDog (cs4)/(cS5)	  */
 #define CONFIG_SYS_MDCNFG_VAL	    0x000009c9
 #define CONFIG_SYS_MDMRS_VAL	    0x00220022
 #define CONFIG_SYS_MDREFR_VAL	    0x000da018	/* Initial setting, individual bits set in lowlevel_init.S */
 #define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
 #define	CONFIG_SYS_SXCNFG_VAL		0x00000000
 /*
  * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
  */
 #define CONFIG_SYS_MECR_VAL	      0x00000000
 #define CONFIG_SYS_MCMEM0_VAL	      0x00010504
 #define CONFIG_SYS_MCMEM1_VAL	      0x00010504
 #define CONFIG_SYS_MCATT0_VAL	      0x00010504
 #define CONFIG_SYS_MCATT1_VAL	      0x00010504
 #define CONFIG_SYS_MCIO0_VAL	      0x00004715
 #define CONFIG_SYS_MCIO1_VAL	      0x00004715
 /* Board specific defines */
 #ifndef __ASSEMBLY__
 /* global prototypes */
 void led_code(int code, int color);
 #endif
 #endif	/* __CONFIG_H */