Commit 68432c27438360aa3bc27c0c73bf3c12a8c6ffa7
Committed by
Albert ARIBAUD
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776784908c
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pxa: move i2c driver to the common place
For better sharing with other platform other than pxa's, it is more convenient to put the driver to the common place. Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Lei Wen <leiwen@marvell.com>
Showing 6 changed files with 455 additions and 470 deletions Inline Diff
arch/arm/cpu/pxa/Makefile
1 | # | 1 | # |
2 | # (C) Copyright 2000-2006 | 2 | # (C) Copyright 2000-2006 |
3 | # Wolfgang Denk, DENX Software Engineering, wd@denx.de. | 3 | # Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | # | 4 | # |
5 | # See file CREDITS for list of people who contributed to this | 5 | # See file CREDITS for list of people who contributed to this |
6 | # project. | 6 | # project. |
7 | # | 7 | # |
8 | # This program is free software; you can redistribute it and/or | 8 | # This program is free software; you can redistribute it and/or |
9 | # modify it under the terms of the GNU General Public License as | 9 | # modify it under the terms of the GNU General Public License as |
10 | # published by the Free Software Foundation; either version 2 of | 10 | # published by the Free Software Foundation; either version 2 of |
11 | # the License, or (at your option) any later version. | 11 | # the License, or (at your option) any later version. |
12 | # | 12 | # |
13 | # This program is distributed in the hope that it will be useful, | 13 | # This program is distributed in the hope that it will be useful, |
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | 14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
16 | # GNU General Public License for more details. | 16 | # GNU General Public License for more details. |
17 | # | 17 | # |
18 | # You should have received a copy of the GNU General Public License | 18 | # You should have received a copy of the GNU General Public License |
19 | # along with this program; if not, write to the Free Software | 19 | # along with this program; if not, write to the Free Software |
20 | # Foundation, Inc., 59 Temple Place, Suite 330, Boston, | 20 | # Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
21 | # MA 02111-1307 USA | 21 | # MA 02111-1307 USA |
22 | # | 22 | # |
23 | 23 | ||
24 | include $(TOPDIR)/config.mk | 24 | include $(TOPDIR)/config.mk |
25 | 25 | ||
26 | LIB = $(obj)lib$(CPU).o | 26 | LIB = $(obj)lib$(CPU).o |
27 | 27 | ||
28 | START = start.o | 28 | START = start.o |
29 | 29 | ||
30 | COBJS += cpu.o | 30 | COBJS += cpu.o |
31 | COBJS += i2c.o | ||
32 | COBJS += pxafb.o | 31 | COBJS += pxafb.o |
33 | COBJS += timer.o | 32 | COBJS += timer.o |
34 | COBJS += usb.o | 33 | COBJS += usb.o |
35 | 34 | ||
36 | SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) | 35 | SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) |
37 | OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) | 36 | OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) |
38 | START := $(addprefix $(obj),$(START)) | 37 | START := $(addprefix $(obj),$(START)) |
39 | 38 | ||
40 | all: $(obj).depend $(START) $(LIB) | 39 | all: $(obj).depend $(START) $(LIB) |
41 | 40 | ||
42 | $(LIB): $(OBJS) | 41 | $(LIB): $(OBJS) |
43 | $(call cmd_link_o_target, $(OBJS)) | 42 | $(call cmd_link_o_target, $(OBJS)) |
44 | 43 | ||
45 | ######################################################################### | 44 | ######################################################################### |
46 | 45 | ||
47 | # defines $(obj).depend target | 46 | # defines $(obj).depend target |
48 | include $(SRCTREE)/rules.mk | 47 | include $(SRCTREE)/rules.mk |
49 | 48 | ||
50 | sinclude $(obj).depend | 49 | sinclude $(obj).depend |
51 | 50 | ||
52 | ######################################################################### | 51 | ######################################################################### |
53 | 52 |
arch/arm/cpu/pxa/i2c.c
1 | /* | File was deleted | |
2 | * (C) Copyright 2000 | ||
3 | * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it | ||
4 | * | ||
5 | * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> | ||
6 | * Marius Groeger <mgroeger@sysgo.de> | ||
7 | * | ||
8 | * (C) Copyright 2003 Pengutronix e.K. | ||
9 | * Robert Schwebel <r.schwebel@pengutronix.de> | ||
10 | * | ||
11 | * See file CREDITS for list of people who contributed to this | ||
12 | * project. | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License as | ||
16 | * published by the Free Software Foundation; either version 2 of | ||
17 | * the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This program is distributed in the hope that it will be useful, | ||
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
22 | * GNU General Public License for more details. | ||
23 | * | ||
24 | * You should have received a copy of the GNU General Public License | ||
25 | * along with this program; if not, write to the Free Software | ||
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
27 | * MA 02111-1307 USA | ||
28 | * | ||
29 | * Back ported to the 8xx platform (from the 8260 platform) by | ||
30 | * Murray.Jensen@cmst.csiro.au, 27-Jan-01. | ||
31 | */ | ||
32 | |||
33 | /* FIXME: this file is PXA255 specific! What about other XScales? */ | ||
34 | |||
35 | #include <common.h> | ||
36 | #include <asm/io.h> | ||
37 | |||
38 | #ifdef CONFIG_HARD_I2C | ||
39 | |||
40 | /* | ||
41 | * - CONFIG_SYS_I2C_SPEED | ||
42 | * - I2C_PXA_SLAVE_ADDR | ||
43 | */ | ||
44 | |||
45 | #include <asm/arch/hardware.h> | ||
46 | #include <asm/arch/pxa-regs.h> | ||
47 | #include <i2c.h> | ||
48 | |||
49 | /*#define DEBUG_I2C 1 /###* activate local debugging output */ | ||
50 | #define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ | ||
51 | |||
52 | #if (CONFIG_SYS_I2C_SPEED == 400000) | ||
53 | #define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) | ||
54 | #else | ||
55 | #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) | ||
56 | #endif | ||
57 | |||
58 | #define I2C_ISR_INIT 0x7FF | ||
59 | |||
60 | #ifdef DEBUG_I2C | ||
61 | #define PRINTD(x) printf x | ||
62 | #else | ||
63 | #define PRINTD(x) | ||
64 | #endif | ||
65 | |||
66 | |||
67 | /* Shall the current transfer have a start/stop condition? */ | ||
68 | #define I2C_COND_NORMAL 0 | ||
69 | #define I2C_COND_START 1 | ||
70 | #define I2C_COND_STOP 2 | ||
71 | |||
72 | /* Shall the current transfer be ack/nacked or being waited for it? */ | ||
73 | #define I2C_ACKNAK_WAITACK 1 | ||
74 | #define I2C_ACKNAK_SENDACK 2 | ||
75 | #define I2C_ACKNAK_SENDNAK 4 | ||
76 | |||
77 | /* Specify who shall transfer the data (master or slave) */ | ||
78 | #define I2C_READ 0 | ||
79 | #define I2C_WRITE 1 | ||
80 | |||
81 | /* All transfers are described by this data structure */ | ||
82 | struct i2c_msg { | ||
83 | u8 condition; | ||
84 | u8 acknack; | ||
85 | u8 direction; | ||
86 | u8 data; | ||
87 | }; | ||
88 | |||
89 | |||
90 | /** | ||
91 | * i2c_pxa_reset: - reset the host controller | ||
92 | * | ||
93 | */ | ||
94 | |||
95 | static void i2c_reset( void ) | ||
96 | { | ||
97 | writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */ | ||
98 | writel(readl(ICR) | ICR_UR, ICR); /* reset the unit */ | ||
99 | udelay(100); | ||
100 | writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */ | ||
101 | #ifdef CONFIG_CPU_MONAHANS | ||
102 | /* | CKENB_1_PWM1 | CKENB_0_PWM0); */ | ||
103 | writel(readl(CKENB) | (CKENB_4_I2C), CKENB); | ||
104 | #else /* CONFIG_CPU_MONAHANS */ | ||
105 | /* set the global I2C clock on */ | ||
106 | writel(readl(CKEN) | CKEN14_I2C, CKEN); | ||
107 | #endif | ||
108 | writel(I2C_PXA_SLAVE_ADDR, ISAR); /* set our slave address */ | ||
109 | writel(I2C_ICR_INIT, ICR); /* set control reg values */ | ||
110 | writel(I2C_ISR_INIT, ISR); /* set clear interrupt bits */ | ||
111 | writel(readl(ICR) | ICR_IUE, ICR); /* enable unit */ | ||
112 | udelay(100); | ||
113 | } | ||
114 | |||
115 | |||
116 | /** | ||
117 | * i2c_isr_set_cleared: - wait until certain bits of the I2C status register | ||
118 | * are set and cleared | ||
119 | * | ||
120 | * @return: 1 in case of success, 0 means timeout (no match within 10 ms). | ||
121 | */ | ||
122 | static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask ) | ||
123 | { | ||
124 | int timeout = 10000; | ||
125 | |||
126 | while( ((ISR & set_mask)!=set_mask) || ((ISR & cleared_mask)!=0) ){ | ||
127 | udelay( 10 ); | ||
128 | if( timeout-- < 0 ) return 0; | ||
129 | } | ||
130 | |||
131 | return 1; | ||
132 | } | ||
133 | |||
134 | |||
135 | /** | ||
136 | * i2c_transfer: - Transfer one byte over the i2c bus | ||
137 | * | ||
138 | * This function can tranfer a byte over the i2c bus in both directions. | ||
139 | * It is used by the public API functions. | ||
140 | * | ||
141 | * @return: 0: transfer successful | ||
142 | * -1: message is empty | ||
143 | * -2: transmit timeout | ||
144 | * -3: ACK missing | ||
145 | * -4: receive timeout | ||
146 | * -5: illegal parameters | ||
147 | * -6: bus is busy and couldn't be aquired | ||
148 | */ | ||
149 | int i2c_transfer(struct i2c_msg *msg) | ||
150 | { | ||
151 | int ret; | ||
152 | |||
153 | if (!msg) | ||
154 | goto transfer_error_msg_empty; | ||
155 | |||
156 | switch(msg->direction) { | ||
157 | |||
158 | case I2C_WRITE: | ||
159 | |||
160 | /* check if bus is not busy */ | ||
161 | if (!i2c_isr_set_cleared(0,ISR_IBB)) | ||
162 | goto transfer_error_bus_busy; | ||
163 | |||
164 | /* start transmission */ | ||
165 | writel(readl(ICR) & ~ICR_START, ICR); | ||
166 | writel(readl(ICR) & ~ICR_STOP, ICR); | ||
167 | writel(msg->data, IDBR); | ||
168 | if (msg->condition == I2C_COND_START) | ||
169 | writel(readl(ICR) | ICR_START, ICR); | ||
170 | if (msg->condition == I2C_COND_STOP) | ||
171 | writel(readl(ICR) | ICR_STOP, ICR); | ||
172 | if (msg->acknack == I2C_ACKNAK_SENDNAK) | ||
173 | writel(readl(ICR) | ICR_ACKNAK, ICR); | ||
174 | if (msg->acknack == I2C_ACKNAK_SENDACK) | ||
175 | writel(readl(ICR) & ~ICR_ACKNAK, ICR); | ||
176 | writel(readl(ICR) & ~ICR_ALDIE, ICR); | ||
177 | writel(readl(ICR) | ICR_TB, ICR); | ||
178 | |||
179 | /* transmit register empty? */ | ||
180 | if (!i2c_isr_set_cleared(ISR_ITE,0)) | ||
181 | goto transfer_error_transmit_timeout; | ||
182 | |||
183 | /* clear 'transmit empty' state */ | ||
184 | writel(readl(ISR) | ISR_ITE, ISR); | ||
185 | |||
186 | /* wait for ACK from slave */ | ||
187 | if (msg->acknack == I2C_ACKNAK_WAITACK) | ||
188 | if (!i2c_isr_set_cleared(0,ISR_ACKNAK)) | ||
189 | goto transfer_error_ack_missing; | ||
190 | break; | ||
191 | |||
192 | case I2C_READ: | ||
193 | |||
194 | /* check if bus is not busy */ | ||
195 | if (!i2c_isr_set_cleared(0,ISR_IBB)) | ||
196 | goto transfer_error_bus_busy; | ||
197 | |||
198 | /* start receive */ | ||
199 | writel(readl(ICR) & ~ICR_START, ICR); | ||
200 | writel(readl(ICR) & ~ICR_STOP, ICR); | ||
201 | if (msg->condition == I2C_COND_START) | ||
202 | writel(readl(ICR) | ICR_START, ICR); | ||
203 | if (msg->condition == I2C_COND_STOP) | ||
204 | writel(readl(ICR) | ICR_STOP, ICR); | ||
205 | if (msg->acknack == I2C_ACKNAK_SENDNAK) | ||
206 | writel(readl(ICR) | ICR_ACKNAK, ICR); | ||
207 | if (msg->acknack == I2C_ACKNAK_SENDACK) | ||
208 | writel(readl(ICR) & ~ICR_ACKNAK, ICR); | ||
209 | writel(readl(ICR) & ~ICR_ALDIE, ICR); | ||
210 | writel(readl(ICR) | ICR_TB, ICR); | ||
211 | |||
212 | /* receive register full? */ | ||
213 | if (!i2c_isr_set_cleared(ISR_IRF,0)) | ||
214 | goto transfer_error_receive_timeout; | ||
215 | |||
216 | msg->data = readl(IDBR); | ||
217 | |||
218 | /* clear 'receive empty' state */ | ||
219 | writel(readl(ISR) | ISR_IRF, ISR); | ||
220 | |||
221 | break; | ||
222 | |||
223 | default: | ||
224 | |||
225 | goto transfer_error_illegal_param; | ||
226 | |||
227 | } | ||
228 | |||
229 | return 0; | ||
230 | |||
231 | transfer_error_msg_empty: | ||
232 | PRINTD(("i2c_transfer: error: 'msg' is empty\n")); | ||
233 | ret = -1; goto i2c_transfer_finish; | ||
234 | |||
235 | transfer_error_transmit_timeout: | ||
236 | PRINTD(("i2c_transfer: error: transmit timeout\n")); | ||
237 | ret = -2; goto i2c_transfer_finish; | ||
238 | |||
239 | transfer_error_ack_missing: | ||
240 | PRINTD(("i2c_transfer: error: ACK missing\n")); | ||
241 | ret = -3; goto i2c_transfer_finish; | ||
242 | |||
243 | transfer_error_receive_timeout: | ||
244 | PRINTD(("i2c_transfer: error: receive timeout\n")); | ||
245 | ret = -4; goto i2c_transfer_finish; | ||
246 | |||
247 | transfer_error_illegal_param: | ||
248 | PRINTD(("i2c_transfer: error: illegal parameters\n")); | ||
249 | ret = -5; goto i2c_transfer_finish; | ||
250 | |||
251 | transfer_error_bus_busy: | ||
252 | PRINTD(("i2c_transfer: error: bus is busy\n")); | ||
253 | ret = -6; goto i2c_transfer_finish; | ||
254 | |||
255 | i2c_transfer_finish: | ||
256 | PRINTD(("i2c_transfer: ISR: 0x%04x\n",ISR)); | ||
257 | i2c_reset(); | ||
258 | return ret; | ||
259 | |||
260 | } | ||
261 | |||
262 | /* ------------------------------------------------------------------------ */ | ||
263 | /* API Functions */ | ||
264 | /* ------------------------------------------------------------------------ */ | ||
265 | |||
266 | void i2c_init(int speed, int slaveaddr) | ||
267 | { | ||
268 | #ifdef CONFIG_SYS_I2C_INIT_BOARD | ||
269 | /* call board specific i2c bus reset routine before accessing the */ | ||
270 | /* environment, which might be in a chip on that bus. For details */ | ||
271 | /* about this problem see doc/I2C_Edge_Conditions. */ | ||
272 | i2c_init_board(); | ||
273 | #endif | ||
274 | } | ||
275 | |||
276 | |||
277 | /** | ||
278 | * i2c_probe: - Test if a chip answers for a given i2c address | ||
279 | * | ||
280 | * @chip: address of the chip which is searched for | ||
281 | * @return: 0 if a chip was found, -1 otherwhise | ||
282 | */ | ||
283 | |||
284 | int i2c_probe(uchar chip) | ||
285 | { | ||
286 | struct i2c_msg msg; | ||
287 | |||
288 | i2c_reset(); | ||
289 | |||
290 | msg.condition = I2C_COND_START; | ||
291 | msg.acknack = I2C_ACKNAK_WAITACK; | ||
292 | msg.direction = I2C_WRITE; | ||
293 | msg.data = (chip << 1) + 1; | ||
294 | if (i2c_transfer(&msg)) return -1; | ||
295 | |||
296 | msg.condition = I2C_COND_STOP; | ||
297 | msg.acknack = I2C_ACKNAK_SENDNAK; | ||
298 | msg.direction = I2C_READ; | ||
299 | msg.data = 0x00; | ||
300 | if (i2c_transfer(&msg)) return -1; | ||
301 | |||
302 | return 0; | ||
303 | } | ||
304 | |||
305 | |||
306 | /** | ||
307 | * i2c_read: - Read multiple bytes from an i2c device | ||
308 | * | ||
309 | * The higher level routines take into account that this function is only | ||
310 | * called with len < page length of the device (see configuration file) | ||
311 | * | ||
312 | * @chip: address of the chip which is to be read | ||
313 | * @addr: i2c data address within the chip | ||
314 | * @alen: length of the i2c data address (1..2 bytes) | ||
315 | * @buffer: where to write the data | ||
316 | * @len: how much byte do we want to read | ||
317 | * @return: 0 in case of success | ||
318 | */ | ||
319 | |||
320 | int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) | ||
321 | { | ||
322 | struct i2c_msg msg; | ||
323 | u8 addr_bytes[3]; /* lowest...highest byte of data address */ | ||
324 | int ret; | ||
325 | |||
326 | PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); | ||
327 | |||
328 | i2c_reset(); | ||
329 | |||
330 | /* dummy chip address write */ | ||
331 | PRINTD(("i2c_read: dummy chip address write\n")); | ||
332 | msg.condition = I2C_COND_START; | ||
333 | msg.acknack = I2C_ACKNAK_WAITACK; | ||
334 | msg.direction = I2C_WRITE; | ||
335 | msg.data = (chip << 1); | ||
336 | msg.data &= 0xFE; | ||
337 | if ((ret=i2c_transfer(&msg))) return -1; | ||
338 | |||
339 | /* | ||
340 | * send memory address bytes; | ||
341 | * alen defines how much bytes we have to send. | ||
342 | */ | ||
343 | /*addr &= ((1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)-1); */ | ||
344 | addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); | ||
345 | addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); | ||
346 | addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); | ||
347 | |||
348 | while (--alen >= 0) { | ||
349 | |||
350 | PRINTD(("i2c_read: send memory word address byte %1d\n",alen)); | ||
351 | msg.condition = I2C_COND_NORMAL; | ||
352 | msg.acknack = I2C_ACKNAK_WAITACK; | ||
353 | msg.direction = I2C_WRITE; | ||
354 | msg.data = addr_bytes[alen]; | ||
355 | if ((ret=i2c_transfer(&msg))) return -1; | ||
356 | } | ||
357 | |||
358 | |||
359 | /* start read sequence */ | ||
360 | PRINTD(("i2c_read: start read sequence\n")); | ||
361 | msg.condition = I2C_COND_START; | ||
362 | msg.acknack = I2C_ACKNAK_WAITACK; | ||
363 | msg.direction = I2C_WRITE; | ||
364 | msg.data = (chip << 1); | ||
365 | msg.data |= 0x01; | ||
366 | if ((ret=i2c_transfer(&msg))) return -1; | ||
367 | |||
368 | /* read bytes; send NACK at last byte */ | ||
369 | while (len--) { | ||
370 | |||
371 | if (len==0) { | ||
372 | msg.condition = I2C_COND_STOP; | ||
373 | msg.acknack = I2C_ACKNAK_SENDNAK; | ||
374 | } else { | ||
375 | msg.condition = I2C_COND_NORMAL; | ||
376 | msg.acknack = I2C_ACKNAK_SENDACK; | ||
377 | } | ||
378 | |||
379 | msg.direction = I2C_READ; | ||
380 | msg.data = 0x00; | ||
381 | if ((ret=i2c_transfer(&msg))) return -1; | ||
382 | |||
383 | *buffer = msg.data; | ||
384 | PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); | ||
385 | buffer++; | ||
386 | |||
387 | } | ||
388 | |||
389 | i2c_reset(); | ||
390 | |||
391 | return 0; | ||
392 | } | ||
393 | |||
394 | |||
395 | /** | ||
396 | * i2c_write: - Write multiple bytes to an i2c device | ||
397 | * | ||
398 | * The higher level routines take into account that this function is only | ||
399 | * called with len < page length of the device (see configuration file) | ||
400 | * | ||
401 | * @chip: address of the chip which is to be written | ||
402 | * @addr: i2c data address within the chip | ||
403 | * @alen: length of the i2c data address (1..2 bytes) | ||
404 | * @buffer: where to find the data to be written | ||
405 | * @len: how much byte do we want to read | ||
406 | * @return: 0 in case of success | ||
407 | */ | ||
408 | |||
409 | int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) | ||
410 | { | ||
411 | struct i2c_msg msg; | ||
412 | u8 addr_bytes[3]; /* lowest...highest byte of data address */ | ||
413 | |||
414 | PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); | ||
415 | |||
416 | i2c_reset(); | ||
417 | |||
418 | /* chip address write */ | ||
419 | PRINTD(("i2c_write: chip address write\n")); | ||
420 | msg.condition = I2C_COND_START; | ||
421 | msg.acknack = I2C_ACKNAK_WAITACK; | ||
422 | msg.direction = I2C_WRITE; | ||
423 | msg.data = (chip << 1); | ||
424 | msg.data &= 0xFE; | ||
425 | if (i2c_transfer(&msg)) return -1; | ||
426 | |||
427 | /* | ||
428 | * send memory address bytes; | ||
429 | * alen defines how much bytes we have to send. | ||
430 | */ | ||
431 | addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); | ||
432 | addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); | ||
433 | addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); | ||
434 | |||
435 | while (--alen >= 0) { | ||
436 | |||
437 | PRINTD(("i2c_write: send memory word address\n")); | ||
438 | msg.condition = I2C_COND_NORMAL; | ||
439 | msg.acknack = I2C_ACKNAK_WAITACK; | ||
440 | msg.direction = I2C_WRITE; | ||
441 | msg.data = addr_bytes[alen]; | ||
442 | if (i2c_transfer(&msg)) return -1; | ||
443 | } | ||
444 | |||
445 | /* write bytes; send NACK at last byte */ | ||
446 | while (len--) { | ||
447 | |||
448 | PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); | ||
449 | |||
450 | if (len==0) | ||
451 | msg.condition = I2C_COND_STOP; | ||
452 | else | ||
453 | msg.condition = I2C_COND_NORMAL; | ||
454 | |||
455 | msg.acknack = I2C_ACKNAK_WAITACK; | ||
456 | msg.direction = I2C_WRITE; | ||
457 | msg.data = *(buffer++); | ||
458 | |||
459 | if (i2c_transfer(&msg)) return -1; | ||
460 | |||
461 | } | ||
462 | |||
463 | i2c_reset(); | ||
464 | |||
465 | return 0; | ||
466 | |||
467 | } | ||
468 | |||
469 | #endif /* CONFIG_HARD_I2C */ | ||
470 | 1 | /* |
drivers/i2c/Makefile
1 | # | 1 | # |
2 | # (C) Copyright 2000-2007 | 2 | # (C) Copyright 2000-2007 |
3 | # Wolfgang Denk, DENX Software Engineering, wd@denx.de. | 3 | # Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | # | 4 | # |
5 | # See file CREDITS for list of people who contributed to this | 5 | # See file CREDITS for list of people who contributed to this |
6 | # project. | 6 | # project. |
7 | # | 7 | # |
8 | # This program is free software; you can redistribute it and/or | 8 | # This program is free software; you can redistribute it and/or |
9 | # modify it under the terms of the GNU General Public License as | 9 | # modify it under the terms of the GNU General Public License as |
10 | # published by the Free Software Foundation; either version 2 of | 10 | # published by the Free Software Foundation; either version 2 of |
11 | # the License, or (at your option) any later version. | 11 | # the License, or (at your option) any later version. |
12 | # | 12 | # |
13 | # This program is distributed in the hope that it will be useful, | 13 | # This program is distributed in the hope that it will be useful, |
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | 14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
16 | # GNU General Public License for more details. | 16 | # GNU General Public License for more details. |
17 | # | 17 | # |
18 | # You should have received a copy of the GNU General Public License | 18 | # You should have received a copy of the GNU General Public License |
19 | # along with this program; if not, write to the Free Software | 19 | # along with this program; if not, write to the Free Software |
20 | # Foundation, Inc., 59 Temple Place, Suite 330, Boston, | 20 | # Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
21 | # MA 02111-1307 USA | 21 | # MA 02111-1307 USA |
22 | # | 22 | # |
23 | 23 | ||
24 | include $(TOPDIR)/config.mk | 24 | include $(TOPDIR)/config.mk |
25 | 25 | ||
26 | LIB := $(obj)libi2c.o | 26 | LIB := $(obj)libi2c.o |
27 | 27 | ||
28 | COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o | 28 | COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o |
29 | COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o | 29 | COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o |
30 | COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o | 30 | COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o |
31 | COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o | 31 | COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o |
32 | COBJS-$(CONFIG_I2C_MV) += mv_i2c.o | ||
32 | COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o | 33 | COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o |
33 | COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o | 34 | COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o |
34 | COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o | 35 | COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o |
35 | COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o | 36 | COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o |
36 | COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o | 37 | COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o |
37 | COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o | 38 | COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o |
38 | COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o | 39 | COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o |
39 | COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o | 40 | COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o |
40 | COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o | 41 | COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o |
41 | COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o | 42 | COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o |
42 | COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o | 43 | COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o |
43 | 44 | ||
44 | COBJS := $(COBJS-y) | 45 | COBJS := $(COBJS-y) |
45 | SRCS := $(COBJS:.o=.c) | 46 | SRCS := $(COBJS:.o=.c) |
46 | OBJS := $(addprefix $(obj),$(COBJS)) | 47 | OBJS := $(addprefix $(obj),$(COBJS)) |
47 | 48 | ||
48 | all: $(LIB) | 49 | all: $(LIB) |
49 | 50 | ||
50 | $(LIB): $(obj).depend $(OBJS) | 51 | $(LIB): $(obj).depend $(OBJS) |
51 | $(call cmd_link_o_target, $(OBJS)) | 52 | $(call cmd_link_o_target, $(OBJS)) |
52 | 53 | ||
53 | ######################################################################### | 54 | ######################################################################### |
54 | 55 | ||
55 | # defines $(obj).depend target | 56 | # defines $(obj).depend target |
56 | include $(SRCTREE)/rules.mk | 57 | include $(SRCTREE)/rules.mk |
57 | 58 | ||
58 | sinclude $(obj).depend | 59 | sinclude $(obj).depend |
59 | 60 | ||
60 | ######################################################################### | 61 | ######################################################################### |
61 | 62 |
drivers/i2c/mv_i2c.c
File was created | 1 | /* | |
2 | * (C) Copyright 2000 | ||
3 | * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it | ||
4 | * | ||
5 | * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> | ||
6 | * Marius Groeger <mgroeger@sysgo.de> | ||
7 | * | ||
8 | * (C) Copyright 2003 Pengutronix e.K. | ||
9 | * Robert Schwebel <r.schwebel@pengutronix.de> | ||
10 | * | ||
11 | * See file CREDITS for list of people who contributed to this | ||
12 | * project. | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License as | ||
16 | * published by the Free Software Foundation; either version 2 of | ||
17 | * the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This program is distributed in the hope that it will be useful, | ||
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
22 | * GNU General Public License for more details. | ||
23 | * | ||
24 | * You should have received a copy of the GNU General Public License | ||
25 | * along with this program; if not, write to the Free Software | ||
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
27 | * MA 02111-1307 USA | ||
28 | * | ||
29 | * Back ported to the 8xx platform (from the 8260 platform) by | ||
30 | * Murray.Jensen@cmst.csiro.au, 27-Jan-01. | ||
31 | */ | ||
32 | |||
33 | #include <common.h> | ||
34 | #include <asm/io.h> | ||
35 | |||
36 | #ifdef CONFIG_HARD_I2C | ||
37 | |||
38 | /* | ||
39 | * - CONFIG_SYS_I2C_SPEED | ||
40 | * - I2C_PXA_SLAVE_ADDR | ||
41 | */ | ||
42 | |||
43 | #include <asm/arch/hardware.h> | ||
44 | #include <asm/arch/pxa-regs.h> | ||
45 | #include <i2c.h> | ||
46 | |||
47 | #if (CONFIG_SYS_I2C_SPEED == 400000) | ||
48 | #define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD \ | ||
49 | | ICR_SCLE) | ||
50 | #else | ||
51 | #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) | ||
52 | #endif | ||
53 | |||
54 | #define I2C_ISR_INIT 0x7FF | ||
55 | |||
56 | #ifdef DEBUG_I2C | ||
57 | #define PRINTD(x) printf x | ||
58 | #else | ||
59 | #define PRINTD(x) | ||
60 | #endif | ||
61 | |||
62 | /* Shall the current transfer have a start/stop condition? */ | ||
63 | #define I2C_COND_NORMAL 0 | ||
64 | #define I2C_COND_START 1 | ||
65 | #define I2C_COND_STOP 2 | ||
66 | |||
67 | /* Shall the current transfer be ack/nacked or being waited for it? */ | ||
68 | #define I2C_ACKNAK_WAITACK 1 | ||
69 | #define I2C_ACKNAK_SENDACK 2 | ||
70 | #define I2C_ACKNAK_SENDNAK 4 | ||
71 | |||
72 | /* Specify who shall transfer the data (master or slave) */ | ||
73 | #define I2C_READ 0 | ||
74 | #define I2C_WRITE 1 | ||
75 | |||
76 | /* All transfers are described by this data structure */ | ||
77 | struct i2c_msg { | ||
78 | u8 condition; | ||
79 | u8 acknack; | ||
80 | u8 direction; | ||
81 | u8 data; | ||
82 | }; | ||
83 | |||
84 | /* | ||
85 | * i2c_pxa_reset: - reset the host controller | ||
86 | * | ||
87 | */ | ||
88 | static void i2c_reset(void) | ||
89 | { | ||
90 | writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */ | ||
91 | writel(readl(ICR) | ICR_UR, ICR); /* reset the unit */ | ||
92 | udelay(100); | ||
93 | writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */ | ||
94 | #ifdef CONFIG_CPU_MONAHANS | ||
95 | /* | CKENB_1_PWM1 | CKENB_0_PWM0); */ | ||
96 | writel(readl(CKENB) | (CKENB_4_I2C), CKENB); | ||
97 | #else /* CONFIG_CPU_MONAHANS */ | ||
98 | /* set the global I2C clock on */ | ||
99 | writel(readl(CKEN) | CKEN14_I2C, CKEN); | ||
100 | #endif | ||
101 | writel(I2C_PXA_SLAVE_ADDR, ISAR); /* set our slave address */ | ||
102 | writel(I2C_ICR_INIT, ICR); /* set control reg values */ | ||
103 | writel(I2C_ISR_INIT, ISR); /* set clear interrupt bits */ | ||
104 | writel(readl(ICR) | ICR_IUE, ICR); /* enable unit */ | ||
105 | udelay(100); | ||
106 | } | ||
107 | |||
108 | /* | ||
109 | * i2c_isr_set_cleared: - wait until certain bits of the I2C status register | ||
110 | * are set and cleared | ||
111 | * | ||
112 | * @return: 1 in case of success, 0 means timeout (no match within 10 ms). | ||
113 | */ | ||
114 | static int i2c_isr_set_cleared(unsigned long set_mask, | ||
115 | unsigned long cleared_mask) | ||
116 | { | ||
117 | int timeout = 10000; | ||
118 | |||
119 | while (((ISR & set_mask) != set_mask) || ((ISR & cleared_mask) != 0)) { | ||
120 | udelay(10); | ||
121 | if (timeout-- < 0) | ||
122 | return 0; | ||
123 | } | ||
124 | |||
125 | return 1; | ||
126 | } | ||
127 | |||
128 | /* | ||
129 | * i2c_transfer: - Transfer one byte over the i2c bus | ||
130 | * | ||
131 | * This function can tranfer a byte over the i2c bus in both directions. | ||
132 | * It is used by the public API functions. | ||
133 | * | ||
134 | * @return: 0: transfer successful | ||
135 | * -1: message is empty | ||
136 | * -2: transmit timeout | ||
137 | * -3: ACK missing | ||
138 | * -4: receive timeout | ||
139 | * -5: illegal parameters | ||
140 | * -6: bus is busy and couldn't be aquired | ||
141 | */ | ||
142 | int i2c_transfer(struct i2c_msg *msg) | ||
143 | { | ||
144 | int ret; | ||
145 | |||
146 | if (!msg) | ||
147 | goto transfer_error_msg_empty; | ||
148 | |||
149 | switch (msg->direction) { | ||
150 | case I2C_WRITE: | ||
151 | /* check if bus is not busy */ | ||
152 | if (!i2c_isr_set_cleared(0, ISR_IBB)) | ||
153 | goto transfer_error_bus_busy; | ||
154 | |||
155 | /* start transmission */ | ||
156 | writel(readl(ICR) & ~ICR_START, ICR); | ||
157 | writel(readl(ICR) & ~ICR_STOP, ICR); | ||
158 | writel(msg->data, IDBR); | ||
159 | if (msg->condition == I2C_COND_START) | ||
160 | writel(readl(ICR) | ICR_START, ICR); | ||
161 | if (msg->condition == I2C_COND_STOP) | ||
162 | writel(readl(ICR) | ICR_STOP, ICR); | ||
163 | if (msg->acknack == I2C_ACKNAK_SENDNAK) | ||
164 | writel(readl(ICR) | ICR_ACKNAK, ICR); | ||
165 | if (msg->acknack == I2C_ACKNAK_SENDACK) | ||
166 | writel(readl(ICR) & ~ICR_ACKNAK, ICR); | ||
167 | writel(readl(ICR) & ~ICR_ALDIE, ICR); | ||
168 | writel(readl(ICR) | ICR_TB, ICR); | ||
169 | |||
170 | /* transmit register empty? */ | ||
171 | if (!i2c_isr_set_cleared(ISR_ITE, 0)) | ||
172 | goto transfer_error_transmit_timeout; | ||
173 | |||
174 | /* clear 'transmit empty' state */ | ||
175 | writel(readl(ISR) | ISR_ITE, ISR); | ||
176 | |||
177 | /* wait for ACK from slave */ | ||
178 | if (msg->acknack == I2C_ACKNAK_WAITACK) | ||
179 | if (!i2c_isr_set_cleared(0, ISR_ACKNAK)) | ||
180 | goto transfer_error_ack_missing; | ||
181 | break; | ||
182 | |||
183 | case I2C_READ: | ||
184 | |||
185 | /* check if bus is not busy */ | ||
186 | if (!i2c_isr_set_cleared(0, ISR_IBB)) | ||
187 | goto transfer_error_bus_busy; | ||
188 | |||
189 | /* start receive */ | ||
190 | writel(readl(ICR) & ~ICR_START, ICR); | ||
191 | writel(readl(ICR) & ~ICR_STOP, ICR); | ||
192 | if (msg->condition == I2C_COND_START) | ||
193 | writel(readl(ICR) | ICR_START, ICR); | ||
194 | if (msg->condition == I2C_COND_STOP) | ||
195 | writel(readl(ICR) | ICR_STOP, ICR); | ||
196 | if (msg->acknack == I2C_ACKNAK_SENDNAK) | ||
197 | writel(readl(ICR) | ICR_ACKNAK, ICR); | ||
198 | if (msg->acknack == I2C_ACKNAK_SENDACK) | ||
199 | writel(readl(ICR) & ~ICR_ACKNAK, ICR); | ||
200 | writel(readl(ICR) & ~ICR_ALDIE, ICR); | ||
201 | writel(readl(ICR) | ICR_TB, ICR); | ||
202 | |||
203 | /* receive register full? */ | ||
204 | if (!i2c_isr_set_cleared(ISR_IRF, 0)) | ||
205 | goto transfer_error_receive_timeout; | ||
206 | |||
207 | msg->data = readl(IDBR); | ||
208 | |||
209 | /* clear 'receive empty' state */ | ||
210 | writel(readl(ISR) | ISR_IRF, ISR); | ||
211 | |||
212 | break; | ||
213 | default: | ||
214 | goto transfer_error_illegal_param; | ||
215 | } | ||
216 | |||
217 | return 0; | ||
218 | |||
219 | transfer_error_msg_empty: | ||
220 | PRINTD(("i2c_transfer: error: 'msg' is empty\n")); | ||
221 | ret = -1; goto i2c_transfer_finish; | ||
222 | |||
223 | transfer_error_transmit_timeout: | ||
224 | PRINTD(("i2c_transfer: error: transmit timeout\n")); | ||
225 | ret = -2; goto i2c_transfer_finish; | ||
226 | |||
227 | transfer_error_ack_missing: | ||
228 | PRINTD(("i2c_transfer: error: ACK missing\n")); | ||
229 | ret = -3; goto i2c_transfer_finish; | ||
230 | |||
231 | transfer_error_receive_timeout: | ||
232 | PRINTD(("i2c_transfer: error: receive timeout\n")); | ||
233 | ret = -4; goto i2c_transfer_finish; | ||
234 | |||
235 | transfer_error_illegal_param: | ||
236 | PRINTD(("i2c_transfer: error: illegal parameters\n")); | ||
237 | ret = -5; goto i2c_transfer_finish; | ||
238 | |||
239 | transfer_error_bus_busy: | ||
240 | PRINTD(("i2c_transfer: error: bus is busy\n")); | ||
241 | ret = -6; goto i2c_transfer_finish; | ||
242 | |||
243 | i2c_transfer_finish: | ||
244 | PRINTD(("i2c_transfer: ISR: 0x%04x\n", ISR)); | ||
245 | i2c_reset(); | ||
246 | return ret; | ||
247 | } | ||
248 | |||
249 | /* ------------------------------------------------------------------------ */ | ||
250 | /* API Functions */ | ||
251 | /* ------------------------------------------------------------------------ */ | ||
252 | void i2c_init(int speed, int slaveaddr) | ||
253 | { | ||
254 | #ifdef CONFIG_SYS_I2C_INIT_BOARD | ||
255 | /* call board specific i2c bus reset routine before accessing the */ | ||
256 | /* environment, which might be in a chip on that bus. For details */ | ||
257 | /* about this problem see doc/I2C_Edge_Conditions. */ | ||
258 | i2c_init_board(); | ||
259 | #endif | ||
260 | } | ||
261 | |||
262 | /* | ||
263 | * i2c_probe: - Test if a chip answers for a given i2c address | ||
264 | * | ||
265 | * @chip: address of the chip which is searched for | ||
266 | * @return: 0 if a chip was found, -1 otherwhise | ||
267 | */ | ||
268 | int i2c_probe(uchar chip) | ||
269 | { | ||
270 | struct i2c_msg msg; | ||
271 | |||
272 | i2c_reset(); | ||
273 | |||
274 | msg.condition = I2C_COND_START; | ||
275 | msg.acknack = I2C_ACKNAK_WAITACK; | ||
276 | msg.direction = I2C_WRITE; | ||
277 | msg.data = (chip << 1) + 1; | ||
278 | if (i2c_transfer(&msg)) | ||
279 | return -1; | ||
280 | |||
281 | msg.condition = I2C_COND_STOP; | ||
282 | msg.acknack = I2C_ACKNAK_SENDNAK; | ||
283 | msg.direction = I2C_READ; | ||
284 | msg.data = 0x00; | ||
285 | if (i2c_transfer(&msg)) | ||
286 | return -1; | ||
287 | |||
288 | return 0; | ||
289 | } | ||
290 | |||
291 | /* | ||
292 | * i2c_read: - Read multiple bytes from an i2c device | ||
293 | * | ||
294 | * The higher level routines take into account that this function is only | ||
295 | * called with len < page length of the device (see configuration file) | ||
296 | * | ||
297 | * @chip: address of the chip which is to be read | ||
298 | * @addr: i2c data address within the chip | ||
299 | * @alen: length of the i2c data address (1..2 bytes) | ||
300 | * @buffer: where to write the data | ||
301 | * @len: how much byte do we want to read | ||
302 | * @return: 0 in case of success | ||
303 | */ | ||
304 | int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) | ||
305 | { | ||
306 | struct i2c_msg msg; | ||
307 | u8 addr_bytes[3]; /* lowest...highest byte of data address */ | ||
308 | |||
309 | PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, " | ||
310 | "len=0x%02x)\n", chip, addr, alen, len)); | ||
311 | |||
312 | i2c_reset(); | ||
313 | |||
314 | /* dummy chip address write */ | ||
315 | PRINTD(("i2c_read: dummy chip address write\n")); | ||
316 | msg.condition = I2C_COND_START; | ||
317 | msg.acknack = I2C_ACKNAK_WAITACK; | ||
318 | msg.direction = I2C_WRITE; | ||
319 | msg.data = (chip << 1); | ||
320 | msg.data &= 0xFE; | ||
321 | if (i2c_transfer(&msg)) | ||
322 | return -1; | ||
323 | |||
324 | /* | ||
325 | * send memory address bytes; | ||
326 | * alen defines how much bytes we have to send. | ||
327 | */ | ||
328 | /*addr &= ((1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)-1); */ | ||
329 | addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); | ||
330 | addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); | ||
331 | addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); | ||
332 | |||
333 | while (--alen >= 0) { | ||
334 | PRINTD(("i2c_read: send memory word address byte %1d\n", alen)); | ||
335 | msg.condition = I2C_COND_NORMAL; | ||
336 | msg.acknack = I2C_ACKNAK_WAITACK; | ||
337 | msg.direction = I2C_WRITE; | ||
338 | msg.data = addr_bytes[alen]; | ||
339 | if (i2c_transfer(&msg)) | ||
340 | return -1; | ||
341 | } | ||
342 | |||
343 | /* start read sequence */ | ||
344 | PRINTD(("i2c_read: start read sequence\n")); | ||
345 | msg.condition = I2C_COND_START; | ||
346 | msg.acknack = I2C_ACKNAK_WAITACK; | ||
347 | msg.direction = I2C_WRITE; | ||
348 | msg.data = (chip << 1); | ||
349 | msg.data |= 0x01; | ||
350 | if (i2c_transfer(&msg)) | ||
351 | return -1; | ||
352 | |||
353 | /* read bytes; send NACK at last byte */ | ||
354 | while (len--) { | ||
355 | if (len == 0) { | ||
356 | msg.condition = I2C_COND_STOP; | ||
357 | msg.acknack = I2C_ACKNAK_SENDNAK; | ||
358 | } else { | ||
359 | msg.condition = I2C_COND_NORMAL; | ||
360 | msg.acknack = I2C_ACKNAK_SENDACK; | ||
361 | } | ||
362 | |||
363 | msg.direction = I2C_READ; | ||
364 | msg.data = 0x00; | ||
365 | if (i2c_transfer(&msg)) | ||
366 | return -1; | ||
367 | |||
368 | *buffer = msg.data; | ||
369 | PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n", | ||
370 | (unsigned int)buffer, *buffer)); | ||
371 | buffer++; | ||
372 | } | ||
373 | |||
374 | i2c_reset(); | ||
375 | |||
376 | return 0; | ||
377 | } | ||
378 | |||
379 | /* | ||
380 | * i2c_write: - Write multiple bytes to an i2c device | ||
381 | * | ||
382 | * The higher level routines take into account that this function is only | ||
383 | * called with len < page length of the device (see configuration file) | ||
384 | * | ||
385 | * @chip: address of the chip which is to be written | ||
386 | * @addr: i2c data address within the chip | ||
387 | * @alen: length of the i2c data address (1..2 bytes) | ||
388 | * @buffer: where to find the data to be written | ||
389 | * @len: how much byte do we want to read | ||
390 | * @return: 0 in case of success | ||
391 | */ | ||
392 | int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) | ||
393 | { | ||
394 | struct i2c_msg msg; | ||
395 | u8 addr_bytes[3]; /* lowest...highest byte of data address */ | ||
396 | |||
397 | PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, " | ||
398 | "len=0x%02x)\n", chip, addr, alen, len)); | ||
399 | |||
400 | i2c_reset(); | ||
401 | |||
402 | /* chip address write */ | ||
403 | PRINTD(("i2c_write: chip address write\n")); | ||
404 | msg.condition = I2C_COND_START; | ||
405 | msg.acknack = I2C_ACKNAK_WAITACK; | ||
406 | msg.direction = I2C_WRITE; | ||
407 | msg.data = (chip << 1); | ||
408 | msg.data &= 0xFE; | ||
409 | if (i2c_transfer(&msg)) | ||
410 | return -1; | ||
411 | |||
412 | /* | ||
413 | * send memory address bytes; | ||
414 | * alen defines how much bytes we have to send. | ||
415 | */ | ||
416 | addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); | ||
417 | addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); | ||
418 | addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); | ||
419 | |||
420 | while (--alen >= 0) { | ||
421 | PRINTD(("i2c_write: send memory word address\n")); | ||
422 | msg.condition = I2C_COND_NORMAL; | ||
423 | msg.acknack = I2C_ACKNAK_WAITACK; | ||
424 | msg.direction = I2C_WRITE; | ||
425 | msg.data = addr_bytes[alen]; | ||
426 | if (i2c_transfer(&msg)) | ||
427 | return -1; | ||
428 | } | ||
429 | |||
430 | /* write bytes; send NACK at last byte */ | ||
431 | while (len--) { | ||
432 | PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n", | ||
433 | (unsigned int)buffer, *buffer)); | ||
434 | |||
435 | if (len == 0) | ||
436 | msg.condition = I2C_COND_STOP; | ||
437 | else | ||
438 | msg.condition = I2C_COND_NORMAL; | ||
439 | |||
440 | msg.acknack = I2C_ACKNAK_WAITACK; | ||
441 | msg.direction = I2C_WRITE; | ||
442 | msg.data = *(buffer++); | ||
443 | |||
444 | if (i2c_transfer(&msg)) | ||
445 | return -1; | ||
446 | } | ||
447 | |||
448 | i2c_reset(); | ||
449 | |||
450 | return 0; | ||
451 | } | ||
452 | #endif /* CONFIG_HARD_I2C */ | ||
453 |
include/configs/innokom.h
1 | /* | 1 | /* |
2 | * (C) Copyright 2000, 2001, 2002 | 2 | * (C) Copyright 2000, 2001, 2002 |
3 | * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de. | 3 | * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de. |
4 | * | 4 | * |
5 | * Configuration for the Auerswald Innokom CPU board. | 5 | * Configuration for the Auerswald Innokom CPU board. |
6 | * | 6 | * |
7 | * See file CREDITS for list of people who contributed to this | 7 | * See file CREDITS for list of people who contributed to this |
8 | * project. | 8 | * project. |
9 | * | 9 | * |
10 | * This program is free software; you can redistribute it and/or | 10 | * This program is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License as | 11 | * modify it under the terms of the GNU General Public License as |
12 | * published by the Free Software Foundation; either version 2 of | 12 | * published by the Free Software Foundation; either version 2 of |
13 | * the License, or (at your option) any later version. | 13 | * the License, or (at your option) any later version. |
14 | * | 14 | * |
15 | * This program is distributed in the hope that it will be useful, | 15 | * This program is distributed in the hope that it will be useful, |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
18 | * GNU General Public License for more details. | 18 | * GNU General Public License for more details. |
19 | * | 19 | * |
20 | * You should have received a copy of the GNU General Public License | 20 | * You should have received a copy of the GNU General Public License |
21 | * along with this program; if not, write to the Free Software | 21 | * along with this program; if not, write to the Free Software |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
23 | * MA 02111-1307 USA | 23 | * MA 02111-1307 USA |
24 | */ | 24 | */ |
25 | 25 | ||
26 | /* | 26 | /* |
27 | * include/configs/innokom.h - configuration options, board specific | 27 | * include/configs/innokom.h - configuration options, board specific |
28 | */ | 28 | */ |
29 | 29 | ||
30 | #ifndef __CONFIG_H | 30 | #ifndef __CONFIG_H |
31 | #define __CONFIG_H | 31 | #define __CONFIG_H |
32 | 32 | ||
33 | /* | 33 | /* |
34 | * High Level Configuration Options | 34 | * High Level Configuration Options |
35 | * (easy to change) | 35 | * (easy to change) |
36 | */ | 36 | */ |
37 | #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ | 37 | #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ |
38 | #define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */ | 38 | #define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */ |
39 | 39 | ||
40 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | 40 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
41 | /* for timer/console/ethernet */ | 41 | /* for timer/console/ethernet */ |
42 | 42 | ||
43 | #define CONFIG_SYS_TEXT_BASE 0x0 | 43 | #define CONFIG_SYS_TEXT_BASE 0x0 |
44 | 44 | ||
45 | /* we will never enable dcache, because we have to setup MMU first */ | 45 | /* we will never enable dcache, because we have to setup MMU first */ |
46 | #define CONFIG_SYS_NO_DCACHE | 46 | #define CONFIG_SYS_NO_DCACHE |
47 | 47 | ||
48 | /* | 48 | /* |
49 | * Hardware drivers | 49 | * Hardware drivers |
50 | */ | 50 | */ |
51 | 51 | ||
52 | /* | 52 | /* |
53 | * select serial console configuration | 53 | * select serial console configuration |
54 | */ | 54 | */ |
55 | #define CONFIG_PXA_SERIAL | 55 | #define CONFIG_PXA_SERIAL |
56 | #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ | 56 | #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ |
57 | 57 | ||
58 | /* allow to overwrite serial and ethaddr */ | 58 | /* allow to overwrite serial and ethaddr */ |
59 | #define CONFIG_ENV_OVERWRITE | 59 | #define CONFIG_ENV_OVERWRITE |
60 | 60 | ||
61 | #define CONFIG_BAUDRATE 19200 | 61 | #define CONFIG_BAUDRATE 19200 |
62 | #define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */ | 62 | #define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */ |
63 | 63 | ||
64 | 64 | ||
65 | /* | 65 | /* |
66 | * BOOTP options | 66 | * BOOTP options |
67 | */ | 67 | */ |
68 | #define CONFIG_BOOTP_BOOTFILESIZE | 68 | #define CONFIG_BOOTP_BOOTFILESIZE |
69 | #define CONFIG_BOOTP_BOOTPATH | 69 | #define CONFIG_BOOTP_BOOTPATH |
70 | #define CONFIG_BOOTP_GATEWAY | 70 | #define CONFIG_BOOTP_GATEWAY |
71 | #define CONFIG_BOOTP_HOSTNAME | 71 | #define CONFIG_BOOTP_HOSTNAME |
72 | 72 | ||
73 | 73 | ||
74 | /* | 74 | /* |
75 | * Command line configuration. | 75 | * Command line configuration. |
76 | */ | 76 | */ |
77 | 77 | ||
78 | #define CONFIG_CMD_ASKENV | 78 | #define CONFIG_CMD_ASKENV |
79 | #define CONFIG_CMD_BDI | 79 | #define CONFIG_CMD_BDI |
80 | #define CONFIG_CMD_CACHE | 80 | #define CONFIG_CMD_CACHE |
81 | #define CONFIG_CMD_DHCP | 81 | #define CONFIG_CMD_DHCP |
82 | #define CONFIG_CMD_ECHO | 82 | #define CONFIG_CMD_ECHO |
83 | #define CONFIG_CMD_SAVEENV | 83 | #define CONFIG_CMD_SAVEENV |
84 | #define CONFIG_CMD_FLASH | 84 | #define CONFIG_CMD_FLASH |
85 | #define CONFIG_CMD_I2C | 85 | #define CONFIG_CMD_I2C |
86 | #define CONFIG_CMD_IMI | 86 | #define CONFIG_CMD_IMI |
87 | #define CONFIG_CMD_LOADB | 87 | #define CONFIG_CMD_LOADB |
88 | #define CONFIG_CMD_MEMORY | 88 | #define CONFIG_CMD_MEMORY |
89 | #define CONFIG_CMD_NET | 89 | #define CONFIG_CMD_NET |
90 | #define CONFIG_CMD_RUN | 90 | #define CONFIG_CMD_RUN |
91 | 91 | ||
92 | 92 | ||
93 | #define CONFIG_BOOTDELAY 3 | 93 | #define CONFIG_BOOTDELAY 3 |
94 | /* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */ | 94 | /* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */ |
95 | #define CONFIG_BOOTARGS "console=ttyS0,19200" | 95 | #define CONFIG_BOOTARGS "console=ttyS0,19200" |
96 | #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF | 96 | #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF |
97 | #define CONFIG_NETMASK 255.255.255.0 | 97 | #define CONFIG_NETMASK 255.255.255.0 |
98 | #define CONFIG_IPADDR 192.168.1.56 | 98 | #define CONFIG_IPADDR 192.168.1.56 |
99 | #define CONFIG_SERVERIP 192.168.1.2 | 99 | #define CONFIG_SERVERIP 192.168.1.2 |
100 | #define CONFIG_BOOTCOMMAND "bootm 0x40000" | 100 | #define CONFIG_BOOTCOMMAND "bootm 0x40000" |
101 | #define CONFIG_SHOW_BOOT_PROGRESS | 101 | #define CONFIG_SHOW_BOOT_PROGRESS |
102 | 102 | ||
103 | #define CONFIG_CMDLINE_TAG 1 | 103 | #define CONFIG_CMDLINE_TAG 1 |
104 | 104 | ||
105 | /* | 105 | /* |
106 | * Miscellaneous configurable options | 106 | * Miscellaneous configurable options |
107 | */ | 107 | */ |
108 | 108 | ||
109 | /* | 109 | /* |
110 | * Size of malloc() pool | 110 | * Size of malloc() pool |
111 | */ | 111 | */ |
112 | #define CONFIG_SYS_MALLOC_LEN (256*1024) | 112 | #define CONFIG_SYS_MALLOC_LEN (256*1024) |
113 | 113 | ||
114 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | 114 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
115 | #define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */ | 115 | #define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */ |
116 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | 116 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
117 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | 117 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
118 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | 118 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
119 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | 119 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
120 | 120 | ||
121 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ | 121 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
122 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | 122 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ |
123 | 123 | ||
124 | #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */ | 124 | #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */ |
125 | 125 | ||
126 | #define CONFIG_SYS_HZ 1000 | 126 | #define CONFIG_SYS_HZ 1000 |
127 | /* RS: the oscillator is actually 3680130?? */ | 127 | /* RS: the oscillator is actually 3680130?? */ |
128 | 128 | ||
129 | #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ | 129 | #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ |
130 | /* 0101000001 */ | 130 | /* 0101000001 */ |
131 | /* ^^^^^ Memory Speed 99.53 MHz */ | 131 | /* ^^^^^ Memory Speed 99.53 MHz */ |
132 | /* ^^ Run Mode Speed = 2x Mem Speed */ | 132 | /* ^^ Run Mode Speed = 2x Mem Speed */ |
133 | /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ | 133 | /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ |
134 | 134 | ||
135 | #define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */ | 135 | #define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */ |
136 | 136 | ||
137 | /* valid baudrates */ | 137 | /* valid baudrates */ |
138 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | 138 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
139 | 139 | ||
140 | /* | 140 | /* |
141 | * I2C bus | 141 | * I2C bus |
142 | */ | 142 | */ |
143 | #define CONFIG_I2C_MV 1 | ||
143 | #define CONFIG_HARD_I2C 1 | 144 | #define CONFIG_HARD_I2C 1 |
144 | #define CONFIG_SYS_I2C_SPEED 50000 | 145 | #define CONFIG_SYS_I2C_SPEED 50000 |
145 | #define CONFIG_SYS_I2C_SLAVE 0xfe | 146 | #define CONFIG_SYS_I2C_SLAVE 0xfe |
146 | 147 | ||
147 | #define CONFIG_ENV_IS_IN_EEPROM 1 | 148 | #define CONFIG_ENV_IS_IN_EEPROM 1 |
148 | 149 | ||
149 | #define CONFIG_ENV_OFFSET 0x00 /* environment starts here */ | 150 | #define CONFIG_ENV_OFFSET 0x00 /* environment starts here */ |
150 | #define CONFIG_ENV_SIZE 1024 /* 1 KiB */ | 151 | #define CONFIG_ENV_SIZE 1024 /* 1 KiB */ |
151 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */ | 152 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */ |
152 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ | 153 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ |
153 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */ | 154 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */ |
154 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* length of address */ | 155 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* length of address */ |
155 | #define CONFIG_SYS_EEPROM_SIZE 4096 /* size in bytes */ | 156 | #define CONFIG_SYS_EEPROM_SIZE 4096 /* size in bytes */ |
156 | #define CONFIG_SYS_I2C_INIT_BOARD 1 /* board has it's own init */ | 157 | #define CONFIG_SYS_I2C_INIT_BOARD 1 /* board has it's own init */ |
157 | 158 | ||
158 | /* | 159 | /* |
159 | * SMSC91C111 Network Card | 160 | * SMSC91C111 Network Card |
160 | */ | 161 | */ |
161 | #define CONFIG_NET_MULTI | 162 | #define CONFIG_NET_MULTI |
162 | #define CONFIG_SMC91111 1 | 163 | #define CONFIG_SMC91111 1 |
163 | #define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */ | 164 | #define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */ |
164 | #undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */ | 165 | #undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */ |
165 | #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ | 166 | #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ |
166 | #define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */ | 167 | #define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */ |
167 | #undef CONFIG_SHOW_ACTIVITY | 168 | #undef CONFIG_SHOW_ACTIVITY |
168 | #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ | 169 | #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ |
169 | 170 | ||
170 | /* | 171 | /* |
171 | * Stack sizes | 172 | * Stack sizes |
172 | * | 173 | * |
173 | * The stack sizes are set up in start.S using the settings below | 174 | * The stack sizes are set up in start.S using the settings below |
174 | */ | 175 | */ |
175 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | 176 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
176 | #ifdef CONFIG_USE_IRQ | 177 | #ifdef CONFIG_USE_IRQ |
177 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | 178 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
178 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | 179 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
179 | #endif | 180 | #endif |
180 | 181 | ||
181 | /* | 182 | /* |
182 | * Physical Memory Map | 183 | * Physical Memory Map |
183 | */ | 184 | */ |
184 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | 185 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
185 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | 186 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
186 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | 187 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ |
187 | 188 | ||
188 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | 189 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
189 | #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ | 190 | #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ |
190 | 191 | ||
191 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */ | 192 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */ |
192 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 | 193 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 |
193 | 194 | ||
194 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | 195 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
195 | 196 | ||
196 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | 197 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
197 | #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) | 198 | #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) |
198 | 199 | ||
199 | /* | 200 | /* |
200 | * JFFS2 partitions | 201 | * JFFS2 partitions |
201 | * | 202 | * |
202 | */ | 203 | */ |
203 | /* development flash */ | 204 | /* development flash */ |
204 | #define CONFIG_MTD_INNOKOM_16MB 1 | 205 | #define CONFIG_MTD_INNOKOM_16MB 1 |
205 | #undef CONFIG_MTD_INNOKOM_64MB | 206 | #undef CONFIG_MTD_INNOKOM_64MB |
206 | 207 | ||
207 | /* production flash */ | 208 | /* production flash */ |
208 | /* | 209 | /* |
209 | #define CONFIG_MTD_INNOKOM_64MB 1 | 210 | #define CONFIG_MTD_INNOKOM_64MB 1 |
210 | #undef CONFIG_MTD_INNOKOM_16MB | 211 | #undef CONFIG_MTD_INNOKOM_16MB |
211 | */ | 212 | */ |
212 | 213 | ||
213 | /* No command line, one static partition, whole device */ | 214 | /* No command line, one static partition, whole device */ |
214 | #undef CONFIG_CMD_MTDPARTS | 215 | #undef CONFIG_CMD_MTDPARTS |
215 | #define CONFIG_JFFS2_DEV "nor0" | 216 | #define CONFIG_JFFS2_DEV "nor0" |
216 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | 217 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF |
217 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | 218 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 |
218 | 219 | ||
219 | /* mtdparts command line support */ | 220 | /* mtdparts command line support */ |
220 | /* Note: fake mtd_id used, no linux mtd map file */ | 221 | /* Note: fake mtd_id used, no linux mtd map file */ |
221 | /* | 222 | /* |
222 | #define CONFIG_CMD_MTDPARTS | 223 | #define CONFIG_CMD_MTDPARTS |
223 | #define MTDIDS_DEFAULT "nor0=innokom-0" | 224 | #define MTDIDS_DEFAULT "nor0=innokom-0" |
224 | */ | 225 | */ |
225 | 226 | ||
226 | /* development flash */ | 227 | /* development flash */ |
227 | /* | 228 | /* |
228 | #define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)" | 229 | #define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)" |
229 | */ | 230 | */ |
230 | 231 | ||
231 | /* production flash */ | 232 | /* production flash */ |
232 | /* | 233 | /* |
233 | #define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)" | 234 | #define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)" |
234 | */ | 235 | */ |
235 | 236 | ||
236 | /* | 237 | /* |
237 | * GPIO settings | 238 | * GPIO settings |
238 | * | 239 | * |
239 | * GP15 == nCS1 is 1 | 240 | * GP15 == nCS1 is 1 |
240 | * GP24 == SFRM is 1 | 241 | * GP24 == SFRM is 1 |
241 | * GP25 == TXD is 1 | 242 | * GP25 == TXD is 1 |
242 | * GP33 == nCS5 is 1 | 243 | * GP33 == nCS5 is 1 |
243 | * GP39 == FFTXD is 1 | 244 | * GP39 == FFTXD is 1 |
244 | * GP41 == RTS is 1 | 245 | * GP41 == RTS is 1 |
245 | * GP47 == TXD is 1 | 246 | * GP47 == TXD is 1 |
246 | * GP49 == nPWE is 1 | 247 | * GP49 == nPWE is 1 |
247 | * GP62 == LED_B is 1 | 248 | * GP62 == LED_B is 1 |
248 | * GP63 == TDM_OE is 1 | 249 | * GP63 == TDM_OE is 1 |
249 | * GP78 == nCS2 is 1 | 250 | * GP78 == nCS2 is 1 |
250 | * GP79 == nCS3 is 1 | 251 | * GP79 == nCS3 is 1 |
251 | * GP80 == nCS4 is 1 | 252 | * GP80 == nCS4 is 1 |
252 | */ | 253 | */ |
253 | #define CONFIG_SYS_GPSR0_VAL 0x03008000 | 254 | #define CONFIG_SYS_GPSR0_VAL 0x03008000 |
254 | #define CONFIG_SYS_GPSR1_VAL 0xC0028282 | 255 | #define CONFIG_SYS_GPSR1_VAL 0xC0028282 |
255 | #define CONFIG_SYS_GPSR2_VAL 0x0001C000 | 256 | #define CONFIG_SYS_GPSR2_VAL 0x0001C000 |
256 | 257 | ||
257 | /* GP02 == DON_RST is 0 | 258 | /* GP02 == DON_RST is 0 |
258 | * GP23 == SCLK is 0 | 259 | * GP23 == SCLK is 0 |
259 | * GP45 == USB_ACT is 0 | 260 | * GP45 == USB_ACT is 0 |
260 | * GP60 == PLLEN is 0 | 261 | * GP60 == PLLEN is 0 |
261 | * GP61 == LED_A is 0 | 262 | * GP61 == LED_A is 0 |
262 | * GP73 == SWUPD_LED is 0 | 263 | * GP73 == SWUPD_LED is 0 |
263 | */ | 264 | */ |
264 | #define CONFIG_SYS_GPCR0_VAL 0x00800004 | 265 | #define CONFIG_SYS_GPCR0_VAL 0x00800004 |
265 | #define CONFIG_SYS_GPCR1_VAL 0x30002000 | 266 | #define CONFIG_SYS_GPCR1_VAL 0x30002000 |
266 | #define CONFIG_SYS_GPCR2_VAL 0x00000100 | 267 | #define CONFIG_SYS_GPCR2_VAL 0x00000100 |
267 | 268 | ||
268 | /* GP00 == DON_READY is input | 269 | /* GP00 == DON_READY is input |
269 | * GP01 == DON_OK is input | 270 | * GP01 == DON_OK is input |
270 | * GP02 == DON_RST is output | 271 | * GP02 == DON_RST is output |
271 | * GP03 == RESET_IND is input | 272 | * GP03 == RESET_IND is input |
272 | * GP07 == RES11 is input | 273 | * GP07 == RES11 is input |
273 | * GP09 == RES12 is input | 274 | * GP09 == RES12 is input |
274 | * GP11 == SWUPDATE is input | 275 | * GP11 == SWUPDATE is input |
275 | * GP14 == nPOWEROK is input | 276 | * GP14 == nPOWEROK is input |
276 | * GP15 == nCS1 is output | 277 | * GP15 == nCS1 is output |
277 | * GP17 == RES22 is input | 278 | * GP17 == RES22 is input |
278 | * GP18 == RDY is input | 279 | * GP18 == RDY is input |
279 | * GP23 == SCLK is output | 280 | * GP23 == SCLK is output |
280 | * GP24 == SFRM is output | 281 | * GP24 == SFRM is output |
281 | * GP25 == TXD is output | 282 | * GP25 == TXD is output |
282 | * GP26 == RXD is input | 283 | * GP26 == RXD is input |
283 | * GP32 == RES21 is input | 284 | * GP32 == RES21 is input |
284 | * GP33 == nCS5 is output | 285 | * GP33 == nCS5 is output |
285 | * GP34 == FFRXD is input | 286 | * GP34 == FFRXD is input |
286 | * GP35 == CTS is input | 287 | * GP35 == CTS is input |
287 | * GP39 == FFTXD is output | 288 | * GP39 == FFTXD is output |
288 | * GP41 == RTS is output | 289 | * GP41 == RTS is output |
289 | * GP42 == USB_OK is input | 290 | * GP42 == USB_OK is input |
290 | * GP45 == USB_ACT is output | 291 | * GP45 == USB_ACT is output |
291 | * GP46 == RXD is input | 292 | * GP46 == RXD is input |
292 | * GP47 == TXD is output | 293 | * GP47 == TXD is output |
293 | * GP49 == nPWE is output | 294 | * GP49 == nPWE is output |
294 | * GP58 == nCPUBUSINT is input | 295 | * GP58 == nCPUBUSINT is input |
295 | * GP59 == LANINT is input | 296 | * GP59 == LANINT is input |
296 | * GP60 == PLLEN is output | 297 | * GP60 == PLLEN is output |
297 | * GP61 == LED_A is output | 298 | * GP61 == LED_A is output |
298 | * GP62 == LED_B is output | 299 | * GP62 == LED_B is output |
299 | * GP63 == TDM_OE is output | 300 | * GP63 == TDM_OE is output |
300 | * GP64 == nDSPINT is input | 301 | * GP64 == nDSPINT is input |
301 | * GP65 == STRAP0 is input | 302 | * GP65 == STRAP0 is input |
302 | * GP67 == STRAP1 is input | 303 | * GP67 == STRAP1 is input |
303 | * GP69 == STRAP2 is input | 304 | * GP69 == STRAP2 is input |
304 | * GP70 == STRAP3 is input | 305 | * GP70 == STRAP3 is input |
305 | * GP71 == STRAP4 is input | 306 | * GP71 == STRAP4 is input |
306 | * GP73 == SWUPD_LED is output | 307 | * GP73 == SWUPD_LED is output |
307 | * GP78 == nCS2 is output | 308 | * GP78 == nCS2 is output |
308 | * GP79 == nCS3 is output | 309 | * GP79 == nCS3 is output |
309 | * GP80 == nCS4 is output | 310 | * GP80 == nCS4 is output |
310 | */ | 311 | */ |
311 | #define CONFIG_SYS_GPDR0_VAL 0x03808004 | 312 | #define CONFIG_SYS_GPDR0_VAL 0x03808004 |
312 | #define CONFIG_SYS_GPDR1_VAL 0xF002A282 | 313 | #define CONFIG_SYS_GPDR1_VAL 0xF002A282 |
313 | #define CONFIG_SYS_GPDR2_VAL 0x0001C200 | 314 | #define CONFIG_SYS_GPDR2_VAL 0x0001C200 |
314 | 315 | ||
315 | /* GP15 == nCS1 is AF10 | 316 | /* GP15 == nCS1 is AF10 |
316 | * GP18 == RDY is AF01 | 317 | * GP18 == RDY is AF01 |
317 | * GP23 == SCLK is AF10 | 318 | * GP23 == SCLK is AF10 |
318 | * GP24 == SFRM is AF10 | 319 | * GP24 == SFRM is AF10 |
319 | * GP25 == TXD is AF10 | 320 | * GP25 == TXD is AF10 |
320 | * GP26 == RXD is AF01 | 321 | * GP26 == RXD is AF01 |
321 | * GP33 == nCS5 is AF10 | 322 | * GP33 == nCS5 is AF10 |
322 | * GP34 == FFRXD is AF01 | 323 | * GP34 == FFRXD is AF01 |
323 | * GP35 == CTS is AF01 | 324 | * GP35 == CTS is AF01 |
324 | * GP39 == FFTXD is AF10 | 325 | * GP39 == FFTXD is AF10 |
325 | * GP41 == RTS is AF10 | 326 | * GP41 == RTS is AF10 |
326 | * GP46 == RXD is AF10 | 327 | * GP46 == RXD is AF10 |
327 | * GP47 == TXD is AF01 | 328 | * GP47 == TXD is AF01 |
328 | * GP49 == nPWE is AF10 | 329 | * GP49 == nPWE is AF10 |
329 | * GP78 == nCS2 is AF10 | 330 | * GP78 == nCS2 is AF10 |
330 | * GP79 == nCS3 is AF10 | 331 | * GP79 == nCS3 is AF10 |
331 | * GP80 == nCS4 is AF10 | 332 | * GP80 == nCS4 is AF10 |
332 | */ | 333 | */ |
333 | #define CONFIG_SYS_GAFR0_L_VAL 0x80000000 | 334 | #define CONFIG_SYS_GAFR0_L_VAL 0x80000000 |
334 | #define CONFIG_SYS_GAFR0_U_VAL 0x001A8010 | 335 | #define CONFIG_SYS_GAFR0_U_VAL 0x001A8010 |
335 | #define CONFIG_SYS_GAFR1_L_VAL 0x60088058 | 336 | #define CONFIG_SYS_GAFR1_L_VAL 0x60088058 |
336 | #define CONFIG_SYS_GAFR1_U_VAL 0x00000008 | 337 | #define CONFIG_SYS_GAFR1_U_VAL 0x00000008 |
337 | #define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 | 338 | #define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 |
338 | #define CONFIG_SYS_GAFR2_U_VAL 0x00000002 | 339 | #define CONFIG_SYS_GAFR2_U_VAL 0x00000002 |
339 | 340 | ||
340 | 341 | ||
341 | /* FIXME: set GPIO_RER/FER */ | 342 | /* FIXME: set GPIO_RER/FER */ |
342 | 343 | ||
343 | /* RDH = 1 | 344 | /* RDH = 1 |
344 | * PH = 1 | 345 | * PH = 1 |
345 | * VFS = 1 | 346 | * VFS = 1 |
346 | * BFS = 1 | 347 | * BFS = 1 |
347 | * SSS = 1 | 348 | * SSS = 1 |
348 | */ | 349 | */ |
349 | #define CONFIG_SYS_PSSR_VAL 0x37 | 350 | #define CONFIG_SYS_PSSR_VAL 0x37 |
350 | 351 | ||
351 | #define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 | 352 | #define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 |
352 | #define CONFIG_SYS_CKEN 0x0 | 353 | #define CONFIG_SYS_CKEN 0x0 |
353 | 354 | ||
354 | /* | 355 | /* |
355 | * Memory settings | 356 | * Memory settings |
356 | * | 357 | * |
357 | * This is the configuration for nCS0/1 -> flash banks | 358 | * This is the configuration for nCS0/1 -> flash banks |
358 | * configuration for nCS1: | 359 | * configuration for nCS1: |
359 | * [31] 0 - Slower Device | 360 | * [31] 0 - Slower Device |
360 | * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns | 361 | * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns |
361 | * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns | 362 | * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns |
362 | * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns | 363 | * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns |
363 | * [19] 1 - 16 Bit bus width | 364 | * [19] 1 - 16 Bit bus width |
364 | * [18:16] 000 - nonburst RAM or FLASH | 365 | * [18:16] 000 - nonburst RAM or FLASH |
365 | * configuration for nCS0: | 366 | * configuration for nCS0: |
366 | * [15] 0 - Slower Device | 367 | * [15] 0 - Slower Device |
367 | * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns | 368 | * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns |
368 | * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns | 369 | * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns |
369 | * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns | 370 | * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns |
370 | * [03] 1 - 16 Bit bus width | 371 | * [03] 1 - 16 Bit bus width |
371 | * [02:00] 000 - nonburst RAM or FLASH | 372 | * [02:00] 000 - nonburst RAM or FLASH |
372 | */ | 373 | */ |
373 | #define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */ | 374 | #define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */ |
374 | 375 | ||
375 | /* This is the configuration for nCS2/3 -> TDM-Switch, DSP | 376 | /* This is the configuration for nCS2/3 -> TDM-Switch, DSP |
376 | * configuration for nCS3: DSP | 377 | * configuration for nCS3: DSP |
377 | * [31] 0 - Slower Device | 378 | * [31] 0 - Slower Device |
378 | * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns | 379 | * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns |
379 | * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns | 380 | * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns |
380 | * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns | 381 | * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns |
381 | * [19] 1 - 16 Bit bus width | 382 | * [19] 1 - 16 Bit bus width |
382 | * [18:16] 100 - variable latency I/O | 383 | * [18:16] 100 - variable latency I/O |
383 | * configuration for nCS2: TDM-Switch | 384 | * configuration for nCS2: TDM-Switch |
384 | * [15] 0 - Slower Device | 385 | * [15] 0 - Slower Device |
385 | * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns | 386 | * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns |
386 | * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns | 387 | * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns |
387 | * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns | 388 | * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns |
388 | * [03] 1 - 16 Bit bus width | 389 | * [03] 1 - 16 Bit bus width |
389 | * [02:00] 100 - variable latency I/O | 390 | * [02:00] 100 - variable latency I/O |
390 | */ | 391 | */ |
391 | #define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */ | 392 | #define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */ |
392 | 393 | ||
393 | /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller | 394 | /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller |
394 | * | 395 | * |
395 | * configuration for nCS5: LAN Controller | 396 | * configuration for nCS5: LAN Controller |
396 | * [31] 0 - Slower Device | 397 | * [31] 0 - Slower Device |
397 | * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns | 398 | * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns |
398 | * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns | 399 | * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns |
399 | * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns | 400 | * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns |
400 | * [19] 1 - 16 Bit bus width | 401 | * [19] 1 - 16 Bit bus width |
401 | * [18:16] 100 - variable latency I/O | 402 | * [18:16] 100 - variable latency I/O |
402 | * configuration for nCS4: ExtBus | 403 | * configuration for nCS4: ExtBus |
403 | * [15] 0 - Slower Device | 404 | * [15] 0 - Slower Device |
404 | * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns | 405 | * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns |
405 | * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns | 406 | * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns |
406 | * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns | 407 | * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns |
407 | * [03] 1 - 16 Bit bus width | 408 | * [03] 1 - 16 Bit bus width |
408 | * [02:00] 100 - variable latency I/O | 409 | * [02:00] 100 - variable latency I/O |
409 | */ | 410 | */ |
410 | #define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */ | 411 | #define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */ |
411 | 412 | ||
412 | /* MDCNFG: SDRAM Configuration Register | 413 | /* MDCNFG: SDRAM Configuration Register |
413 | * | 414 | * |
414 | * [31:29] 000 - reserved | 415 | * [31:29] 000 - reserved |
415 | * [28] 0 - no SA1111 compatiblity mode | 416 | * [28] 0 - no SA1111 compatiblity mode |
416 | * [27] 0 - latch return data with return clock | 417 | * [27] 0 - latch return data with return clock |
417 | * [26] 0 - alternate addressing for pair 2/3 | 418 | * [26] 0 - alternate addressing for pair 2/3 |
418 | * [25:24] 00 - timings | 419 | * [25:24] 00 - timings |
419 | * [23] 0 - internal banks in lower partition 2/3 (not used) | 420 | * [23] 0 - internal banks in lower partition 2/3 (not used) |
420 | * [22:21] 00 - row address bits for partition 2/3 (not used) | 421 | * [22:21] 00 - row address bits for partition 2/3 (not used) |
421 | * [20:19] 00 - column address bits for partition 2/3 (not used) | 422 | * [20:19] 00 - column address bits for partition 2/3 (not used) |
422 | * [18] 0 - SDRAM partition 2/3 width is 32 bit | 423 | * [18] 0 - SDRAM partition 2/3 width is 32 bit |
423 | * [17] 0 - SDRAM partition 3 disabled | 424 | * [17] 0 - SDRAM partition 3 disabled |
424 | * [16] 0 - SDRAM partition 2 disabled | 425 | * [16] 0 - SDRAM partition 2 disabled |
425 | * [15:13] 000 - reserved | 426 | * [15:13] 000 - reserved |
426 | * [12] 1 - SA1111 compatiblity mode | 427 | * [12] 1 - SA1111 compatiblity mode |
427 | * [11] 1 - latch return data with return clock | 428 | * [11] 1 - latch return data with return clock |
428 | * [10] 0 - no alternate addressing for pair 0/1 | 429 | * [10] 0 - no alternate addressing for pair 0/1 |
429 | * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk | 430 | * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk |
430 | * [7] 1 - 4 internal banks in lower partition pair | 431 | * [7] 1 - 4 internal banks in lower partition pair |
431 | * [06:05] 10 - 13 row address bits for partition 0/1 | 432 | * [06:05] 10 - 13 row address bits for partition 0/1 |
432 | * [04:03] 01 - 9 column address bits for partition 0/1 | 433 | * [04:03] 01 - 9 column address bits for partition 0/1 |
433 | * [02] 0 - SDRAM partition 0/1 width is 32 bit | 434 | * [02] 0 - SDRAM partition 0/1 width is 32 bit |
434 | * [01] 0 - disable SDRAM partition 1 | 435 | * [01] 0 - disable SDRAM partition 1 |
435 | * [00] 1 - enable SDRAM partition 0 | 436 | * [00] 1 - enable SDRAM partition 0 |
436 | */ | 437 | */ |
437 | /* use the configuration above but disable partition 0 */ | 438 | /* use the configuration above but disable partition 0 */ |
438 | #define CONFIG_SYS_MDCNFG_VAL 0x000019c8 | 439 | #define CONFIG_SYS_MDCNFG_VAL 0x000019c8 |
439 | 440 | ||
440 | /* MDREFR: SDRAM Refresh Control Register | 441 | /* MDREFR: SDRAM Refresh Control Register |
441 | * | 442 | * |
442 | * [32:26] 0 - reserved | 443 | * [32:26] 0 - reserved |
443 | * [25] 0 - K2FREE: not free running | 444 | * [25] 0 - K2FREE: not free running |
444 | * [24] 0 - K1FREE: not free running | 445 | * [24] 0 - K1FREE: not free running |
445 | * [23] 1 - K0FREE: not free running | 446 | * [23] 1 - K0FREE: not free running |
446 | * [22] 0 - SLFRSH: self refresh disabled | 447 | * [22] 0 - SLFRSH: self refresh disabled |
447 | * [21] 0 - reserved | 448 | * [21] 0 - reserved |
448 | * [20] 0 - APD: no auto power down | 449 | * [20] 0 - APD: no auto power down |
449 | * [19] 0 - K2DB2: SDCLK2 is MemClk | 450 | * [19] 0 - K2DB2: SDCLK2 is MemClk |
450 | * [18] 0 - K2RUN: disable SDCLK2 | 451 | * [18] 0 - K2RUN: disable SDCLK2 |
451 | * [17] 0 - K1DB2: SDCLK1 is MemClk | 452 | * [17] 0 - K1DB2: SDCLK1 is MemClk |
452 | * [16] 1 - K1RUN: enable SDCLK1 | 453 | * [16] 1 - K1RUN: enable SDCLK1 |
453 | * [15] 1 - E1PIN: SDRAM clock enable | 454 | * [15] 1 - E1PIN: SDRAM clock enable |
454 | * [14] 1 - K0DB2: SDCLK0 is MemClk | 455 | * [14] 1 - K0DB2: SDCLK0 is MemClk |
455 | * [13] 0 - K0RUN: disable SDCLK0 | 456 | * [13] 0 - K0RUN: disable SDCLK0 |
456 | * [12] 1 - E0PIN: disable SDCKE0 | 457 | * [12] 1 - E0PIN: disable SDCKE0 |
457 | * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 | 458 | * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 |
458 | */ | 459 | */ |
459 | #define CONFIG_SYS_MDREFR_VAL 0x0081D018 | 460 | #define CONFIG_SYS_MDREFR_VAL 0x0081D018 |
460 | 461 | ||
461 | /* MDMRS: Mode Register Set Configuration Register | 462 | /* MDMRS: Mode Register Set Configuration Register |
462 | * | 463 | * |
463 | * [31] 0 - reserved | 464 | * [31] 0 - reserved |
464 | * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) | 465 | * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) |
465 | * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) | 466 | * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) |
466 | * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) | 467 | * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) |
467 | * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) | 468 | * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) |
468 | * [15] 0 - reserved | 469 | * [15] 0 - reserved |
469 | * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. | 470 | * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. |
470 | * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. | 471 | * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. |
471 | * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. | 472 | * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. |
472 | * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. | 473 | * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. |
473 | */ | 474 | */ |
474 | #define CONFIG_SYS_MDMRS_VAL 0x00020022 | 475 | #define CONFIG_SYS_MDMRS_VAL 0x00020022 |
475 | 476 | ||
476 | /* | 477 | /* |
477 | * PCMCIA and CF Interfaces | 478 | * PCMCIA and CF Interfaces |
478 | */ | 479 | */ |
479 | #define CONFIG_SYS_MECR_VAL 0x00000000 | 480 | #define CONFIG_SYS_MECR_VAL 0x00000000 |
480 | #define CONFIG_SYS_MCMEM0_VAL 0x00000000 | 481 | #define CONFIG_SYS_MCMEM0_VAL 0x00000000 |
481 | #define CONFIG_SYS_MCMEM1_VAL 0x00000000 | 482 | #define CONFIG_SYS_MCMEM1_VAL 0x00000000 |
482 | #define CONFIG_SYS_MCATT0_VAL 0x00000000 | 483 | #define CONFIG_SYS_MCATT0_VAL 0x00000000 |
483 | #define CONFIG_SYS_MCATT1_VAL 0x00000000 | 484 | #define CONFIG_SYS_MCATT1_VAL 0x00000000 |
484 | #define CONFIG_SYS_MCIO0_VAL 0x00000000 | 485 | #define CONFIG_SYS_MCIO0_VAL 0x00000000 |
485 | #define CONFIG_SYS_MCIO1_VAL 0x00000000 | 486 | #define CONFIG_SYS_MCIO1_VAL 0x00000000 |
486 | 487 | ||
487 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 | 488 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 |
488 | #define CONFIG_SYS_SXCNFG_VAL 0x00000000 | 489 | #define CONFIG_SYS_SXCNFG_VAL 0x00000000 |
489 | 490 | ||
490 | /* | 491 | /* |
491 | #define CSB226_USER_LED0 0x00000008 | 492 | #define CSB226_USER_LED0 0x00000008 |
492 | #define CSB226_USER_LED1 0x00000010 | 493 | #define CSB226_USER_LED1 0x00000010 |
493 | #define CSB226_USER_LED2 0x00000020 | 494 | #define CSB226_USER_LED2 0x00000020 |
494 | */ | 495 | */ |
495 | 496 | ||
496 | /* | 497 | /* |
497 | * FLASH and environment organization | 498 | * FLASH and environment organization |
498 | */ | 499 | */ |
499 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | 500 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
500 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */ | 501 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */ |
501 | 502 | ||
502 | /* timeout values are in ticks */ | 503 | /* timeout values are in ticks */ |
503 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ | 504 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
504 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | 505 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
505 | 506 | ||
506 | #endif /* __CONFIG_H */ | 507 | #endif /* __CONFIG_H */ |
507 | 508 |
include/configs/xm250.h
1 | /* | 1 | /* |
2 | * (C) Copyright 2002 | 2 | * (C) Copyright 2002 |
3 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | 3 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
4 | * | 4 | * |
5 | * (C) Copyright 2002 | 5 | * (C) Copyright 2002 |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | 6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
7 | * Marius Groeger <mgroeger@sysgo.de> | 7 | * Marius Groeger <mgroeger@sysgo.de> |
8 | * | 8 | * |
9 | * See file CREDITS for list of people who contributed to this | 9 | * See file CREDITS for list of people who contributed to this |
10 | * project. | 10 | * project. |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License as | 13 | * modify it under the terms of the GNU General Public License as |
14 | * published by the Free Software Foundation; either version 2 of | 14 | * published by the Free Software Foundation; either version 2 of |
15 | * the License, or (at your option) any later version. | 15 | * the License, or (at your option) any later version. |
16 | * | 16 | * |
17 | * This program is distributed in the hope that it will be useful, | 17 | * This program is distributed in the hope that it will be useful, |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
20 | * GNU General Public License for more details. | 20 | * GNU General Public License for more details. |
21 | * | 21 | * |
22 | * You should have received a copy of the GNU General Public License | 22 | * You should have received a copy of the GNU General Public License |
23 | * along with this program; if not, write to the Free Software | 23 | * along with this program; if not, write to the Free Software |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
25 | * MA 02111-1307 USA | 25 | * MA 02111-1307 USA |
26 | */ | 26 | */ |
27 | 27 | ||
28 | #ifndef __CONFIG_H | 28 | #ifndef __CONFIG_H |
29 | #define __CONFIG_H | 29 | #define __CONFIG_H |
30 | 30 | ||
31 | /* | 31 | /* |
32 | * High Level Configuration Options | 32 | * High Level Configuration Options |
33 | * (easy to change) | 33 | * (easy to change) |
34 | */ | 34 | */ |
35 | #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ | 35 | #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ |
36 | #define CONFIG_XM250 1 /* on a MicroSys XM250 Board */ | 36 | #define CONFIG_XM250 1 /* on a MicroSys XM250 Board */ |
37 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | 37 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
38 | #define CONFIG_SYS_TEXT_BASE 0x0 | 38 | #define CONFIG_SYS_TEXT_BASE 0x0 |
39 | 39 | ||
40 | /* we will never enable dcache, because we have to setup MMU first */ | 40 | /* we will never enable dcache, because we have to setup MMU first */ |
41 | #define CONFIG_SYS_NO_DCACHE | 41 | #define CONFIG_SYS_NO_DCACHE |
42 | 42 | ||
43 | /* | 43 | /* |
44 | * Size of malloc() pool; this lives below the uppermost 128 KiB which are | 44 | * Size of malloc() pool; this lives below the uppermost 128 KiB which are |
45 | * used for the RAM copy of the uboot code | 45 | * used for the RAM copy of the uboot code |
46 | * | 46 | * |
47 | */ | 47 | */ |
48 | #define CONFIG_SYS_MALLOC_LEN (256*1024) | 48 | #define CONFIG_SYS_MALLOC_LEN (256*1024) |
49 | 49 | ||
50 | /* | 50 | /* |
51 | * Hardware drivers | 51 | * Hardware drivers |
52 | */ | 52 | */ |
53 | #define CONFIG_NET_MULTI | 53 | #define CONFIG_NET_MULTI |
54 | #define CONFIG_SMC91111 | 54 | #define CONFIG_SMC91111 |
55 | #define CONFIG_SMC91111_BASE 0x04000300 | 55 | #define CONFIG_SMC91111_BASE 0x04000300 |
56 | #undef CONFIG_SMC91111_EXT_PHY | 56 | #undef CONFIG_SMC91111_EXT_PHY |
57 | #define CONFIG_SMC_USE_32_BIT | 57 | #define CONFIG_SMC_USE_32_BIT |
58 | #undef CONFIG_SHOW_ACTIVITY | 58 | #undef CONFIG_SHOW_ACTIVITY |
59 | #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ | 59 | #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ |
60 | 60 | ||
61 | /* | 61 | /* |
62 | * I2C bus | 62 | * I2C bus |
63 | */ | 63 | */ |
64 | #define CONFIG_I2C_MV 1 | ||
64 | #define CONFIG_HARD_I2C 1 | 65 | #define CONFIG_HARD_I2C 1 |
65 | #define CONFIG_SYS_I2C_SPEED 50000 | 66 | #define CONFIG_SYS_I2C_SPEED 50000 |
66 | #define CONFIG_SYS_I2C_SLAVE 0xfe | 67 | #define CONFIG_SYS_I2C_SLAVE 0xfe |
67 | 68 | ||
68 | #define CONFIG_RTC_PCF8563 1 | 69 | #define CONFIG_RTC_PCF8563 1 |
69 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 | 70 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
70 | 71 | ||
71 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* A0 = 0 (hardwired) */ | 72 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* A0 = 0 (hardwired) */ |
72 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 4 bits = 16 octets */ | 73 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 4 bits = 16 octets */ |
73 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */ | 74 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */ |
74 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* length of address */ | 75 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* length of address */ |
75 | #define CONFIG_SYS_EEPROM_SIZE 2048 /* size in bytes */ | 76 | #define CONFIG_SYS_EEPROM_SIZE 2048 /* size in bytes */ |
76 | #undef CONFIG_SYS_I2C_INIT_BOARD /* board has no own init */ | 77 | #undef CONFIG_SYS_I2C_INIT_BOARD /* board has no own init */ |
77 | 78 | ||
78 | /* | 79 | /* |
79 | * select serial console configuration | 80 | * select serial console configuration |
80 | */ | 81 | */ |
81 | #define CONFIG_PXA_SERIAL | 82 | #define CONFIG_PXA_SERIAL |
82 | #define CONFIG_FFUART 1 /* we use FFUART */ | 83 | #define CONFIG_FFUART 1 /* we use FFUART */ |
83 | 84 | ||
84 | /* allow to overwrite serial and ethaddr */ | 85 | /* allow to overwrite serial and ethaddr */ |
85 | #define CONFIG_ENV_OVERWRITE | 86 | #define CONFIG_ENV_OVERWRITE |
86 | 87 | ||
87 | #define CONFIG_BAUDRATE 115200 | 88 | #define CONFIG_BAUDRATE 115200 |
88 | 89 | ||
89 | 90 | ||
90 | /* | 91 | /* |
91 | * BOOTP options | 92 | * BOOTP options |
92 | */ | 93 | */ |
93 | #define CONFIG_BOOTP_BOOTFILESIZE | 94 | #define CONFIG_BOOTP_BOOTFILESIZE |
94 | #define CONFIG_BOOTP_BOOTPATH | 95 | #define CONFIG_BOOTP_BOOTPATH |
95 | #define CONFIG_BOOTP_GATEWAY | 96 | #define CONFIG_BOOTP_GATEWAY |
96 | #define CONFIG_BOOTP_HOSTNAME | 97 | #define CONFIG_BOOTP_HOSTNAME |
97 | 98 | ||
98 | 99 | ||
99 | /* | 100 | /* |
100 | * Command line configuration. | 101 | * Command line configuration. |
101 | */ | 102 | */ |
102 | #include <config_cmd_default.h> | 103 | #include <config_cmd_default.h> |
103 | 104 | ||
104 | #define CONFIG_CMD_ELF | 105 | #define CONFIG_CMD_ELF |
105 | #define CONFIG_CMD_EEPROM | 106 | #define CONFIG_CMD_EEPROM |
106 | #define CONFIG_CMD_DATE | 107 | #define CONFIG_CMD_DATE |
107 | #define CONFIG_CMD_I2C | 108 | #define CONFIG_CMD_I2C |
108 | 109 | ||
109 | 110 | ||
110 | #define CONFIG_BOOTDELAY 3 | 111 | #define CONFIG_BOOTDELAY 3 |
111 | 112 | ||
112 | /* | 113 | /* |
113 | * Miscellaneous configurable options | 114 | * Miscellaneous configurable options |
114 | */ | 115 | */ |
115 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | 116 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
116 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | 117 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
117 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | 118 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
118 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | 119 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
119 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | 120 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
120 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | 121 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
121 | 122 | ||
122 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ | 123 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
123 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | 124 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ |
124 | 125 | ||
125 | #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ | 126 | #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ |
126 | 127 | ||
127 | #define CONFIG_SYS_HZ 1000 | 128 | #define CONFIG_SYS_HZ 1000 |
128 | #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */ | 129 | #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */ |
129 | 130 | ||
130 | /* valid baudrates */ | 131 | /* valid baudrates */ |
131 | 132 | ||
132 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | 133 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
133 | 134 | ||
134 | /* | 135 | /* |
135 | * Definitions related to passing arguments to kernel. | 136 | * Definitions related to passing arguments to kernel. |
136 | */ | 137 | */ |
137 | #define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ | 138 | #define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ |
138 | #define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ | 139 | #define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ |
139 | #define CONFIG_INITRD_TAG 1 /* do not send initrd params */ | 140 | #define CONFIG_INITRD_TAG 1 /* do not send initrd params */ |
140 | #undef CONFIG_VFD /* do not send framebuffer setup */ | 141 | #undef CONFIG_VFD /* do not send framebuffer setup */ |
141 | 142 | ||
142 | /* | 143 | /* |
143 | * Stack sizes | 144 | * Stack sizes |
144 | * | 145 | * |
145 | * The stack sizes are set up in start.S using the settings below | 146 | * The stack sizes are set up in start.S using the settings below |
146 | */ | 147 | */ |
147 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | 148 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
148 | #ifdef CONFIG_USE_IRQ | 149 | #ifdef CONFIG_USE_IRQ |
149 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | 150 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
150 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | 151 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
151 | #endif | 152 | #endif |
152 | 153 | ||
153 | /* | 154 | /* |
154 | * Physical Memory Map | 155 | * Physical Memory Map |
155 | */ | 156 | */ |
156 | #define CONFIG_NR_DRAM_BANKS 4 | 157 | #define CONFIG_NR_DRAM_BANKS 4 |
157 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | 158 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
158 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | 159 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ |
159 | #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ | 160 | #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ |
160 | #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ | 161 | #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ |
161 | #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ | 162 | #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ |
162 | #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ | 163 | #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ |
163 | #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ | 164 | #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ |
164 | #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ | 165 | #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ |
165 | 166 | ||
166 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | 167 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
167 | #define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ | 168 | #define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ |
168 | #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ | 169 | #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ |
169 | #define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ | 170 | #define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ |
170 | #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ | 171 | #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ |
171 | 172 | ||
172 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 | 173 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 |
173 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 | 174 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 |
174 | 175 | ||
175 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | 176 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
176 | 177 | ||
177 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | 178 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
178 | #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) | 179 | #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) |
179 | 180 | ||
180 | /* | 181 | /* |
181 | * FLASH and environment organization | 182 | * FLASH and environment organization |
182 | */ | 183 | */ |
183 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | 184 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
184 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | 185 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
185 | 186 | ||
186 | /* timeout values are in ticks */ | 187 | /* timeout values are in ticks */ |
187 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ | 188 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
188 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | 189 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
189 | #define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Set Lock Bit */ | 190 | #define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Set Lock Bit */ |
190 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Clear Lock Bits */ | 191 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Clear Lock Bits */ |
191 | #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | 192 | #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ |
192 | 193 | ||
193 | #define CONFIG_ENV_IS_IN_FLASH 1 | 194 | #define CONFIG_ENV_IS_IN_FLASH 1 |
194 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */ | 195 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */ |
195 | #define CONFIG_ENV_SIZE 0x4000 | 196 | #define CONFIG_ENV_SIZE 0x4000 |
196 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ | 197 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ |
197 | #define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */ | 198 | #define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */ |
198 | 199 | ||
199 | /****************************************************************************** | 200 | /****************************************************************************** |
200 | * | 201 | * |
201 | * CPU specific defines | 202 | * CPU specific defines |
202 | * | 203 | * |
203 | ******************************************************************************/ | 204 | ******************************************************************************/ |
204 | 205 | ||
205 | /* | 206 | /* |
206 | * GPIO settings | 207 | * GPIO settings |
207 | * | 208 | * |
208 | * GPIO pin assignments | 209 | * GPIO pin assignments |
209 | * GPIO Name Dir Out AF | 210 | * GPIO Name Dir Out AF |
210 | * 0 NC | 211 | * 0 NC |
211 | * 1 NC | 212 | * 1 NC |
212 | * 2 SIRQ1 I | 213 | * 2 SIRQ1 I |
213 | * 3 SIRQ2 I | 214 | * 3 SIRQ2 I |
214 | * 4 SIRQ3 I | 215 | * 4 SIRQ3 I |
215 | * 5 DMAACK1 O 0 | 216 | * 5 DMAACK1 O 0 |
216 | * 6 DMAACK2 O 0 | 217 | * 6 DMAACK2 O 0 |
217 | * 7 DMAACK3 O 0 | 218 | * 7 DMAACK3 O 0 |
218 | * 8 TC1 O 0 | 219 | * 8 TC1 O 0 |
219 | * 9 TC2 O 0 | 220 | * 9 TC2 O 0 |
220 | * 10 TC3 O 0 | 221 | * 10 TC3 O 0 |
221 | * 11 nDMAEN O 1 | 222 | * 11 nDMAEN O 1 |
222 | * 12 AENCTRL O 0 | 223 | * 12 AENCTRL O 0 |
223 | * 13 PLDTC O 0 | 224 | * 13 PLDTC O 0 |
224 | * 14 ETHIRQ I | 225 | * 14 ETHIRQ I |
225 | * 15 NC | 226 | * 15 NC |
226 | * 16 NC | 227 | * 16 NC |
227 | * 17 NC | 228 | * 17 NC |
228 | * 18 RDY I | 229 | * 18 RDY I |
229 | * 19 DMASIO I | 230 | * 19 DMASIO I |
230 | * 20 ETHIRQ NC | 231 | * 20 ETHIRQ NC |
231 | * 21 NC | 232 | * 21 NC |
232 | * 22 PGMEN O 1 FIXME for debug only enable flash | 233 | * 22 PGMEN O 1 FIXME for debug only enable flash |
233 | * 23 NC | 234 | * 23 NC |
234 | * 24 NC | 235 | * 24 NC |
235 | * 25 NC | 236 | * 25 NC |
236 | * 26 NC | 237 | * 26 NC |
237 | * 27 NC | 238 | * 27 NC |
238 | * 28 NC | 239 | * 28 NC |
239 | * 29 NC | 240 | * 29 NC |
240 | * 30 NC | 241 | * 30 NC |
241 | * 31 NC | 242 | * 31 NC |
242 | * 32 NC | 243 | * 32 NC |
243 | * 33 NC | 244 | * 33 NC |
244 | * 34 FFRXD I 01 | 245 | * 34 FFRXD I 01 |
245 | * 35 FFCTS I 01 | 246 | * 35 FFCTS I 01 |
246 | * 36 FFDCD I 01 | 247 | * 36 FFDCD I 01 |
247 | * 37 FFDSR I 01 | 248 | * 37 FFDSR I 01 |
248 | * 38 FFRI I 01 | 249 | * 38 FFRI I 01 |
249 | * 39 FFTXD O 1 10 | 250 | * 39 FFTXD O 1 10 |
250 | * 40 FFDTR O 0 10 | 251 | * 40 FFDTR O 0 10 |
251 | * 41 FFRTS O 0 10 | 252 | * 41 FFRTS O 0 10 |
252 | * 42 RS232FOFF O 0 00 | 253 | * 42 RS232FOFF O 0 00 |
253 | * 43 NC | 254 | * 43 NC |
254 | * 44 NC | 255 | * 44 NC |
255 | * 45 IRSL0 O 0 | 256 | * 45 IRSL0 O 0 |
256 | * 46 IRRX0 I 01 | 257 | * 46 IRRX0 I 01 |
257 | * 47 IRTX0 O 0 10 | 258 | * 47 IRTX0 O 0 10 |
258 | * 48 NC | 259 | * 48 NC |
259 | * 49 nIOWE O 0 | 260 | * 49 nIOWE O 0 |
260 | * 50 NC | 261 | * 50 NC |
261 | * 51 NC | 262 | * 51 NC |
262 | * 52 NC | 263 | * 52 NC |
263 | * 53 NC | 264 | * 53 NC |
264 | * 54 NC | 265 | * 54 NC |
265 | * 55 NC | 266 | * 55 NC |
266 | * 56 NC | 267 | * 56 NC |
267 | * 57 NC | 268 | * 57 NC |
268 | * 58 DKDIRQ I | 269 | * 58 DKDIRQ I |
269 | * 59 NC | 270 | * 59 NC |
270 | * 60 NC | 271 | * 60 NC |
271 | * 61 NC | 272 | * 61 NC |
272 | * 62 NC | 273 | * 62 NC |
273 | * 63 NC | 274 | * 63 NC |
274 | * 64 COMLED O 0 | 275 | * 64 COMLED O 0 |
275 | * 65 COMLED O 0 | 276 | * 65 COMLED O 0 |
276 | * 66 COMLED O 0 | 277 | * 66 COMLED O 0 |
277 | * 67 COMLED O 0 | 278 | * 67 COMLED O 0 |
278 | * 68 COMLED O 0 | 279 | * 68 COMLED O 0 |
279 | * 69 COMLED O 0 | 280 | * 69 COMLED O 0 |
280 | * 70 COMLED O 0 | 281 | * 70 COMLED O 0 |
281 | * 71 COMLED O 0 | 282 | * 71 COMLED O 0 |
282 | * 72 NC | 283 | * 72 NC |
283 | * 73 NC | 284 | * 73 NC |
284 | * 74 NC | 285 | * 74 NC |
285 | * 75 NC | 286 | * 75 NC |
286 | * 76 NC | 287 | * 76 NC |
287 | * 77 NC | 288 | * 77 NC |
288 | * 78 CSIO O 1 | 289 | * 78 CSIO O 1 |
289 | * 79 NC | 290 | * 79 NC |
290 | * 80 CSETH O 1 | 291 | * 80 CSETH O 1 |
291 | * | 292 | * |
292 | * NOTE: All NC's are defined to be outputs | 293 | * NOTE: All NC's are defined to be outputs |
293 | * | 294 | * |
294 | */ | 295 | */ |
295 | /* Pin direction control */ | 296 | /* Pin direction control */ |
296 | #define CONFIG_SYS_GPDR0_VAL 0xd3808000 | 297 | #define CONFIG_SYS_GPDR0_VAL 0xd3808000 |
297 | #define CONFIG_SYS_GPDR1_VAL 0xfcffab83 | 298 | #define CONFIG_SYS_GPDR1_VAL 0xfcffab83 |
298 | #define CONFIG_SYS_GPDR2_VAL 0x0001ffff | 299 | #define CONFIG_SYS_GPDR2_VAL 0x0001ffff |
299 | /* Set and Clear registers */ | 300 | /* Set and Clear registers */ |
300 | #define CONFIG_SYS_GPSR0_VAL 0x00008000 | 301 | #define CONFIG_SYS_GPSR0_VAL 0x00008000 |
301 | #define CONFIG_SYS_GPSR1_VAL 0x00ff0002 | 302 | #define CONFIG_SYS_GPSR1_VAL 0x00ff0002 |
302 | #define CONFIG_SYS_GPSR2_VAL 0x0001c000 | 303 | #define CONFIG_SYS_GPSR2_VAL 0x0001c000 |
303 | #define CONFIG_SYS_GPCR0_VAL 0x00000000 | 304 | #define CONFIG_SYS_GPCR0_VAL 0x00000000 |
304 | #define CONFIG_SYS_GPCR1_VAL 0x00000000 | 305 | #define CONFIG_SYS_GPCR1_VAL 0x00000000 |
305 | #define CONFIG_SYS_GPCR2_VAL 0x00000000 | 306 | #define CONFIG_SYS_GPCR2_VAL 0x00000000 |
306 | /* Edge detect registers (these are set by the kernel) */ | 307 | /* Edge detect registers (these are set by the kernel) */ |
307 | #define CONFIG_SYS_GRER0_VAL 0x00002180 | 308 | #define CONFIG_SYS_GRER0_VAL 0x00002180 |
308 | #define CONFIG_SYS_GRER1_VAL 0x00000000 | 309 | #define CONFIG_SYS_GRER1_VAL 0x00000000 |
309 | #define CONFIG_SYS_GRER2_VAL 0x00000000 | 310 | #define CONFIG_SYS_GRER2_VAL 0x00000000 |
310 | #define CONFIG_SYS_GFER0_VAL 0x000043e0 | 311 | #define CONFIG_SYS_GFER0_VAL 0x000043e0 |
311 | #define CONFIG_SYS_GFER1_VAL 0x00000000 | 312 | #define CONFIG_SYS_GFER1_VAL 0x00000000 |
312 | #define CONFIG_SYS_GFER2_VAL 0x00000000 | 313 | #define CONFIG_SYS_GFER2_VAL 0x00000000 |
313 | /* Alternate function registers */ | 314 | /* Alternate function registers */ |
314 | #define CONFIG_SYS_GAFR0_L_VAL 0x80000004 | 315 | #define CONFIG_SYS_GAFR0_L_VAL 0x80000004 |
315 | #define CONFIG_SYS_GAFR0_U_VAL 0x595a8010 | 316 | #define CONFIG_SYS_GAFR0_U_VAL 0x595a8010 |
316 | #define CONFIG_SYS_GAFR1_L_VAL 0x699a9559 | 317 | #define CONFIG_SYS_GAFR1_L_VAL 0x699a9559 |
317 | #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aaaa | 318 | #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aaaa |
318 | #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa | 319 | #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa |
319 | #define CONFIG_SYS_GAFR2_U_VAL 0x00000002 | 320 | #define CONFIG_SYS_GAFR2_U_VAL 0x00000002 |
320 | 321 | ||
321 | /* | 322 | /* |
322 | * Clocks, power control and interrupts | 323 | * Clocks, power control and interrupts |
323 | */ | 324 | */ |
324 | #define CONFIG_SYS_PSSR_VAL 0x00000030 | 325 | #define CONFIG_SYS_PSSR_VAL 0x00000030 |
325 | #define CONFIG_SYS_CCCR 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */ | 326 | #define CONFIG_SYS_CCCR 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */ |
326 | #define CONFIG_SYS_CKEN 0x000141ec /* FFUART and STUART enabled */ | 327 | #define CONFIG_SYS_CKEN 0x000141ec /* FFUART and STUART enabled */ |
327 | #define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ | 328 | #define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ |
328 | 329 | ||
329 | /* FIXME | 330 | /* FIXME |
330 | * | 331 | * |
331 | * RTC settings | 332 | * RTC settings |
332 | * Watchdog | 333 | * Watchdog |
333 | * | 334 | * |
334 | */ | 335 | */ |
335 | 336 | ||
336 | /* | 337 | /* |
337 | * Memory settings | 338 | * Memory settings |
338 | * | 339 | * |
339 | */ | 340 | */ |
340 | #define CONFIG_SYS_MSC0_VAL 0x122423f0 /* FLASH / LAN (cs0)/(cS1) */ | 341 | #define CONFIG_SYS_MSC0_VAL 0x122423f0 /* FLASH / LAN (cs0)/(cS1) */ |
341 | #define CONFIG_SYS_MSC1_VAL 0x35f4aa4c /* USB / ST3+ST5 (cs2)/(cS3) */ | 342 | #define CONFIG_SYS_MSC1_VAL 0x35f4aa4c /* USB / ST3+ST5 (cs2)/(cS3) */ |
342 | #define CONFIG_SYS_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */ | 343 | #define CONFIG_SYS_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */ |
343 | #define CONFIG_SYS_MDCNFG_VAL 0x000009c9 | 344 | #define CONFIG_SYS_MDCNFG_VAL 0x000009c9 |
344 | #define CONFIG_SYS_MDMRS_VAL 0x00220022 | 345 | #define CONFIG_SYS_MDMRS_VAL 0x00220022 |
345 | #define CONFIG_SYS_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */ | 346 | #define CONFIG_SYS_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */ |
346 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 | 347 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 |
347 | #define CONFIG_SYS_SXCNFG_VAL 0x00000000 | 348 | #define CONFIG_SYS_SXCNFG_VAL 0x00000000 |
348 | 349 | ||
349 | /* | 350 | /* |
350 | * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) | 351 | * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) |
351 | */ | 352 | */ |
352 | #define CONFIG_SYS_MECR_VAL 0x00000000 | 353 | #define CONFIG_SYS_MECR_VAL 0x00000000 |
353 | #define CONFIG_SYS_MCMEM0_VAL 0x00010504 | 354 | #define CONFIG_SYS_MCMEM0_VAL 0x00010504 |
354 | #define CONFIG_SYS_MCMEM1_VAL 0x00010504 | 355 | #define CONFIG_SYS_MCMEM1_VAL 0x00010504 |
355 | #define CONFIG_SYS_MCATT0_VAL 0x00010504 | 356 | #define CONFIG_SYS_MCATT0_VAL 0x00010504 |
356 | #define CONFIG_SYS_MCATT1_VAL 0x00010504 | 357 | #define CONFIG_SYS_MCATT1_VAL 0x00010504 |
357 | #define CONFIG_SYS_MCIO0_VAL 0x00004715 | 358 | #define CONFIG_SYS_MCIO0_VAL 0x00004715 |
358 | #define CONFIG_SYS_MCIO1_VAL 0x00004715 | 359 | #define CONFIG_SYS_MCIO1_VAL 0x00004715 |
359 | 360 | ||
360 | /* Board specific defines */ | 361 | /* Board specific defines */ |
361 | 362 | ||
362 | #ifndef __ASSEMBLY__ | 363 | #ifndef __ASSEMBLY__ |
363 | 364 | ||
364 | /* global prototypes */ | 365 | /* global prototypes */ |
365 | void led_code(int code, int color); | 366 | void led_code(int code, int color); |
366 | 367 | ||
367 | #endif | 368 | #endif |
368 | 369 | ||
369 | #endif /* __CONFIG_H */ | 370 | #endif /* __CONFIG_H */ |
370 | 371 |