Eric Lee / smarc-uboot

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Commit 68fbb20f0db35e533488fd3b1c8ace8c880b2212

Authored by Peng Fan
1 parent 1f0bb39408
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-12798 imx6ull: fix snvs tamper pin usage 

SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
not in IOMUXC, so correct the related registers' offset.

Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
them from iomuxc pins.

Define CONFIG_IOMUX_LPSR for mx6ull_ddr3_arm2 board to enable
using these pins.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Showing 4 changed files with 30 additions and 16 deletions Side-by-side Diff

arch/arm/imx-common/iomux-v3.c
Diff comments   View file @ 68fbb20
... ... @@ -4,7 +4,7 @@
4 4 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
5 5 * <armlinux@phytec.de>
6 6 *
7   - * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
  7 + * Copyright (C) 2004-2011, 2016 Freescale Semiconductor, Inc.
8 8 *
9 9 * SPDX-License-Identifier: GPL-2.0+
10 10 */
... ... @@ -42,6 +42,7 @@
42 42 #ifdef CONFIG_IOMUX_LPSR
43 43 u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
44 44  
  45 +#ifdef CONFIG_MX7
45 46 if (lpsr == IOMUX_CONFIG_LPSR) {
46 47 base = (void *)IOMUXC_LPSR_BASE_ADDR;
47 48 mux_mode &= ~IOMUX_CONFIG_LPSR;
48 49  
49 50  
... ... @@ -49,9 +50,17 @@
49 50 if (sel_input_ofs)
50 51 sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
51 52 }
  53 +#else
  54 + if (is_cpu_type(MXC_CPU_MX6ULL)) {
  55 + if (lpsr == IOMUX_CONFIG_LPSR) {
  56 + base = (void *)IOMUXC_SNVS_BASE_ADDR;
  57 + mux_mode &= ~IOMUX_CONFIG_LPSR;
  58 + }
  59 + }
52 60 #endif
  61 +#endif
53 62  
54   - if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs)
  63 + if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6ULL) || mux_ctrl_ofs)
55 64 __raw_writel(mux_mode, base + mux_ctrl_ofs);
56 65  
57 66 if (sel_input_ofs)
arch/arm/include/asm/arch-mx6/mx6ull_pins.h
Diff comments   View file @ 68fbb20
... ... @@ -10,20 +10,23 @@
10 10 #include <asm/imx-common/iomux-v3.h>
11 11  
12 12 enum {
  13 + MX6_PAD_BOOT_MODE0__GPIO5_IO10 = IOMUX_PAD(0x0044, 0x0000, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
  14 + MX6_PAD_BOOT_MODE1__GPIO5_IO11 = IOMUX_PAD(0x0048, 0x0004, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
  15 +
13 16 /*
14 17 * The TAMPER Pin can be used for GPIO, which depends on
15 18 * TAMPER_PIN_DISABLE[1:0] settings.
16 19 */
17   - MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 = IOMUX_PAD(0x02A8, 0x001C, 5, 0x0000, 0, 0),
18   - MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 = IOMUX_PAD(0x02AC, 0x0020, 5, 0x0000, 0, 0),
19   - MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 = IOMUX_PAD(0x02B0, 0x0024, 5, 0x0000, 0, 0),
20   - MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 = IOMUX_PAD(0x02B4, 0x0028, 5, 0x0000, 0, 0),
21   - MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 = IOMUX_PAD(0x02B8, 0x002C, 5, 0x0000, 0, 0),
22   - MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 = IOMUX_PAD(0x02BC, 0x0030, 5, 0x0000, 0, 0),
23   - MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 = IOMUX_PAD(0x02C0, 0x0034, 5, 0x0000, 0, 0),
24   - MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 = IOMUX_PAD(0x02C4, 0x0038, 5, 0x0000, 0, 0),
25   - MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 = IOMUX_PAD(0x02C8, 0x003C, 5, 0x0000, 0, 0),
26   - MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 = IOMUX_PAD(0x02CC, 0x0040, 5, 0x0000, 0, 0),
  20 + MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 = IOMUX_PAD(0x004C, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
  21 + MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 = IOMUX_PAD(0x0050, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
  22 + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 = IOMUX_PAD(0x0054, 0x0010, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
  23 + MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 = IOMUX_PAD(0x0058, 0x0014, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
  24 + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 = IOMUX_PAD(0x005C, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
  25 + MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 = IOMUX_PAD(0x0060, 0x001C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
  26 + MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 = IOMUX_PAD(0x0064, 0x0020, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
  27 + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 = IOMUX_PAD(0x0068, 0x0024, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
  28 + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 = IOMUX_PAD(0x006C, 0x0028, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
  29 + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 = IOMUX_PAD(0x0070, 0x002C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
27 30  
28 31 MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x02D0, 0x0044, 0, 0x0000, 0, 0),
29 32 MX6_PAD_JTAG_MOD__GPT2_CLK = IOMUX_PAD(0x02D0, 0x0044, 1, 0x05A0, 0, 0),
arch/arm/include/asm/imx-common/iomux-v3.h
Diff comments   View file @ 68fbb20
... ... @@ -3,7 +3,7 @@
3 3 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
4 4 * <armlinux@phytec.de>
5 5 *
6   - * Copyright (C) 2011 Freescale Semiconductor, Inc.
  6 + * Copyright (C) 2011, 2016 Freescale Semiconductor, Inc.
7 7 *
8 8 * SPDX-License-Identifier: GPL-2.0+
9 9 */
10 10  
... ... @@ -85,12 +85,12 @@
85 85  
86 86 #define NO_PAD_CTRL (1 << 17)
87 87  
88   -#ifdef CONFIG_MX7
89   -
90   -#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
91 88 #define IOMUX_CONFIG_LPSR 0x8
92 89 #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
93 90 MUX_MODE_SHIFT)
  91 +#ifdef CONFIG_MX7
  92 +
  93 +#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
94 94  
95 95 #define PAD_CTL_DSE_1P8V_140OHM (0x0<<0)
96 96 #define PAD_CTL_DSE_1P8V_35OHM (0x1<<0)
include/configs/mx6ull_ddr3_arm2.h
Diff comments   View file @ 68fbb20
... ... @@ -32,6 +32,8 @@
32 32  
33 33 #include "mx6ul_arm2.h"
34 34  
  35 +#define CONFIG_IOMUX_LPSR
  36 +
35 37 #define PHYS_SDRAM_SIZE SZ_1G
36 38  
37 39 #ifdef CONFIG_SYS_USE_SPINOR