Commit 68fbc0e68604a3e58c6980e3d934e9741e561174
Committed by
Albert ARIBAUD
Albert ARIBAUD
1 parent
e78b140801
Exists in
master
and in
56 other branches
imx: mx53ard: Add support for NAND Flash
Add support for the Samsung K9LAG08U0M NAND Flash (2-GiB MLC NAND Flash, 2-kiB pages, 256-kiB blocks, 30-ns R/W cycles, 1 CS) on mx53ard. eNFC_CLK_ROOT is set up with a cycle time of 37.5 ns (400 MHz / 3 / 5) for this board, which satisfies the 30-ns NF R/W cycle requirement. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Showing 2 changed files with 76 additions and 0 deletions Side-by-side Diff
board/freescale/mx53ard/mx53ard.c
| ... | ... | @@ -58,6 +58,71 @@ |
| 58 | 58 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
| 59 | 59 | } |
| 60 | 60 | |
| 61 | +#ifdef CONFIG_NAND_MXC | |
| 62 | +static void setup_iomux_nand(void) | |
| 63 | +{ | |
| 64 | + u32 i, reg; | |
| 65 | + #define M4IF_GENP_WEIM_MM_MASK 0x00000001 | |
| 66 | + #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 | |
| 67 | + | |
| 68 | + reg = __raw_readl(M4IF_BASE_ADDR + 0xc); | |
| 69 | + reg &= ~M4IF_GENP_WEIM_MM_MASK; | |
| 70 | + __raw_writel(reg, M4IF_BASE_ADDR + 0xc); | |
| 71 | + for (i = 0x4; i < 0x94; i += 0x18) { | |
| 72 | + reg = __raw_readl(WEIM_BASE_ADDR + i); | |
| 73 | + reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK; | |
| 74 | + __raw_writel(reg, WEIM_BASE_ADDR + i); | |
| 75 | + } | |
| 76 | + | |
| 77 | + mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0); | |
| 78 | + mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH); | |
| 79 | + mxc_request_iomux(MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0); | |
| 80 | + mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, PAD_CTL_DRV_HIGH); | |
| 81 | + mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0); | |
| 82 | + mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PKE_ENABLE | | |
| 83 | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU); | |
| 84 | + mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0); | |
| 85 | + mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH); | |
| 86 | + mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0); | |
| 87 | + mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH); | |
| 88 | + mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0); | |
| 89 | + mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PKE_ENABLE | | |
| 90 | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU); | |
| 91 | + mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0); | |
| 92 | + mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH); | |
| 93 | + mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0); | |
| 94 | + mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH); | |
| 95 | + mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0); | |
| 96 | + mxc_iomux_set_pad(MX53_PIN_EIM_DA0, PAD_CTL_PKE_ENABLE | | |
| 97 | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); | |
| 98 | + mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0); | |
| 99 | + mxc_iomux_set_pad(MX53_PIN_EIM_DA1, PAD_CTL_PKE_ENABLE | | |
| 100 | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); | |
| 101 | + mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0); | |
| 102 | + mxc_iomux_set_pad(MX53_PIN_EIM_DA2, PAD_CTL_PKE_ENABLE | | |
| 103 | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); | |
| 104 | + mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0); | |
| 105 | + mxc_iomux_set_pad(MX53_PIN_EIM_DA3, PAD_CTL_PKE_ENABLE | | |
| 106 | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); | |
| 107 | + mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0); | |
| 108 | + mxc_iomux_set_pad(MX53_PIN_EIM_DA4, PAD_CTL_PKE_ENABLE | | |
| 109 | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); | |
| 110 | + mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0); | |
| 111 | + mxc_iomux_set_pad(MX53_PIN_EIM_DA5, PAD_CTL_PKE_ENABLE | | |
| 112 | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); | |
| 113 | + mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0); | |
| 114 | + mxc_iomux_set_pad(MX53_PIN_EIM_DA6, PAD_CTL_PKE_ENABLE | | |
| 115 | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); | |
| 116 | + mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0); | |
| 117 | + mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE | | |
| 118 | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); | |
| 119 | +} | |
| 120 | +#else | |
| 121 | +static void setup_iomux_nand(void) | |
| 122 | +{ | |
| 123 | +} | |
| 124 | +#endif | |
| 125 | + | |
| 61 | 126 | static void setup_iomux_uart(void) |
| 62 | 127 | { |
| 63 | 128 | /* UART1 RXD */ |
| ... | ... | @@ -277,6 +342,7 @@ |
| 277 | 342 | |
| 278 | 343 | int board_early_init_f(void) |
| 279 | 344 | { |
| 345 | + setup_iomux_nand(); | |
| 280 | 346 | setup_iomux_uart(); |
| 281 | 347 | return 0; |
| 282 | 348 | } |
include/configs/mx53ard.h
| ... | ... | @@ -41,6 +41,16 @@ |
| 41 | 41 | #define CONFIG_BOARD_EARLY_INIT_F |
| 42 | 42 | #define CONFIG_MXC_GPIO |
| 43 | 43 | |
| 44 | +#define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 45 | +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI | |
| 46 | +#define CONFIG_NAND_MXC | |
| 47 | +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI | |
| 48 | +#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR | |
| 49 | +#define CONFIG_SYS_NAND_LARGEPAGE | |
| 50 | +#define CONFIG_MXC_NAND_HWECC | |
| 51 | +#define CONFIG_SYS_NAND_USE_FLASH_BBT | |
| 52 | +#define CONFIG_CMD_NAND | |
| 53 | + | |
| 44 | 54 | #define CONFIG_MXC_UART |
| 45 | 55 | #define CONFIG_MXC_UART_BASE UART1_BASE |
| 46 | 56 |