Eric Lee / smarc-uboot

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Commit 690e425844511fe37d3315e86414d0a9e3accd1c

Authored by Prabhakar Kushwaha
Committed by York Sun
1 parent 3fdc827ca8
Exists in master and in 49 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

powerpc:Rename CONFIG_PBLRCW_CONFIG & CONFIG_SYS_FSL_PBL_PBI 

Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG.

Also add their details in README.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 9 changed files with 33 additions and 19 deletions Side-by-side Diff

... ... @@ -419,8 +419,8 @@
419 419 -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
420 420  
421 421 $(obj)u-boot.pbl: $(obj)u-boot.bin
422   - $(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \
423   - -R $(CONFIG_PBLPBI_CONFIG) -T pblimage \
  422 + $(obj)tools/mkimage -n $(CONFIG_SYS_FSL_PBL_RCW) \
  423 + -R $(CONFIG_SYS_FSL_PBL_PBI) -T pblimage \
424 424 -d $< $@
425 425  
426 426 $(obj)u-boot.sha1: $(obj)u-boot.bin
... ... @@ -472,6 +472,15 @@
472 472 Board config to use DDR3. It can be enabled for SoCs with
473 473 Freescale DDR3 controllers.
474 474  
  475 + CONFIG_SYS_FSL_PBL_PBI
  476 + It enables addition of RCW (Power on reset configuration) in built image.
  477 + Please refer doc/README.pblimage for more details
  478 +
  479 + CONFIG_SYS_FSL_PBL_RCW
  480 + It adds PBI(pre-boot instructions) commands in u-boot build image.
  481 + PBI commands can be used to configure SoC before it starts the execution.
  482 + Please refer doc/README.pblimage for more details
  483 +
475 484 - Intel Monahans options:
476 485 CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
477 486  
include/configs/B4860QDS.h
Diff comments   View file @ 690e425
... ... @@ -16,8 +16,8 @@
16 16 #ifdef CONFIG_RAMBOOT_PBL
17 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
19   -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
20   -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
  19 +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
  20 +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
21 21 #endif
22 22  
23 23 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
include/configs/P2041RDB.h
Diff comments   View file @ 690e425
... ... @@ -18,8 +18,9 @@
18 18 #ifdef CONFIG_RAMBOOT_PBL
19 19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20 20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
21   -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
22   -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
  21 +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
  22 +#define CONFIG_SYS_FSL_PBL_RCW \
  23 + $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
23 24 #endif
24 25  
25 26 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
include/configs/T1040QDS.h
Diff comments   View file @ 690e425
... ... @@ -32,8 +32,8 @@
32 32 #ifdef CONFIG_RAMBOOT_PBL
33 33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
34 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
35   -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
36   -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
  35 +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
  36 +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
37 37 #endif
38 38  
39 39 /* High Level Configuration Options */
include/configs/T2080QDS.h
Diff comments   View file @ 690e425
... ... @@ -45,8 +45,8 @@
45 45 #ifdef CONFIG_RAMBOOT_PBL
46 46 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
47 47 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
48   -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg
49   -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg
  48 +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg
  49 +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg
50 50 #endif
51 51  
52 52 #define CONFIG_SRIO_PCIE_BOOT_MASTER
include/configs/T4240QDS.h
Diff comments   View file @ 690e425
... ... @@ -21,8 +21,8 @@
21 21 #ifdef CONFIG_RAMBOOT_PBL
22 22 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
23 23 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
24   -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
25   -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
  24 +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
  25 +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
26 26 #endif
27 27  
28 28 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
include/configs/corenet_ds.h
Diff comments   View file @ 690e425
... ... @@ -15,15 +15,19 @@
15 15 #ifdef CONFIG_RAMBOOT_PBL
16 16 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
17 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
18   -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
  18 +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
19 19 #if defined(CONFIG_P3041DS)
20   -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
  20 +#define CONFIG_SYS_FSL_PBL_RCW \
  21 + $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
21 22 #elif defined(CONFIG_P4080DS)
22   -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
  23 +#define CONFIG_SYS_FSL_PBL_RCW \
  24 + $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
23 25 #elif defined(CONFIG_P5020DS)
24   -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
  26 +#define CONFIG_SYS_FSL_PBL_RCW \
  27 + $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
25 28 #elif defined(CONFIG_P5040DS)
26   -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
  29 +#define CONFIG_SYS_FSL_PBL_RCW \
  30 + $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
27 31 #endif
28 32 #endif
29 33  
include/configs/km/kmp204x-common.h
Diff comments   View file @ 690e425
... ... @@ -24,8 +24,8 @@
24 24 #define CONFIG_RAMBOOT_PBL
25 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
26 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
27   -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/keymile/kmp204x/pbi.cfg
28   -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg
  27 +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/keymile/kmp204x/pbi.cfg
  28 +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg
29 29  
30 30 /* High Level Configuration Options */
31 31 #define CONFIG_BOOKE