Eric Lee / smarc-uboot

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Commit 6921d2811bb4f9a866f8ab858ce126d7e8eecc02

Authored by Gaurav Jain
Committed by Ye Li
1 parent ac70a113ab
Exists in emb_lf_v2022.04

LFU-320 crypto/fsl: fsl_hash: Fix dcache issue in caam_hash_finish 

HW accelerated hash operations are giving incorrect hash output.
so add flush and invalidate for input/output hash buffers.

Fixes: 94e3c8c4fd (crypto/fsl - Add progressive hashing support using hardware acceleration.)
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>

Showing 1 changed file with 8 additions and 0 deletions Side-by-side Diff

drivers/crypto/fsl/fsl_hash.c
Diff comments   View file @ 6921d28
... ... @@ -149,12 +149,20 @@
149 149 driver_hash[caam_algo].digestsize,
150 150 1);
151 151  
  152 + flush_dcache_range((ulong)ctx->sg_tbl, (ulong)(ctx->sg_tbl) + len);
  153 + flush_dcache_range((ulong)ctx->sha_desc,
  154 + (ulong)(ctx->sha_desc) + (sizeof(uint32_t) * MAX_CAAM_DESCSIZE));
  155 + flush_dcache_range((ulong)ctx->hash,
  156 + (ulong)(ctx->hash) + driver_hash[caam_algo].digestsize);
  157 +
152 158 ret = run_descriptor_jr(ctx->sha_desc);
153 159  
154 160 if (ret) {
155 161 debug("Error %x\n", ret);
156 162 return ret;
157 163 } else {
  164 + invalidate_dcache_range((ulong)ctx->hash,
  165 + (ulong)(ctx->hash) + driver_hash[caam_algo].digestsize);
158 166 memcpy(dest_buf, ctx->hash, sizeof(ctx->hash));
159 167 }
160 168 free(ctx);