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Commit 69624195a3678b78569addf739b58275ae39460a

Authored by Wolfgang Denk
Committed by Albert ARIBAUD
1 parent 957731eda0
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: remove broken "mx1fs2" board 

Signed-off-by: Wolfgang Denk <wd@denx.de>

Showing 10 changed files with 1 additions and 1626 deletions Side-by-side Diff

... ... @@ -326,7 +326,6 @@
326 326 magnesium \
327 327 mv88f6281gtw_ge \
328 328 mx1ads \
329   - mx1fs2 \
330 329 netstar \
331 330 nhk8815 \
332 331 nhk8815_onenand \
board/mx1fs2/Makefile
View file @ 6962419
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# See file CREDITS for list of people who contributed to this
6   -# project.
7   -#
8   -# This program is free software; you can redistribute it and/or
9   -# modify it under the terms of the GNU General Public License as
10   -# published by the Free Software Foundation; either version 2 of
11   -# the License, or (at your option) any later version.
12   -#
13   -# This program is distributed in the hope that it will be useful,
14   -# but WITHOUT ANY WARRANTY; without even the implied warranty of
15   -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   -# GNU General Public License for more details.
17   -#
18   -# You should have received a copy of the GNU General Public License
19   -# along with this program; if not, write to the Free Software
20   -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   -# MA 02111-1307 USA
22   -#
23   -
24   -include $(TOPDIR)/config.mk
25   -
26   -LIB = $(obj)lib$(BOARD).o
27   -
28   -COBJS := mx1fs2.o flash.o
29   -SOBJS := lowlevel_init.o
30   -
31   -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
32   -OBJS := $(addprefix $(obj),$(COBJS))
33   -SOBJS := $(addprefix $(obj),$(SOBJS))
34   -
35   -$(LIB): $(obj).depend $(OBJS) $(SOBJS)
36   - $(call cmd_link_o_target, $(OBJS) $(SOBJS))
37   -
38   -clean:
39   - rm -f $(SOBJS) $(OBJS)
40   -
41   -distclean: clean
42   - rm -f $(LIB) core *.bak $(obj).depend
43   -
44   -#########################################################################
45   -
46   -# defines $(obj).depend target
47   -include $(SRCTREE)/rules.mk
48   -
49   -sinclude $(obj).depend
50   -
51   -#########################################################################
board/mx1fs2/config.mk
View file @ 6962419
1   -#
2   -# This config file is used for compilation of IMX sources
3   -#
4   -# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE.
5   -# This allows for example having one copy located at the end of ram and stored
6   -# in flash device and later on while developing use other location to test
7   -# the code in RAM device only.
8   -#
9   -
10   -CONFIG_SYS_TEXT_BASE = 0x08f00000
board/mx1fs2/flash.c
View file @ 6962419
1   -/*
2   - * (C) 2000-2004 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
3   - * (C) 2003 August Hoeraendl, Logotronic GmbH
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -#undef CONFIG_FLASH_16BIT
25   -
26   -#include <common.h>
27   -
28   -#define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE
29   -#define MAIN_SECT_SIZE MX1FS2_FLASH_SECT_SIZE
30   -
31   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
32   -
33   -/*
34   - * NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
35   - * has nothing to do with the flash chip being 8-bit or 16-bit.
36   - */
37   -#ifdef CONFIG_FLASH_16BIT
38   -typedef unsigned short FLASH_PORT_WIDTH;
39   -typedef volatile unsigned short FLASH_PORT_WIDTHV;
40   -
41   -#define FLASH_ID_MASK 0xFFFF
42   -#else
43   -typedef unsigned long FLASH_PORT_WIDTH;
44   -typedef volatile unsigned long FLASH_PORT_WIDTHV;
45   -
46   -#define FLASH_ID_MASK 0xFFFFFFFF
47   -#endif
48   -
49   -#define FPW FLASH_PORT_WIDTH
50   -#define FPWV FLASH_PORT_WIDTHV
51   -
52   -#define ORMASK(size) ((-size) & OR_AM_MSK)
53   -
54   -/*-----------------------------------------------------------------------
55   - * Functions
56   - */
57   -#if 0
58   -static ulong flash_get_size(FPWV * addr, flash_info_t * info);
59   -static void flash_get_offsets(ulong base, flash_info_t * info);
60   -#endif
61   -static void flash_reset(flash_info_t * info);
62   -static int write_word_intel(flash_info_t * info, FPWV * dest, FPW data);
63   -static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
64   -#define write_word(in, de, da) write_word_amd(in, de, da)
65   -#ifdef CONFIG_SYS_FLASH_PROTECTION
66   -static void flash_sync_real_protect(flash_info_t * info);
67   -#endif
68   -
69   -/*-----------------------------------------------------------------------
70   - * flash_init()
71   - *
72   - * sets up flash_info and returns size of FLASH (bytes)
73   - */
74   -ulong
75   -flash_init(void)
76   -{
77   - int i, j;
78   - ulong size = 0;
79   -
80   - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
81   - ulong flashbase = 0;
82   - flash_info[i].flash_id =
83   - (FLASH_MAN_AMD & FLASH_VENDMASK) |
84   - (FLASH_AM640U & FLASH_TYPEMASK);
85   - flash_info[i].size = FLASH_BANK_SIZE;
86   - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
87   - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
88   - switch (i) {
89   - case 0:
90   - flashbase = MX1FS2_FLASH_BASE;
91   - break;
92   - default:
93   - panic("configured too many flash banks!\n");
94   - break;
95   - }
96   - for (j = 0; j < flash_info[i].sector_count; j++) {
97   - flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE;
98   - }
99   - size += flash_info[i].size;
100   - }
101   -
102   - /* Protect monitor and environment sectors */
103   - flash_protect(FLAG_PROTECT_SET,
104   - CONFIG_SYS_FLASH_BASE,
105   - CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
106   - &flash_info[0]);
107   -
108   - flash_protect(FLAG_PROTECT_SET,
109   - CONFIG_ENV_ADDR,
110   - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
111   -
112   - return size;
113   -}
114   -
115   -/*-----------------------------------------------------------------------
116   - */
117   -static void
118   -flash_reset(flash_info_t * info)
119   -{
120   - FPWV *base = (FPWV *) (info->start[0]);
121   -
122   - /* Put FLASH back in read mode */
123   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
124   - *base = (FPW) 0x00FF00FF; /* Intel Read Mode */
125   - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
126   - *base = (FPW) 0x00F000F0; /* AMD Read Mode */
127   -}
128   -
129   -/*-----------------------------------------------------------------------
130   - */
131   -#if 0
132   -static void
133   -flash_get_offsets(ulong base, flash_info_t * info)
134   -{
135   - int i;
136   -
137   - /* set up sector start address table */
138   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
139   - && (info->flash_id & FLASH_BTYPE)) {
140   - int bootsect_size; /* number of bytes/boot sector */
141   - int sect_size; /* number of bytes/regular sector */
142   -
143   - bootsect_size = 0x00002000 * (sizeof (FPW) / 2);
144   - sect_size = 0x00010000 * (sizeof (FPW) / 2);
145   -
146   - /* set sector offsets for bottom boot block type */
147   - for (i = 0; i < 8; ++i) {
148   - info->start[i] = base + (i * bootsect_size);
149   - }
150   - for (i = 8; i < info->sector_count; i++) {
151   - info->start[i] = base + ((i - 7) * sect_size);
152   - }
153   - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
154   - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
155   -
156   - int sect_size; /* number of bytes/sector */
157   -
158   - sect_size = 0x00010000 * (sizeof (FPW) / 2);
159   -
160   - /* set up sector start address table (uniform sector type) */
161   - for (i = 0; i < info->sector_count; i++)
162   - info->start[i] = base + (i * sect_size);
163   - }
164   -}
165   -#endif /* 0 */
166   -
167   -/*-----------------------------------------------------------------------
168   - */
169   -
170   -void
171   -flash_print_info(flash_info_t * info)
172   -{
173   - int i;
174   - uchar *boottype;
175   - uchar *bootletter;
176   - char *fmt;
177   - uchar botbootletter[] = "B";
178   - uchar topbootletter[] = "T";
179   - uchar botboottype[] = "bottom boot sector";
180   - uchar topboottype[] = "top boot sector";
181   -
182   - if (info->flash_id == FLASH_UNKNOWN) {
183   - printf("missing or unknown FLASH type\n");
184   - return;
185   - }
186   -
187   - switch (info->flash_id & FLASH_VENDMASK) {
188   - case FLASH_MAN_AMD:
189   - printf("AMD ");
190   - break;
191   - case FLASH_MAN_BM:
192   - printf("BRIGHT MICRO ");
193   - break;
194   - case FLASH_MAN_FUJ:
195   - printf("FUJITSU ");
196   - break;
197   - case FLASH_MAN_SST:
198   - printf("SST ");
199   - break;
200   - case FLASH_MAN_STM:
201   - printf("STM ");
202   - break;
203   - case FLASH_MAN_INTEL:
204   - printf("INTEL ");
205   - break;
206   - default:
207   - printf("Unknown Vendor ");
208   - break;
209   - }
210   -
211   - /* check for top or bottom boot, if it applies */
212   - if (info->flash_id & FLASH_BTYPE) {
213   - boottype = botboottype;
214   - bootletter = botbootletter;
215   - } else {
216   - boottype = topboottype;
217   - bootletter = topbootletter;
218   - }
219   -
220   - switch (info->flash_id & FLASH_TYPEMASK) {
221   - case FLASH_AM640U:
222   - fmt = "29LV641D (64 Mbit, uniform sectors)\n";
223   - break;
224   - case FLASH_28F800C3B:
225   - case FLASH_28F800C3T:
226   - fmt = "28F800C3%s (8 Mbit, %s)\n";
227   - break;
228   - case FLASH_INTEL800B:
229   - case FLASH_INTEL800T:
230   - fmt = "28F800B3%s (8 Mbit, %s)\n";
231   - break;
232   - case FLASH_28F160C3B:
233   - case FLASH_28F160C3T:
234   - fmt = "28F160C3%s (16 Mbit, %s)\n";
235   - break;
236   - case FLASH_INTEL160B:
237   - case FLASH_INTEL160T:
238   - fmt = "28F160B3%s (16 Mbit, %s)\n";
239   - break;
240   - case FLASH_28F320C3B:
241   - case FLASH_28F320C3T:
242   - fmt = "28F320C3%s (32 Mbit, %s)\n";
243   - break;
244   - case FLASH_INTEL320B:
245   - case FLASH_INTEL320T:
246   - fmt = "28F320B3%s (32 Mbit, %s)\n";
247   - break;
248   - case FLASH_28F640C3B:
249   - case FLASH_28F640C3T:
250   - fmt = "28F640C3%s (64 Mbit, %s)\n";
251   - break;
252   - case FLASH_INTEL640B:
253   - case FLASH_INTEL640T:
254   - fmt = "28F640B3%s (64 Mbit, %s)\n";
255   - break;
256   - default:
257   - fmt = "Unknown Chip Type\n";
258   - break;
259   - }
260   -
261   - printf(fmt, bootletter, boottype);
262   -
263   - printf(" Size: %ld MB in %d Sectors\n",
264   - info->size >> 20, info->sector_count);
265   -
266   - printf(" Sector Start Addresses:");
267   -
268   - for (i = 0; i < info->sector_count; ++i) {
269   - if ((i % 5) == 0) {
270   - printf("\n ");
271   - }
272   -
273   - printf(" %08lX%s", info->start[i],
274   - info->protect[i] ? " (RO)" : " ");
275   - }
276   -
277   - printf("\n");
278   -}
279   -
280   -/*-----------------------------------------------------------------------
281   - */
282   -
283   -/*
284   - * The following code cannot be run from FLASH!
285   - */
286   -
287   -#if 0
288   -ulong
289   -flash_get_size(FPWV * addr, flash_info_t * info)
290   -{
291   - /* Write auto select command: read Manufacturer ID */
292   -
293   - /* Write auto select command sequence and test FLASH answer */
294   - addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
295   - addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
296   - addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */
297   -
298   - /* The manufacturer codes are only 1 byte, so just use 1 byte.
299   - * This works for any bus width and any FLASH device width.
300   - */
301   - switch (addr[0] & 0xff) {
302   -
303   - case (uchar) AMD_MANUFACT:
304   - info->flash_id = FLASH_MAN_AMD;
305   - break;
306   -
307   - case (uchar) INTEL_MANUFACT:
308   - info->flash_id = FLASH_MAN_INTEL;
309   - break;
310   -
311   - default:
312   - info->flash_id = FLASH_UNKNOWN;
313   - info->sector_count = 0;
314   - info->size = 0;
315   - break;
316   - }
317   -
318   - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
319   - if (info->flash_id != FLASH_UNKNOWN)
320   - switch (addr[1]) {
321   -
322   - case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
323   - info->flash_id += FLASH_AM640U;
324   - info->sector_count = 128;
325   - info->size = 0x00800000 * (sizeof (FPW) / 2);
326   - break; /* => 8 or 16 MB */
327   -
328   - case (FPW) INTEL_ID_28F800C3B:
329   - info->flash_id += FLASH_28F800C3B;
330   - info->sector_count = 23;
331   - info->size = 0x00100000 * (sizeof (FPW) / 2);
332   - break; /* => 1 or 2 MB */
333   -
334   - case (FPW) INTEL_ID_28F800B3B:
335   - info->flash_id += FLASH_INTEL800B;
336   - info->sector_count = 23;
337   - info->size = 0x00100000 * (sizeof (FPW) / 2);
338   - break; /* => 1 or 2 MB */
339   -
340   - case (FPW) INTEL_ID_28F160C3B:
341   - info->flash_id += FLASH_28F160C3B;
342   - info->sector_count = 39;
343   - info->size = 0x00200000 * (sizeof (FPW) / 2);
344   - break; /* => 2 or 4 MB */
345   -
346   - case (FPW) INTEL_ID_28F160B3B:
347   - info->flash_id += FLASH_INTEL160B;
348   - info->sector_count = 39;
349   - info->size = 0x00200000 * (sizeof (FPW) / 2);
350   - break; /* => 2 or 4 MB */
351   -
352   - case (FPW) INTEL_ID_28F320C3B:
353   - info->flash_id += FLASH_28F320C3B;
354   - info->sector_count = 71;
355   - info->size = 0x00400000 * (sizeof (FPW) / 2);
356   - break; /* => 4 or 8 MB */
357   -
358   - case (FPW) INTEL_ID_28F320B3B:
359   - info->flash_id += FLASH_INTEL320B;
360   - info->sector_count = 71;
361   - info->size = 0x00400000 * (sizeof (FPW) / 2);
362   - break; /* => 4 or 8 MB */
363   -
364   - case (FPW) INTEL_ID_28F640C3B:
365   - info->flash_id += FLASH_28F640C3B;
366   - info->sector_count = 135;
367   - info->size = 0x00800000 * (sizeof (FPW) / 2);
368   - break; /* => 8 or 16 MB */
369   -
370   - case (FPW) INTEL_ID_28F640B3B:
371   - info->flash_id += FLASH_INTEL640B;
372   - info->sector_count = 135;
373   - info->size = 0x00800000 * (sizeof (FPW) / 2);
374   - break; /* => 8 or 16 MB */
375   -
376   - default:
377   - info->flash_id = FLASH_UNKNOWN;
378   - info->sector_count = 0;
379   - info->size = 0;
380   - return (0); /* => no or unknown flash */
381   - }
382   -
383   - flash_get_offsets((ulong) addr, info);
384   -
385   - /* Put FLASH back in read mode */
386   - flash_reset(info);
387   -
388   - return (info->size);
389   -}
390   -#endif /* 0 */
391   -
392   -#ifdef CONFIG_SYS_FLASH_PROTECTION
393   -/*-----------------------------------------------------------------------
394   - */
395   -
396   -static void
397   -flash_sync_real_protect(flash_info_t * info)
398   -{
399   - FPWV *addr = (FPWV *) (info->start[0]);
400   - FPWV *sect;
401   - int i;
402   -
403   - switch (info->flash_id & FLASH_TYPEMASK) {
404   - case FLASH_28F800C3B:
405   - case FLASH_28F800C3T:
406   - case FLASH_28F160C3B:
407   - case FLASH_28F160C3T:
408   - case FLASH_28F320C3B:
409   - case FLASH_28F320C3T:
410   - case FLASH_28F640C3B:
411   - case FLASH_28F640C3T:
412   - /* check for protected sectors */
413   - *addr = (FPW) 0x00900090;
414   - for (i = 0; i < info->sector_count; i++) {
415   - /* read sector protection at sector address, (A7 .. A0) = 0x02.
416   - * D0 = 1 for each device if protected.
417   - * If at least one device is protected the sector is marked
418   - * protected, but mixed protected and unprotected devices
419   - * within a sector should never happen.
420   - */
421   - sect = (FPWV *) (info->start[i]);
422   - info->protect[i] =
423   - (sect[2] & (FPW) (0x00010001)) ? 1 : 0;
424   - }
425   -
426   - /* Put FLASH back in read mode */
427   - flash_reset(info);
428   - break;
429   -
430   - case FLASH_AM640U:
431   - default:
432   - /* no hardware protect that we support */
433   - break;
434   - }
435   -}
436   -#endif
437   -
438   -/*-----------------------------------------------------------------------
439   - */
440   -
441   -int
442   -flash_erase(flash_info_t * info, int s_first, int s_last)
443   -{
444   - FPWV *addr;
445   - int flag, prot, sect;
446   - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
447   - ulong start, now, last;
448   - int rcode = 0;
449   -
450   - if ((s_first < 0) || (s_first > s_last)) {
451   - if (info->flash_id == FLASH_UNKNOWN) {
452   - printf("- missing\n");
453   - } else {
454   - printf("- no sectors to erase\n");
455   - }
456   - return 1;
457   - }
458   -
459   - switch (info->flash_id & FLASH_TYPEMASK) {
460   - case FLASH_INTEL800B:
461   - case FLASH_INTEL160B:
462   - case FLASH_INTEL320B:
463   - case FLASH_INTEL640B:
464   - case FLASH_28F800C3B:
465   - case FLASH_28F160C3B:
466   - case FLASH_28F320C3B:
467   - case FLASH_28F640C3B:
468   - case FLASH_AM640U:
469   - break;
470   - case FLASH_UNKNOWN:
471   - default:
472   - printf("Can't erase unknown flash type %08lx - aborted\n",
473   - info->flash_id);
474   - return 1;
475   - }
476   -
477   - prot = 0;
478   - for (sect = s_first; sect <= s_last; ++sect) {
479   - if (info->protect[sect]) {
480   - prot++;
481   - }
482   - }
483   -
484   - if (prot) {
485   - printf("- Warning: %d protected sectors will not be erased!\n",
486   - prot);
487   - } else {
488   - printf("\n");
489   - }
490   -
491   - start = get_timer(0);
492   - last = start;
493   -
494   - /* Start erase on unprotected sectors */
495   - for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
496   -
497   - if (info->protect[sect] != 0) /* protected, skip it */
498   - continue;
499   -
500   - /* Disable interrupts which might cause a timeout here */
501   - flag = disable_interrupts();
502   -
503   - addr = (FPWV *) (info->start[sect]);
504   - if (intel) {
505   - *addr = (FPW) 0x00500050; /* clear status register */
506   - *addr = (FPW) 0x00200020; /* erase setup */
507   - *addr = (FPW) 0x00D000D0; /* erase confirm */
508   - } else {
509   - /* must be AMD style if not Intel */
510   - FPWV *base; /* first address in bank */
511   -
512   - base = (FPWV *) (info->start[0]);
513   - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
514   - base[0x02AA] = (FPW) 0x00550055; /* unlock */
515   - base[0x0555] = (FPW) 0x00800080; /* erase mode */
516   - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
517   - base[0x02AA] = (FPW) 0x00550055; /* unlock */
518   - *addr = (FPW) 0x00300030; /* erase sector */
519   - }
520   -
521   - /* re-enable interrupts if necessary */
522   - if (flag)
523   - enable_interrupts();
524   -
525   - /* wait at least 50us for AMD, 80us for Intel.
526   - * Let's wait 1 ms.
527   - */
528   - udelay(1000);
529   -
530   - while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
531   - if ((now = get_timer(0)) - start > CONFIG_SYS_FLASH_ERASE_TOUT) {
532   - printf("Timeout\n");
533   -
534   - if (intel) {
535   - /* suspend erase */
536   - *addr = (FPW) 0x00B000B0;
537   - }
538   -
539   - flash_reset(info); /* reset to read mode */
540   - rcode = 1; /* failed */
541   - break;
542   - }
543   -
544   - /* show that we're waiting */
545   - if ((now - last) > 1000) { /* every second */
546   - putc('.');
547   - last = now;
548   - }
549   - }
550   -
551   - flash_reset(info); /* reset to read mode */
552   - }
553   -
554   - printf(" done\n");
555   - return rcode;
556   -}
557   -
558   -/*-----------------------------------------------------------------------
559   - * Copy memory to flash, returns:
560   - * 0 - OK
561   - * 1 - write timeout
562   - * 2 - Flash not erased
563   - */
564   -int
565   -bad_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
566   -{
567   - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
568   - int bytes; /* number of bytes to program in current word */
569   - int left; /* number of bytes left to program */
570   - int i, res;
571   -
572   - for (left = cnt, res = 0;
573   - left > 0 && res == 0;
574   - addr += sizeof (data), left -= sizeof (data) - bytes) {
575   -
576   - bytes = addr & (sizeof (data) - 1);
577   - addr &= ~(sizeof (data) - 1);
578   -
579   - /* combine source and destination data so can program
580   - * an entire word of 16 or 32 bits
581   - */
582   - for (i = 0; i < sizeof (data); i++) {
583   - data <<= 8;
584   - if (i < bytes || i - bytes >= left)
585   - data += *((uchar *) addr + i);
586   - else
587   - data += *src++;
588   - }
589   -
590   - /* write one word to the flash */
591   - switch (info->flash_id & FLASH_VENDMASK) {
592   - case FLASH_MAN_AMD:
593   - res = write_word_amd(info, (FPWV *) addr, data);
594   - break;
595   - case FLASH_MAN_INTEL:
596   - res = write_word_intel(info, (FPWV *) addr, data);
597   - break;
598   - default:
599   - /* unknown flash type, error! */
600   - printf("missing or unknown FLASH type\n");
601   - res = 1; /* not really a timeout, but gives error */
602   - break;
603   - }
604   - }
605   -
606   - return (res);
607   -}
608   -
609   -/**
610   - * write_buf: - Copy memory to flash.
611   - *
612   - * @param info:
613   - * @param src: source of copy transaction
614   - * @param addr: where to copy to
615   - * @param cnt: number of bytes to copy
616   - *
617   - * @return error code
618   - */
619   -
620   -int
621   -write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
622   -{
623   - ulong cp, wp;
624   - FPW data;
625   - int l;
626   - int i, rc;
627   -
628   - wp = (addr & ~1); /* get lower word aligned address */
629   -
630   - /* handle unaligned start bytes */
631   - if ((l = addr - wp) != 0) {
632   - data = 0;
633   - for (i = 0, cp = wp; i < l; ++i, ++cp) {
634   - data = (data >> 8) | (*(uchar *) cp << 8);
635   - }
636   - for (; i < 2 && cnt > 0; ++i) {
637   - data = (data >> 8) | (*src++ << 8);
638   - --cnt;
639   - ++cp;
640   - }
641   - for (; cnt == 0 && i < 2; ++i, ++cp) {
642   - data = (data >> 8) | (*(uchar *) cp << 8);
643   - }
644   -
645   - if ((rc = write_word(info, (FPWV *)wp, data)) != 0) {
646   - return (rc);
647   - }
648   - wp += 2;
649   - }
650   -
651   - /* handle word aligned part */
652   - while (cnt >= 2) {
653   - /* data = *((vushort*)src); */
654   - data = *((FPW *) src);
655   - if ((rc = write_word(info, (FPWV *)wp, data)) != 0) {
656   - return (rc);
657   - }
658   - src += sizeof (FPW);
659   - wp += sizeof (FPW);
660   - cnt -= sizeof (FPW);
661   - }
662   -
663   - if (cnt == 0)
664   - return ERR_OK;
665   -
666   - /*
667   - * handle unaligned tail bytes
668   - */
669   - data = 0;
670   - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
671   - data = (data >> 8) | (*src++ << 8);
672   - --cnt;
673   - }
674   - for (; i < 2; ++i, ++cp) {
675   - data = (data >> 8) | (*(uchar *) cp << 8);
676   - }
677   -
678   - return write_word(info, (FPWV *)wp, data);
679   -}
680   -
681   -/*-----------------------------------------------------------------------
682   - * Write a word to Flash for AMD FLASH
683   - * A word is 16 or 32 bits, whichever the bus width of the flash bank
684   - * (not an individual chip) is.
685   - *
686   - * returns:
687   - * 0 - OK
688   - * 1 - write timeout
689   - * 2 - Flash not erased
690   - */
691   -static int
692   -write_word_amd(flash_info_t * info, FPWV * dest, FPW data)
693   -{
694   - ulong start;
695   - int flag;
696   - int res = 0; /* result, assume success */
697   - FPWV *base; /* first address in flash bank */
698   -
699   - /* Check if Flash is (sufficiently) erased */
700   - if ((*dest & data) != data) {
701   - return (2);
702   - }
703   -
704   - base = (FPWV *) (info->start[0]);
705   - /* Disable interrupts which might cause a timeout here */
706   - flag = disable_interrupts();
707   -
708   - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
709   - base[0x02AA] = (FPW) 0x00550055; /* unlock */
710   - base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */
711   -
712   - *dest = data; /* start programming the data */
713   -
714   - /* re-enable interrupts if necessary */
715   - if (flag)
716   - enable_interrupts();
717   -
718   - start = get_timer(0);
719   -
720   - /* data polling for D7 */
721   - while (res == 0
722   - && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
723   - if (get_timer(0) - start > CONFIG_SYS_FLASH_WRITE_TOUT) {
724   - *dest = (FPW) 0x00F000F0; /* reset bank */
725   - printf("SHA timeout\n");
726   - res = 1;
727   - }
728   - }
729   -
730   - return (res);
731   -}
732   -
733   -/*-----------------------------------------------------------------------
734   - * Write a word to Flash for Intel FLASH
735   - * A word is 16 or 32 bits, whichever the bus width of the flash bank
736   - * (not an individual chip) is.
737   - *
738   - * returns:
739   - * 0 - OK
740   - * 1 - write timeout
741   - * 2 - Flash not erased
742   - */
743   -static int
744   -write_word_intel(flash_info_t * info, FPWV * dest, FPW data)
745   -{
746   - ulong start;
747   - int flag;
748   - int res = 0; /* result, assume success */
749   -
750   - /* Check if Flash is (sufficiently) erased */
751   - if ((*dest & data) != data) {
752   - return (2);
753   - }
754   -
755   - /* Disable interrupts which might cause a timeout here */
756   - flag = disable_interrupts();
757   -
758   - *dest = (FPW) 0x00500050; /* clear status register */
759   - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */
760   - *dest = (FPW) 0x00400040; /* program setup */
761   -
762   - *dest = data; /* start programming the data */
763   -
764   - /* re-enable interrupts if necessary */
765   - if (flag)
766   - enable_interrupts();
767   -
768   - start = get_timer(0);
769   -
770   - while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
771   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
772   - *dest = (FPW) 0x00B000B0; /* Suspend program */
773   - res = 1;
774   - }
775   - }
776   -
777   - if (res == 0 && (*dest & (FPW) 0x00100010))
778   - res = 1; /* write failed, time out error is close enough */
779   -
780   - *dest = (FPW) 0x00500050; /* clear status register */
781   - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */
782   -
783   - return (res);
784   -}
785   -
786   -#ifdef CONFIG_SYS_FLASH_PROTECTION
787   -/*-----------------------------------------------------------------------
788   - */
789   -int
790   -flash_real_protect(flash_info_t * info, long sector, int prot)
791   -{
792   - int rcode = 0; /* assume success */
793   - FPWV *addr; /* address of sector */
794   - FPW value;
795   -
796   - addr = (FPWV *) (info->start[sector]);
797   -
798   - switch (info->flash_id & FLASH_TYPEMASK) {
799   - case FLASH_28F800C3B:
800   - case FLASH_28F800C3T:
801   - case FLASH_28F160C3B:
802   - case FLASH_28F160C3T:
803   - case FLASH_28F320C3B:
804   - case FLASH_28F320C3T:
805   - case FLASH_28F640C3B:
806   - case FLASH_28F640C3T:
807   - flash_reset(info); /* make sure in read mode */
808   - *addr = (FPW) 0x00600060L; /* lock command setup */
809   - if (prot)
810   - *addr = (FPW) 0x00010001L; /* lock sector */
811   - else
812   - *addr = (FPW) 0x00D000D0L; /* unlock sector */
813   - flash_reset(info); /* reset to read mode */
814   -
815   - /* now see if it really is locked/unlocked as requested */
816   - *addr = (FPW) 0x00900090;
817   - /* read sector protection at sector address, (A7 .. A0) = 0x02.
818   - * D0 = 1 for each device if protected.
819   - * If at least one device is protected the sector is marked
820   - * protected, but return failure. Mixed protected and
821   - * unprotected devices within a sector should never happen.
822   - */
823   - value = addr[2] & (FPW) 0x00010001;
824   - if (value == 0)
825   - info->protect[sector] = 0;
826   - else if (value == (FPW) 0x00010001)
827   - info->protect[sector] = 1;
828   - else {
829   - /* error, mixed protected and unprotected */
830   - rcode = 1;
831   - info->protect[sector] = 1;
832   - }
833   - if (info->protect[sector] != prot)
834   - rcode = 1; /* failed to protect/unprotect as requested */
835   -
836   - /* reload all protection bits from hardware for now */
837   - flash_sync_real_protect(info);
838   - break;
839   -
840   - case FLASH_AM640U:
841   - default:
842   - /* no hardware protect that we support */
843   - info->protect[sector] = prot;
844   - break;
845   - }
846   -
847   - return rcode;
848   -}
849   -#endif
board/mx1fs2/intel.h
View file @ 6962419
1   -/*
2   - * Copyright (C) 2002 ETC s.r.o.
3   - * All rights reserved.
4   - *
5   - * Redistribution and use in source and binary forms, with or without
6   - * modification, are permitted provided that the following conditions
7   - * are met:
8   - * 1. Redistributions of source code must retain the above copyright
9   - * notice, this list of conditions and the following disclaimer.
10   - * 2. Redistributions in binary form must reproduce the above copyright
11   - * notice, this list of conditions and the following disclaimer in the
12   - * documentation and/or other materials provided with the distribution.
13   - * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
14   - * may be used to endorse or promote products derived from this software
15   - * without specific prior written permission.
16   - *
17   - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18   - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19   - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20   - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
21   - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22   - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23   - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
24   - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25   - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26   - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27   - *
28   - * Written by Marcel Telka <marcel@telka.sk>, 2002.
29   - *
30   - * Documentation:
31   - * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
32   - * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
33   - * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
34   - * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
35   - *
36   - * This file is taken from OpenWinCE project hosted by SourceForge.net
37   - *
38   - */
39   -
40   -#ifndef FLASH_INTEL_H
41   -#define FLASH_INTEL_H
42   -
43   -#include <common.h>
44   -
45   -/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
46   -
47   -#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
48   -#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
49   -#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
50   -#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
51   -#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
52   -#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
53   -#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
54   -#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
55   -#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
56   -#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
57   -#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
58   -#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
59   -#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
60   -#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
61   -#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
62   -#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
63   -
64   -/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
65   -
66   -#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
67   -#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
68   -#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
69   -#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
70   -#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
71   -#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
72   -#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
73   -#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
74   -
75   -/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
76   -
77   -#define CFI_CHIP_INTEL_28F320J3A 0x0016
78   -#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
79   -#define CFI_CHIP_INTEL_28F640J3A 0x0017
80   -#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
81   -#define CFI_CHIP_INTEL_28F128J3A 0x0018
82   -#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
83   -
84   -/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
85   -
86   -#define CFI_CHIP_INTEL_28F640K3 0x8801
87   -#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
88   -#define CFI_CHIP_INTEL_28F128K3 0x8802
89   -#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
90   -#define CFI_CHIP_INTEL_28F256K3 0x8803
91   -#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
92   -#define CFI_CHIP_INTEL_28F640K18 0x8805
93   -#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
94   -#define CFI_CHIP_INTEL_28F128K18 0x8806
95   -#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
96   -#define CFI_CHIP_INTEL_28F256K18 0x8807
97   -#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
98   -
99   -#endif /* FLASH_INTEL_H */
board/mx1fs2/lowlevel_init.S
View file @ 6962419
1   -/*
2   - * Copyright (C) 2004 Sascha Hauer, Pengutronix
3   - *
4   - * This program is free software; you can redistribute it and/or
5   - * modify it under the terms of the GNU General Public License
6   - * as published by the Free Software Foundation; either version 2
7   - * of the License, or (at your option) any later version.
8   - *
9   - * This program is distributed in the hope that it will be useful,
10   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
11   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12   - * GNU General Public License for more details.
13   - *
14   - * You should have received a copy of the GNU General Public License
15   - * along with this program; if not, write to the Free Software
16   - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
17   - * 02111-1307, USA.
18   - *
19   - */
20   -
21   -#include <config.h>
22   -#include <version.h>
23   -#include <asm/arch/imx-regs.h>
24   -
25   -.globl lowlevel_init
26   -lowlevel_init:
27   -
28   - mov r10, lr
29   -
30   -/* Change PERCLK1DIV to 14 ie 14+1 */
31   - ldr r0, =PCDR
32   - ldr r1, =CONFIG_SYS_PCDR_VAL
33   - str r1, [r0]
34   -
35   -/* set MCU PLL Control Register 0 */
36   -
37   - ldr r0, =MPCTL0
38   - ldr r1, =CONFIG_SYS_MPCTL0_VAL
39   - str r1, [r0]
40   -
41   -/* set MCU PLL Control Register 1 */
42   -
43   - ldr r0, =MPCTL1
44   - ldr r1, =CONFIG_SYS_MPCTL1_VAL
45   - str r1, [r0]
46   -
47   -/* set mpll restart bit */
48   - ldr r0, =CSCR
49   - ldr r1, [r0]
50   - orr r1,r1,#(1<<21)
51   - str r1, [r0]
52   -
53   - mov r2,#0x10
54   -1:
55   - mov r3,#0x2000
56   -2:
57   - subs r3,r3,#1
58   - bne 2b
59   -
60   - subs r2,r2,#1
61   - bne 1b
62   -
63   -/* set System PLL Control Register 0 */
64   -
65   - ldr r0, =SPCTL0
66   - ldr r1, =CONFIG_SYS_SPCTL0_VAL
67   - str r1, [r0]
68   -
69   -/* set System PLL Control Register 1 */
70   -
71   - ldr r0, =SPCTL1
72   - ldr r1, =CONFIG_SYS_SPCTL1_VAL
73   - str r1, [r0]
74   -
75   -/* set spll restart bit */
76   - ldr r0, =CSCR
77   - ldr r1, [r0]
78   - orr r1,r1,#(1<<22)
79   - str r1, [r0]
80   -
81   - mov r2,#0x10
82   -1:
83   - mov r3,#0x2000
84   -2:
85   - subs r3,r3,#1
86   - bne 2b
87   -
88   - subs r2,r2,#1
89   - bne 1b
90   -
91   - ldr r0, =CSCR
92   - ldr r1, =CONFIG_SYS_CSCR_VAL
93   - str r1, [r0]
94   -
95   - ldr r0, =GPCR
96   - ldr r1, =CONFIG_SYS_GPCR_VAL
97   - str r1, [r0]
98   -
99   -/*
100   - * I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
101   - * this.....
102   - *
103   - * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
104   - * register 1, this stops it using the output of the PLL and thus runs at the
105   - * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
106   - * use the value set in the CM_OSC registers...regardless of what you set it
107   - * too! Thus, although i thought i was running at 140MHz, i'm actually running
108   - * at 40!..
109   - *
110   - * Slapping this into my bootloader does the trick...
111   - *
112   - * MRC p15,0,r0,c1,c0,0 ; read core configuration register
113   - * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
114   - * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
115   - * register
116   - *
117   - */
118   - MRC p15,0,r0,c1,c0,0
119   -/* ORR r0,r0,#0xC0000000 async mode */
120   -/* ORR r0,r0,#0x40000000 sync mode */
121   - ORR r0,r0,#0xC0000000
122   - MCR p15,0,r0,c1,c0,0
123   -
124   - ldr r0, =GIUS(0)
125   - ldr r1, =CONFIG_SYS_GIUS_A_VAL
126   - str r1, [r0]
127   -
128   - ldr r0, =FMCR
129   - ldr r1, =CONFIG_SYS_FMCR_VAL
130   - str r1, [r0]
131   -
132   - ldr r0, =CS0U
133   - ldr r1, =CONFIG_SYS_CS0U_VAL
134   - str r1, [r0]
135   -
136   - ldr r0, =CS0L
137   - ldr r1, =CONFIG_SYS_CS0L_VAL
138   - str r1, [r0]
139   -
140   - ldr r0, =CS1U
141   - ldr r1, =CONFIG_SYS_CS1U_VAL
142   - str r1, [r0]
143   -
144   - ldr r0, =CS1L
145   - ldr r1, =CONFIG_SYS_CS1L_VAL
146   - str r1, [r0]
147   -
148   - ldr r0, =CS4U
149   - ldr r1, =CONFIG_SYS_CS4U_VAL
150   - str r1, [r0]
151   -
152   - ldr r0, =CS4L
153   - ldr r1, =CONFIG_SYS_CS4L_VAL
154   - str r1, [r0]
155   -
156   - ldr r0, =CS5U
157   - ldr r1, =CONFIG_SYS_CS5U_VAL
158   - str r1, [r0]
159   -
160   - ldr r0, =CS5L
161   - ldr r1, =CONFIG_SYS_CS5L_VAL
162   - str r1, [r0]
163   -
164   -/* SDRAM Setup */
165   -
166   - ldr r1,=0x00221000 /* adr of SDCTRL0 */
167   - ldr r0,=0x92120200
168   - str r0,[r1,#0] /* put in precharge command mode */
169   - ldr r2,=0x08200000 /* adr for precharge cmd */
170   - ldr r0,[r2,#0] /* precharge */
171   - ldr r0,=0xA2120200
172   - ldr r2,=0x08000000 /* start of SDRAM */
173   - str r0,[r1,#0] /* put in auto-refresh mode */
174   - ldr r0,[r2,#0] /* auto-refresh */
175   - ldr r0,[r2,#0] /* auto-refresh */
176   - ldr r0,[r2,#0] /* auto-refresh */
177   - ldr r0,[r2,#0] /* auto-refresh */
178   - ldr r0,[r2,#0] /* auto-refresh */
179   - ldr r0,[r2,#0] /* auto-refresh */
180   - ldr r0,[r2,#0] /* auto-refresh */
181   - ldr r0,=0xB2120200
182   - ldr r2,=0x08111800
183   - str r0,[r1,#0] /* setup for mode register of SDRAM */
184   - ldr r0,[r2,#0] /* program mode register */
185   - ldr r0,=0x82124267
186   - str r0,[r1,#0] /* back to normal operation */
187   -
188   - mov pc,r10
board/mx1fs2/mx1fs2.c
View file @ 6962419
1   -/*
2   - * Copyright (C) 2004 Sascha Hauer, Pengutronix
3   - *
4   - * This program is free software; you can redistribute it and/or
5   - * modify it under the terms of the GNU General Public License as
6   - * published by the Free Software Foundation; either version 2 of
7   - * the License, or (at your option) any later version.
8   - *
9   - * This program is distributed in the hope that it will be useful,
10   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
11   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12   - * GNU General Public License for more details.
13   - *
14   - * You should have received a copy of the GNU General Public License
15   - * along with this program; if not, write to the Free Software
16   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17   - * MA 02111-1307 USA
18   - *
19   - */
20   -
21   -#include <common.h>
22   -#include <asm/arch/imx-regs.h>
23   -
24   -DECLARE_GLOBAL_DATA_PTR;
25   -
26   -#define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
27   -
28   -extern void imx_gpio_mode(int gpio_mode);
29   -
30   -static void logo_init(void)
31   -{
32   - imx_gpio_mode(PD15_PF_LD0);
33   - imx_gpio_mode(PD16_PF_LD1);
34   - imx_gpio_mode(PD17_PF_LD2);
35   - imx_gpio_mode(PD18_PF_LD3);
36   - imx_gpio_mode(PD19_PF_LD4);
37   - imx_gpio_mode(PD20_PF_LD5);
38   - imx_gpio_mode(PD21_PF_LD6);
39   - imx_gpio_mode(PD22_PF_LD7);
40   - imx_gpio_mode(PD23_PF_LD8);
41   - imx_gpio_mode(PD24_PF_LD9);
42   - imx_gpio_mode(PD25_PF_LD10);
43   - imx_gpio_mode(PD26_PF_LD11);
44   - imx_gpio_mode(PD27_PF_LD12);
45   - imx_gpio_mode(PD28_PF_LD13);
46   - imx_gpio_mode(PD29_PF_LD14);
47   - imx_gpio_mode(PD30_PF_LD15);
48   - imx_gpio_mode(PD14_PF_FLM_VSYNC);
49   - imx_gpio_mode(PD13_PF_LP_HSYNC);
50   - imx_gpio_mode(PD6_PF_LSCLK);
51   - imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_DR);
52   - imx_gpio_mode(PD11_PF_CONTRAST);
53   - imx_gpio_mode(PD10_PF_SPL_SPR);
54   -
55   - LCDC_RMCR = 0x00000000;
56   - LCDC_PCR = PCR_COLOR | PCR_PBSIZ_8 | PCR_BPIX_16 | PCR_PCD(5);
57   - LCDC_HCR = HCR_H_WIDTH(2);
58   - LCDC_VCR = VCR_V_WIDTH(2);
59   -
60   - LCDC_PWMR = 0x00000380; /* contrast to 0x80 middle (is best !!!) */
61   - LCDC_SSA = 0x10040000; /* image in flash */
62   -
63   - LCDC_SIZE = SIZE_XMAX(320) | SIZE_YMAX(240); /* screen size */
64   -
65   - LCDC_VPW = 0x000000A0; /* Virtual Page Width Register */
66   - LCDC_POS = 0x00000000; /* panning offset 0 (0 pixel offset) */
67   -
68   - /* disable Cursor */
69   - LCDC_CPOS = 0x00000000;
70   -
71   - /* fixed burst length */
72   - LCDC_DMACR = DMACR_BURST | DMACR_HM(8) | DMACR_TM(2);
73   -
74   - /* enable LCD */
75   - DR(3) |= 0x00001000;
76   - LCDC_RMCR = RMCR_LCDC_EN;
77   -
78   -}
79   -
80   -int
81   -board_init(void)
82   -{
83   - gd->bd->bi_arch_number = MACH_TYPE_MX1FS2;
84   - gd->bd->bi_boot_params = 0x08000100;
85   -serial_init();
86   - logo_init();
87   - return 0;
88   -}
89   -
90   -int
91   -dram_init(void)
92   -{
93   -#if ( CONFIG_NR_DRAM_BANKS > 0 )
94   - gd->bd->bi_dram[0].start = MX1FS2_SDRAM_1;
95   - gd->bd->bi_dram[0].size = MX1FS2_SDRAM_1_SIZE;
96   -#endif
97   - return 0;
98   -}
99   -
100   -/**
101   - * show_boot_progress: - indicate state of the boot process
102   - *
103   - * @param status: Status number - see README for details.
104   - *
105   - */
106   -
107   -void
108   -show_boot_progress(int status)
109   -{
110   - /* We use this as a hook to disable serial ports just before booting
111   - * This way we suppress the "uncompressing linux..." message
112   - */
113   -#ifdef CONFIG_SILENT_CONSOLE
114   - if( status == 8) {
115   - if( getenv("silent") != NULL ) {
116   - *(volatile unsigned long *)0x206080 &= ~1;
117   - *(volatile unsigned long *)0x207080 &= ~1;
118   - }
119   - }
120   -#endif
121   - return;
122   -}
... ... @@ -63,7 +63,6 @@
63 63 m501sk arm arm920t - - at91rm9200
64 64 at91rm9200dk arm arm920t - atmel at91rm9200
65 65 mx1ads arm arm920t - - imx
66   -mx1fs2 arm arm920t - - imx
67 66 scb9328 arm arm920t - - imx
68 67 cm4008 arm arm920t - - ks8695
69 68 cm41xx arm arm920t - - ks8695
doc/README.scrapyard
Diff comments   View file @ 6962419
... ... @@ -11,6 +11,7 @@
11 11  
12 12 Board Arch CPU removed Commit last known maintainer/contact
13 13 =============================================================================
  14 +mx1fs2 arm arm920t - 2011-07-17
14 15 lpd7a404 arm lh7a40x - 2011-07-17
15 16 edb9301 arm arm920t - 2011-07-17
16 17 edb9302 arm arm920t - 2011-07-17
include/configs/mx1fs2.h
View file @ 6962419
1   -/*
2   - * Copyright (C) 2004 Sascha Hauer, Pengutronix
3   - *
4   - * This program is free software; you can redistribute it and/or
5   - * modify it under the terms of the GNU General Public License as
6   - * published by the Free Software Foundation; either version 2 of
7   - * the License, or (at your option) any later version.
8   - *
9   - * This program is distributed in the hope that it will be useful,
10   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
11   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12   - * GNU General Public License for more details.
13   - *
14   - * You should have received a copy of the GNU General Public License
15   - * along with this program; if not, write to the Free Software
16   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17   - * MA 02111-1307 USA
18   - */
19   -
20   -#ifndef __CONFIG_H
21   -#define __CONFIG_H
22   -
23   -#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
24   -#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
25   -#define CONFIG_MX1FS2 1 /* on a mx1fs2 board */
26   -#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
27   -
28   -/*
29   - * Select serial console configuration
30   - */
31   -#undef _CONFIG_UART1 /* internal uart 1 */
32   -#define _CONFIG_UART2 /* internal uart 2 */
33   -#undef _CONFIG_UART3 /* internal uart 3 */
34   -#undef _CONFIG_UART4 /* internal uart 4 */
35   -#undef CONFIG_SILENT_CONSOLE /* use this to disable output */
36   -
37   -/*
38   - * BOOTP options
39   - */
40   -#define CONFIG_BOOTP_BOOTFILESIZE
41   -#define CONFIG_BOOTP_BOOTPATH
42   -#define CONFIG_BOOTP_GATEWAY
43   -#define CONFIG_BOOTP_HOSTNAME
44   -
45   -/*
46   - * Command line configuration.
47   - */
48   -#include <config_cmd_default.h>
49   -
50   -#define CONFIG_CMD_JFFS2
51   -
52   -#undef CONFIG_CMD_CONSOLE
53   -#undef CONFIG_CMD_DHCP
54   -#undef CONFIG_CMD_LOADS
55   -#undef CONFIG_CMD_NET
56   -#undef CONFIG_CMD_PING
57   -#undef CONFIG_CMD_SOURCE
58   -
59   -/*
60   - * Boot options. Setting delay to -1 stops autostart count down.
61   - */
62   -#define CONFIG_BOOTDELAY 10
63   -#define CONFIG_BOOTARGS "root=/dev/mtdblock4 console=ttySMX0,115200n8 rootfstype=jffs2"
64   -#define CONFIG_BOOTCOMMAND "bootm 10080000"
65   -#define CONFIG_SHOW_BOOT_PROGRESS
66   -
67   -/*
68   - * General options for u-boot. Modify to save memory foot print
69   - */
70   -#define CONFIG_SYS_LONGHELP /* undef saves memory */
71   -#define CONFIG_SYS_PROMPT "mx1fs2> " /* prompt string */
72   -#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
73   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
74   -#define CONFIG_SYS_MAXARGS 16 /* max command args */
75   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
76   -
77   -#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */
78   -#define CONFIG_SYS_MEMTEST_END 0x08F00000
79   -
80   -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
81   -#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
82   -
83   -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
84   -#define CONFIG_BAUDRATE 115200
85   -/*
86   - * Definitions related to passing arguments to kernel.
87   - */
88   -#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
89   -#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
90   -#define CONFIG_INITRD_TAG 1 /* send initrd params */
91   -
92   -/*
93   - * Malloc pool need to host env + 128 Kb reserve for other allocations.
94   - */
95   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
96   -
97   -#define CONFIG_STACKSIZE (120<<10) /* stack size */
98   -
99   -#ifdef CONFIG_USE_IRQ
100   -#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
101   -#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
102   -#endif
103   -
104   -/* SDRAM Setup Values
105   - * 0x910a8300 Precharge Command CAS 3
106   - * 0x910a8200 Precharge Command CAS 2
107   - *
108   - * 0xa10a8300 AutoRefresh Command CAS 3
109   - * 0xa10a8200 Set AutoRefresh Command CAS 2
110   - */
111   -#define PRECHARGE_CMD 0x910a8300
112   -#define AUTOREFRESH_CMD 0xa10a8300
113   -
114   -#define BUS32BIT_VERSION
115   -/*
116   - * SDRAM Memory Map
117   - */
118   -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
119   -#define MX1FS2_SDRAM_1 0x08000000 /* SDRAM bank #1 */
120   -#ifdef BUS32BIT_VERSION
121   -#define MX1FS2_SDRAM_1_SIZE (0x04000000 - 0x100000) /* 64 MB - 1M Framebuffer */
122   -#else
123   -#define MX1FS2_SDRAM_1_SIZE (0x01FC0000 - 0x100000) /* 32 MB - 1M Framebuffer */
124   -#endif
125   -/*
126   - * Flash Controller settings
127   - */
128   -
129   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
130   -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
131   -
132   -#ifdef BUS32BIT_VERSION
133   -#define MX1FS2_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */
134   -#define MX1FS2_FLASH_INTERLEAVE 2 /* ... made of 2 chips */
135   -#define MX1FS2_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank*/
136   -#define MX1FS2_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
137   -#else
138   -#define MX1FS2_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
139   -#define MX1FS2_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
140   -#define MX1FS2_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank*/
141   -#define MX1FS2_FLASH_SECT_SIZE 0x00010000 /* size of erase sector */
142   -#endif
143   -#define MX1FS2_FLASH_BASE 0x10000000 /* location of flash memory */
144   -#define MX1FS2_FLASH_UNLOCK 1 /* perform hw unlock first */
145   -
146   -/* This should be defined if CFI FLASH device is present. Actually benefit
147   - is not so clear to me. In other words we can provide more informations
148   - to user, but this expects more complex flash handling we do not provide
149   - now.*/
150   -#undef CONFIG_SYS_FLASH_CFI
151   -
152   -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */
153   -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */
154   -
155   -#define CONFIG_SYS_FLASH_BASE MX1FS2_FLASH_BASE
156   -
157   -/*
158   - * This is setting for JFFS2 support in u-boot.
159   - * Right now there is no gain for user, but later on booting kernel might be
160   - * possible. Consider using XIP kernel running from flash to save RAM
161   - * footprint.
162   - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
163   - */
164   -
165   -/*
166   - * JFFS2 partitions
167   - */
168   -/* No command line, one static partition, whole device */
169   -/*
170   -#undef CONFIG_CMD_MTDPARTS
171   -#define CONFIG_JFFS2_DEV "nor0"
172   -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
173   -#define CONFIG_JFFS2_PART_OFFSET 0x00050000
174   -*/
175   -
176   -/* mtdparts command line support */
177   -/* Note: fake mtd_id used, no linux mtd map file */
178   -#define CONFIG_CMD_MTDPARTS
179   -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
180   -#define CONFIG_FLASH_CFI_MTD
181   -#define MTDIDS_DEFAULT "nor0=mx1fs2-0"
182   -
183   -#ifdef BUS32BIT_VERSION
184   -#define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:2m@5m(part0),5m@9m(part1)"
185   -#else
186   -#define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:-@320k(jffs2)"
187   -#endif
188   -
189   -/*
190   - * Environment setup. Definitions of monitor location and size with
191   - * definition of environment setup ends up in 2 possibilities.
192   - * 1. Embeded environment - in u-boot code is space for environment
193   - * 2. Environment is read from predefined sector of flash
194   - * Right now we support 2. possiblity, but expecting no env placed
195   - * on mentioned address right now. This also needs to provide whole
196   - * sector for it - for us 256Kb is really waste of memory. U-boot uses
197   - * default env. and until kernel parameters could be sent to kernel
198   - * env. has no sense to us.
199   - */
200   -
201   -#define CONFIG_SYS_MONITOR_BASE 0x10000000
202   -#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
203   -#define CONFIG_ENV_IS_IN_FLASH 1
204   -#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */
205   -#define CONFIG_ENV_SIZE 0x20000
206   -
207   -#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
208   -
209   -/* Setup CS4 and CS5 */
210   -#define CONFIG_SYS_GIUS_A_VAL 0x0003fffe
211   -
212   -/*
213   - * CSxU_VAL:
214   - * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
215   - * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
216   - *
217   - * CSxL_VAL:
218   - * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
219   - * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
220   - */
221   -
222   -#define CONFIG_SYS_CS0U_VAL 0x00008C00
223   -#define CONFIG_SYS_CS0L_VAL 0x22222601
224   -#define CONFIG_SYS_CS1U_VAL 0x00008C00
225   -#define CONFIG_SYS_CS1L_VAL 0x22222301
226   -#define CONFIG_SYS_CS4U_VAL 0x00008C00
227   -#define CONFIG_SYS_CS4L_VAL 0x22222301
228   -#define CONFIG_SYS_CS5U_VAL 0x00008C00
229   -#define CONFIG_SYS_CS5L_VAL 0x22222301
230   -
231   -/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
232   - f_ref=16,777MHz
233   -
234   - 0x002a141f: 191,9944MHz
235   - 0x040b2007: 144MHz
236   - 0x042a141f: 96MHz
237   - 0x0811140d: 64MHz
238   - 0x040e200e: 150MHz
239   - 0x00321431: 200MHz
240   -
241   - 0x08001800: 64MHz mit 16er Quarz
242   - 0x04001800: 96MHz mit 16er Quarz
243   - 0x04002400: 144MHz mit 16er Quarz
244   -
245   - 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
246   - |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
247   -
248   -#define CONFIG_SYS_MPCTL0_VAL 0x07E723AD
249   -#define CONFIG_SYS_MPCTL1_VAL 0x00000040
250   -#define CONFIG_SYS_PCDR_VAL 0x00010005
251   -#define CONFIG_SYS_GPCR_VAL 0x00000FFB
252   -
253   -#define USE_16M_OSZI /* If you have one, you want to use it
254   - The internal 32kHz oszillator jitters */
255   -#ifdef USE_16M_OSZI
256   -
257   -#define CONFIG_SYS_SPCTL0_VAL 0x04001401
258   -#define CONFIG_SYS_SPCTL1_VAL 0x0C000040
259   -#define CONFIG_SYS_CSCR_VAL 0x07030003
260   -#define CONFIG_SYS_CLK_FREQ 16780000
261   -#define CONFIG_SYSPLL_CLK_FREQ 16000000
262   -
263   -#else
264   -
265   -#define CONFIG_SYS_SPCTL0_VAL 0x07E716D1
266   -#define CONFIG_SYS_CSCR_VAL 0x06000003
267   -#define CONFIG_SYS_CLK_FREQ 16780000
268   -#define CONFIG_SYSPLL_CLK_FREQ 16780000
269   -
270   -#endif
271   -
272   -/*
273   - * Well this has to be defined, but on the other hand it is used differently
274   - * one may expect. For instance loadb command do not cares :-)
275   - * So advice is - do not relay on this...
276   - */
277   -#define CONFIG_SYS_LOAD_ADDR 0x08400000
278   -
279   -#define CONFIG_SYS_FMCR_VAL 0x00000003 /* Reset Default */
280   -
281   -/* Bit[0:3] contain PERCLK1DIV for UART 1
282   - 0x000b00b ->b<- -> 192MHz/12=16MHz
283   - 0x000b00b ->8<- -> 144MHz/09=16MHz
284   - 0x000b00b ->3<- -> 64MHz/4=16MHz */
285   -
286   -#ifdef _CONFIG_UART1
287   -#define CONFIG_IMX_SERIAL
288   -#define CONFIG_IMX_SERIAL1
289   -#elif defined _CONFIG_UART2
290   -#define CONFIG_IMX_SERIAL
291   -#define CONFIG_IMX_SERIAL2
292   -#elif defined _CONFIG_UART3 | defined _CONFIG_UART4
293   -#define CONFIG_SYS_NS16550
294   -#define CONFIG_SYS_NS16550_SERIAL
295   -#define CONFIG_SYS_NS16550_CLK 3686400
296   -#define CONFIG_SYS_NS16550_REG_SIZE 1
297   -#define CONFIG_CONS_INDEX 1
298   -#ifdef _CONFIG_UART3
299   -#define CONFIG_SYS_NS16550_COM1 0x15000000
300   -#elif defined _CONFIG_UART4
301   -#define CONFIG_SYS_NS16550_COM1 0x16000000
302   -#endif
303   -#endif
304   -
305   -#endif /* __CONFIG_H */