Merge branch 'master' of git://git.denx.de/u-boot-mmc

Tom Rini
2 parents a5a5882611 2b8a9692f9
Showing 5 changed files Side-by-side Diff
common/cmd_mmc.c
drivers/mmc/dw_mmc.c
drivers/mmc/exynos_dw_mmc.c
drivers/mmc/mmc.c
include/mmc.h
@@ -90,7 +90,8 @@
 	puts("Capacity: ");
 	print_size(mmc->capacity, "\n");
  
-	printf("Bus Width: %d-bit\n", mmc->bus_width);
+	printf("Bus Width: %d-bit%s\n", mmc->bus_width,
+			mmc->ddr_mode ? " DDR" : "");
 }
 static struct mmc *init_mmc_device(int dev, bool force_init)
 {
@@ -318,7 +318,7 @@
 	dwmci_writel(host, DWMCI_CTYPE, ctype);
  
 	regs = dwmci_readl(host, DWMCI_UHS_REG);
-	if (mmc->card_caps & MMC_MODE_DDR_52MHz)
+	if (mmc->ddr_mode)
 		regs |= DWMCI_DDR_MODE;
 	else
 		regs &= DWMCI_DDR_MODE;
@@ -101,7 +101,7 @@
 	host->get_mmc_clk = exynos_dwmci_get_clk;
 	/* Add the mmc channel to be registered with mmc core */
 	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
-		debug("dwmmc%d registration failed\n", index);
+		printf("DWMMC%d registration failed\n", index);
 		return -1;
 	}
 	return 0;
@@ -146,7 +146,7 @@
 	flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
 	err = exynos_pinmux_config(host->dev_id, flag);
 	if (err) {
-		debug("DWMMC not configure\n");
+		printf("DWMMC%d not configure\n", index);
 		return err;
 	}
  
  
  
  
@@ -162,21 +162,22 @@
 	/* Extract device id for each mmc channel */
 	host->dev_id = pinmux_decode_periph_id(blob, node);
  
+	host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
+	if (host->dev_index == host->dev_id)
+		host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
+
+
 	/* Get the bus width from the device node */
 	host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
 	if (host->buswidth <= 0) {
-		debug("DWMMC: Can't get bus-width\n");
+		printf("DWMMC%d: Can't get bus-width\n", host->dev_index);
 		return -EINVAL;
 	}
  
-	host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
-	if (host->dev_index == host->dev_id)
-		host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
-
 	/* Set the base address from the device node */
 	base = fdtdec_get_addr(blob, node, "reg");
 	if (!base) {
-		debug("DWMMC: Can't get base address\n");
+		printf("DWMMC%d: Can't get base address\n", host->dev_index);
 		return -EINVAL;
 	}
 	host->ioaddr = (void *)base;
@@ -184,7 +185,8 @@
 	/* Extract the timing info from the node */
 	err =  fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
 	if (err) {
-		debug("Can't get sdr-timings for devider\n");
+		printf("DWMMC%d: Can't get sdr-timings for devider\n",
+				host->dev_index);
 		return -EINVAL;
 	}
  
@@ -214,7 +216,7 @@
 		host = &dwmci_host[i];
 		err = exynos_dwmci_get_config(blob, node, host);
 		if (err) {
-			debug("%s: failed to decode dev %d\n", __func__, i);
+			printf("%s: failed to decode dev %d\n", __func__, i);
 			return err;
 		}
  
@@ -159,7 +159,7 @@
 {
 	struct mmc_cmd cmd;
  
-	if (mmc->card_caps & MMC_MODE_DDR_52MHz)
+	if (mmc->ddr_mode)
 		return 0;
  
 	cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
@@ -486,7 +486,7 @@
 	char cardtype;
 	int err;
  
-	mmc->card_caps = 0;
+	mmc->card_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
  
 	if (mmc_host_is_spi(mmc))
 		return 0;
@@ -519,7 +519,7 @@
  
 	/* High Speed is set, there are two types: 52MHz and 26MHz */
 	if (cardtype & EXT_CSD_CARD_TYPE_52) {
-		if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
+		if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
 			mmc->card_caps |= MMC_MODE_DDR_52MHz;
 		mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 	} else {
@@ -1001,6 +1001,9 @@
 		case 6:
 			mmc->version = MMC_VERSION_4_5;
 			break;
+		case 7:
+			mmc->version = MMC_VERSION_5_0;
+			break;
 		}
  
 		/*
@@ -1022,6 +1025,21 @@
 			mmc->erase_grp_size =
 				ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
 					MMC_MAX_BLOCK_LEN * 1024;
+			/*
+			 * if high capacity and partition setting completed
+			 * SEC_COUNT is valid even if it is smaller than 2 GiB
+			 * JEDEC Standard JESD84-B45, 6.2.4
+			 */
+			if (mmc->high_capacity &&
+			    (ext_csd[EXT_CSD_PARTITION_SETTING] &
+			     EXT_CSD_PARTITION_SETTING_COMPLETED)) {
+				capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
+					(ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
+					(ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
+					(ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
+				capacity *= MMC_MAX_BLOCK_LEN;
+				mmc->capacity_user = capacity;
+			}
 		} else {
 			/* Calculate the group size from the csd value. */
 			int erase_gsz, erase_gmul;
@@ -1103,8 +1121,10 @@
  
 		/* An array to map CSD bus widths to host cap bits */
 		static unsigned ext_to_hostcaps[] = {
-			[EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz,
-			[EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz,
+			[EXT_CSD_DDR_BUS_WIDTH_4] =
+				MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
+			[EXT_CSD_DDR_BUS_WIDTH_8] =
+				MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
 			[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
 			[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
 		};
  
  
@@ -1116,13 +1136,13 @@
  
 		for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
 			unsigned int extw = ext_csd_bits[idx];
+			unsigned int caps = ext_to_hostcaps[extw];
  
 			/*
-			 * Check to make sure the controller supports
-			 * this bus width, if it's more than 1
+			 * Check to make sure the card and controller support
+			 * these capabilities
 			 */
-			if (extw != EXT_CSD_BUS_WIDTH_1 &&
-					!(mmc->cfg->host_caps & ext_to_hostcaps[extw]))
+			if ((mmc->card_caps & caps) != caps)
 				continue;
  
 			err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  
  
  
  
@@ -1131,26 +1151,33 @@
 			if (err)
 				continue;
  
+			mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
 			mmc_set_bus_width(mmc, widths[idx]);
  
 			err = mmc_send_ext_csd(mmc, test_csd);
-			/* Only compare read only fields */
-			if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \
-				    == test_csd[EXT_CSD_PARTITIONING_SUPPORT]
-				 && ext_csd[EXT_CSD_HC_WP_GRP_SIZE] \
-				    == test_csd[EXT_CSD_HC_WP_GRP_SIZE] \
-				 && ext_csd[EXT_CSD_REV] \
-				    == test_csd[EXT_CSD_REV]
-				 && ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \
-				    == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
-				 && memcmp(&ext_csd[EXT_CSD_SEC_CNT], \
-					&test_csd[EXT_CSD_SEC_CNT], 4) == 0) {
  
-				mmc->card_caps |= ext_to_hostcaps[extw];
+			if (err)
+				continue;
+
+			/* Only compare read only fields */
+			if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
+				== test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
+			    ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
+				== test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
+			    ext_csd[EXT_CSD_REV]
+				== test_csd[EXT_CSD_REV] &&
+			    ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
+				== test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
+			    memcmp(&ext_csd[EXT_CSD_SEC_CNT],
+				   &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
 				break;
-			}
+			else
+				err = SWITCH_ERR;
 		}
  
+		if (err)
+			return err;
+
 		if (mmc->card_caps & MMC_MODE_HS) {
 			if (mmc->card_caps & MMC_MODE_HS_52MHz)
 				mmc->tran_speed = 52000000;
@@ -1161,6 +1188,12 @@
  
 	mmc_set_clock(mmc, mmc->tran_speed);
  
+	/* Fix the block length for DDR mode */
+	if (mmc->ddr_mode) {
+		mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
+		mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
+	}
+
 	/* fill in device description */
 	mmc->block_dev.lun = 0;
 	mmc->block_dev.type = 0;
@@ -1306,6 +1339,7 @@
 	if (err)
 		return err;
  
+	mmc->ddr_mode = 0;
 	mmc_set_bus_width(mmc, 1);
 	mmc_set_clock(mmc, 1);
  
@@ -1408,8 +1442,11 @@
  
 		printf("%s: %d", m->cfg->name, m->block_dev.dev);
  
-		if (entry->next != &mmc_devices)
-			printf("%c ", separator);
+		if (entry->next != &mmc_devices) {
+			printf("%c", separator);
+			if (separator != '\n')
+				puts (" ");
+		}
 	}
  
 	printf("\n");
@@ -31,6 +31,7 @@
 #define MMC_VERSION_4_3		(MMC_VERSION_MMC | 0x403)
 #define MMC_VERSION_4_41	(MMC_VERSION_MMC | 0x429)
 #define MMC_VERSION_4_5		(MMC_VERSION_MMC | 0x405)
+#define MMC_VERSION_5_0		(MMC_VERSION_MMC | 0x500)
  
 #define MMC_MODE_HS		(1 << 0)
 #define MMC_MODE_HS_52MHz	(1 << 1)
@@ -147,6 +148,7 @@
  * EXT_CSD fields
  */
 #define EXT_CSD_GP_SIZE_MULT		143	/* R/W */
+#define EXT_CSD_PARTITION_SETTING	155	/* R/W */
 #define EXT_CSD_PARTITIONS_ATTRIBUTE	156	/* R/W */
 #define EXT_CSD_PARTITIONING_SUPPORT	160	/* RO */
 #define EXT_CSD_RST_N_FUNCTION		162	/* R/W */
@@ -197,6 +199,8 @@
 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x)	(x << 2)
 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x)	(x)
  
+#define EXT_CSD_PARTITION_SETTING_COMPLETED	(1 << 0)
+
 #define R1_ILLEGAL_COMMAND		(1 << 22)
 #define R1_APP_CMD			(1 << 5)
  
@@ -314,6 +318,7 @@
 	char init_in_progress;	/* 1 if we have done mmc_start_init() */
 	char preinit;		/* start init as early as possible */
 	uint op_cond_response;	/* the response byte from the last op_cond */
+	int ddr_mode;
 };
  
 int mmc_register(struct mmc *mmc);
...	...	@@ -90,7 +90,8 @@
90	90	puts("Capacity: ");
91	91	print_size(mmc->capacity, "\n");
92	92
93		- printf("Bus Width: %d-bit\n", mmc->bus_width);
	93	+ printf("Bus Width: %d-bit%s\n", mmc->bus_width,
	94	+ mmc->ddr_mode ? " DDR" : "");
94	95	}
95	96	static struct mmc *init_mmc_device(int dev, bool force_init)
96	97	{
...	...	@@ -318,7 +318,7 @@
318	318	dwmci_writel(host, DWMCI_CTYPE, ctype);
319	319
320	320	regs = dwmci_readl(host, DWMCI_UHS_REG);
321		- if (mmc->card_caps & MMC_MODE_DDR_52MHz)
	321	+ if (mmc->ddr_mode)
322	322	regs \|= DWMCI_DDR_MODE;
323	323	else
324	324	regs &= DWMCI_DDR_MODE;
...	...	@@ -101,7 +101,7 @@
101	101	host->get_mmc_clk = exynos_dwmci_get_clk;
102	102	/* Add the mmc channel to be registered with mmc core */
103	103	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
104		- debug("dwmmc%d registration failed\n", index);
	104	+ printf("DWMMC%d registration failed\n", index);
105	105	return -1;
106	106	}
107	107	return 0;
...	...	@@ -146,7 +146,7 @@
146	146	flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
147	147	err = exynos_pinmux_config(host->dev_id, flag);
148	148	if (err) {
149		- debug("DWMMC not configure\n");
	149	+ printf("DWMMC%d not configure\n", index);
150	150	return err;
151	151	}
152	152
153	153
154	154
155	155
...	...	@@ -162,21 +162,22 @@
162	162	/* Extract device id for each mmc channel */
163	163	host->dev_id = pinmux_decode_periph_id(blob, node);
164	164
	165	+ host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
	166	+ if (host->dev_index == host->dev_id)
	167	+ host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
	168	+
	169	+
165	170	/* Get the bus width from the device node */
166	171	host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
167	172	if (host->buswidth <= 0) {
168		- debug("DWMMC: Can't get bus-width\n");
	173	+ printf("DWMMC%d: Can't get bus-width\n", host->dev_index);
169	174	return -EINVAL;
170	175	}
171	176
172		- host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
173		- if (host->dev_index == host->dev_id)
174		- host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
175		-
176	177	/* Set the base address from the device node */
177	178	base = fdtdec_get_addr(blob, node, "reg");
178	179	if (!base) {
179		- debug("DWMMC: Can't get base address\n");
	180	+ printf("DWMMC%d: Can't get base address\n", host->dev_index);
180	181	return -EINVAL;
181	182	}
182	183	host->ioaddr = (void *)base;
...	...	@@ -184,7 +185,8 @@
184	185	/* Extract the timing info from the node */
185	186	err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
186	187	if (err) {
187		- debug("Can't get sdr-timings for devider\n");
	188	+ printf("DWMMC%d: Can't get sdr-timings for devider\n",
	189	+ host->dev_index);
188	190	return -EINVAL;
189	191	}
190	192
...	...	@@ -214,7 +216,7 @@
214	216	host = &dwmci_host[i];
215	217	err = exynos_dwmci_get_config(blob, node, host);
216	218	if (err) {
217		- debug("%s: failed to decode dev %d\n", __func__, i);
	219	+ printf("%s: failed to decode dev %d\n", __func__, i);
218	220	return err;
219	221	}
220	222
...	...	@@ -159,7 +159,7 @@
159	159	{
160	160	struct mmc_cmd cmd;
161	161
162		- if (mmc->card_caps & MMC_MODE_DDR_52MHz)
	162	+ if (mmc->ddr_mode)
163	163	return 0;
164	164
165	165	cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
...	...	@@ -486,7 +486,7 @@
486	486	char cardtype;
487	487	int err;
488	488
489		- mmc->card_caps = 0;
	489	+ mmc->card_caps = MMC_MODE_4BIT \| MMC_MODE_8BIT;
490	490
491	491	if (mmc_host_is_spi(mmc))
492	492	return 0;
...	...	@@ -519,7 +519,7 @@
519	519
520	520	/* High Speed is set, there are two types: 52MHz and 26MHz */
521	521	if (cardtype & EXT_CSD_CARD_TYPE_52) {
522		- if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
	522	+ if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
523	523	mmc->card_caps \|= MMC_MODE_DDR_52MHz;
524	524	mmc->card_caps \|= MMC_MODE_HS_52MHz \| MMC_MODE_HS;
525	525	} else {
...	...	@@ -1001,6 +1001,9 @@
1001	1001	case 6:
1002	1002	mmc->version = MMC_VERSION_4_5;
1003	1003	break;
	1004	+ case 7:
	1005	+ mmc->version = MMC_VERSION_5_0;
	1006	+ break;
1004	1007	}
1005	1008
1006	1009	/*
...	...	@@ -1022,6 +1025,21 @@
1022	1025	mmc->erase_grp_size =
1023	1026	ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
1024	1027	MMC_MAX_BLOCK_LEN * 1024;
	1028	+ /*
	1029	+ * if high capacity and partition setting completed
	1030	+ * SEC_COUNT is valid even if it is smaller than 2 GiB
	1031	+ * JEDEC Standard JESD84-B45, 6.2.4
	1032	+ */
	1033	+ if (mmc->high_capacity &&
	1034	+ (ext_csd[EXT_CSD_PARTITION_SETTING] &
	1035	+ EXT_CSD_PARTITION_SETTING_COMPLETED)) {
	1036	+ capacity = (ext_csd[EXT_CSD_SEC_CNT]) \|
	1037	+ (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) \|
	1038	+ (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) \|
	1039	+ (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
	1040	+ capacity *= MMC_MAX_BLOCK_LEN;
	1041	+ mmc->capacity_user = capacity;
	1042	+ }
1025	1043	} else {
1026	1044	/* Calculate the group size from the csd value. */
1027	1045	int erase_gsz, erase_gmul;
...	...	@@ -1103,8 +1121,10 @@
1103	1121
1104	1122	/* An array to map CSD bus widths to host cap bits */
1105	1123	static unsigned ext_to_hostcaps[] = {
1106		- [EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz,
1107		- [EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz,
	1124	+ [EXT_CSD_DDR_BUS_WIDTH_4] =
	1125	+ MMC_MODE_DDR_52MHz \| MMC_MODE_4BIT,
	1126	+ [EXT_CSD_DDR_BUS_WIDTH_8] =
	1127	+ MMC_MODE_DDR_52MHz \| MMC_MODE_8BIT,
1108	1128	[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1109	1129	[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1110	1130	};
1111	1131
1112	1132
...	...	@@ -1116,13 +1136,13 @@
1116	1136
1117	1137	for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1118	1138	unsigned int extw = ext_csd_bits[idx];
	1139	+ unsigned int caps = ext_to_hostcaps[extw];
1119	1140
1120	1141	/*
1121		- * Check to make sure the controller supports
1122		- * this bus width, if it's more than 1
	1142	+ * Check to make sure the card and controller support
	1143	+ * these capabilities
1123	1144	*/
1124		- if (extw != EXT_CSD_BUS_WIDTH_1 &&
1125		- !(mmc->cfg->host_caps & ext_to_hostcaps[extw]))
	1145	+ if ((mmc->card_caps & caps) != caps)
1126	1146	continue;
1127	1147
1128	1148	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1129	1149
1130	1150
1131	1151
1132	1152
...	...	@@ -1131,26 +1151,33 @@
1131	1151	if (err)
1132	1152	continue;
1133	1153
	1154	+ mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1134	1155	mmc_set_bus_width(mmc, widths[idx]);
1135	1156
1136	1157	err = mmc_send_ext_csd(mmc, test_csd);
1137		- /* Only compare read only fields */
1138		- if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \
1139		- == test_csd[EXT_CSD_PARTITIONING_SUPPORT]
1140		- && ext_csd[EXT_CSD_HC_WP_GRP_SIZE] \
1141		- == test_csd[EXT_CSD_HC_WP_GRP_SIZE] \
1142		- && ext_csd[EXT_CSD_REV] \
1143		- == test_csd[EXT_CSD_REV]
1144		- && ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \
1145		- == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1146		- && memcmp(&ext_csd[EXT_CSD_SEC_CNT], \
1147		- &test_csd[EXT_CSD_SEC_CNT], 4) == 0) {
1148	1158
1149		- mmc->card_caps \|= ext_to_hostcaps[extw];
	1159	+ if (err)
	1160	+ continue;
	1161	+
	1162	+ /* Only compare read only fields */
	1163	+ if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
	1164	+ == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
	1165	+ ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
	1166	+ == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
	1167	+ ext_csd[EXT_CSD_REV]
	1168	+ == test_csd[EXT_CSD_REV] &&
	1169	+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
	1170	+ == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
	1171	+ memcmp(&ext_csd[EXT_CSD_SEC_CNT],
	1172	+ &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1150	1173	break;
1151		- }
	1174	+ else
	1175	+ err = SWITCH_ERR;
1152	1176	}
1153	1177
	1178	+ if (err)
	1179	+ return err;
	1180	+
1154	1181	if (mmc->card_caps & MMC_MODE_HS) {
1155	1182	if (mmc->card_caps & MMC_MODE_HS_52MHz)
1156	1183	mmc->tran_speed = 52000000;
...	...	@@ -1161,6 +1188,12 @@
1161	1188
1162	1189	mmc_set_clock(mmc, mmc->tran_speed);
1163	1190
	1191	+ /* Fix the block length for DDR mode */
	1192	+ if (mmc->ddr_mode) {
	1193	+ mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
	1194	+ mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
	1195	+ }
	1196	+
1164	1197	/* fill in device description */
1165	1198	mmc->block_dev.lun = 0;
1166	1199	mmc->block_dev.type = 0;
...	...	@@ -1306,6 +1339,7 @@
1306	1339	if (err)
1307	1340	return err;
1308	1341
	1342	+ mmc->ddr_mode = 0;
1309	1343	mmc_set_bus_width(mmc, 1);
1310	1344	mmc_set_clock(mmc, 1);
1311	1345
...	...	@@ -1408,8 +1442,11 @@
1408	1442
1409	1443	printf("%s: %d", m->cfg->name, m->block_dev.dev);
1410	1444
1411		- if (entry->next != &mmc_devices)
1412		- printf("%c ", separator);
	1445	+ if (entry->next != &mmc_devices) {
	1446	+ printf("%c", separator);
	1447	+ if (separator != '\n')
	1448	+ puts (" ");
	1449	+ }
1413	1450	}
1414	1451
1415	1452	printf("\n");
...	...	@@ -31,6 +31,7 @@
31	31	#define MMC_VERSION_4_3 (MMC_VERSION_MMC \| 0x403)
32	32	#define MMC_VERSION_4_41 (MMC_VERSION_MMC \| 0x429)
33	33	#define MMC_VERSION_4_5 (MMC_VERSION_MMC \| 0x405)
	34	+#define MMC_VERSION_5_0 (MMC_VERSION_MMC \| 0x500)
34	35
35	36	#define MMC_MODE_HS (1 << 0)
36	37	#define MMC_MODE_HS_52MHz (1 << 1)
...	...	@@ -147,6 +148,7 @@
147	148	* EXT_CSD fields
148	149	*/
149	150	#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
	151	+#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
150	152	#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
151	153	#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
152	154	#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
...	...	@@ -197,6 +199,8 @@
197	199	#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
198	200	#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
199	201
	202	+#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
	203	+
200	204	#define R1_ILLEGAL_COMMAND (1 << 22)
201	205	#define R1_APP_CMD (1 << 5)
202	206
...	...	@@ -314,6 +318,7 @@
314	318	char init_in_progress; /* 1 if we have done mmc_start_init() */
315	319	char preinit; /* start init as early as possible */
316	320	uint op_cond_response; /* the response byte from the last op_cond */
	321	+ int ddr_mode;
317	322	};
318	323
319	324	int mmc_register(struct mmc *mmc);