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Commit 69c789f385de7672f1e849c03baee40fa7d1ec44

Authored by Nishanth Menon
Committed by Dan Murphy
1 parent a20b7482a5
Exists in v2015.07-smarct4x and in 3 other branches ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc

ARM: DRA72: disable workaround for 801819 

DRA72x processor variants are single core and it does not export ACP[1].
Hence, we have no source for generating an external snoop requests which
appear to be key to the deadlock in DRA72x design.

Since we build the same image for DRA74x and DRA72x platforms, lets
runtime detect and disable the workaround (in favor of performance) on
DRA72x platforms.

[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html

Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
(cherry picked from commit 095a5ef88e08c3df0f273c20a39cb921900cfae6)
Signed-off-by: Dan Murphy <dmurphy@ti.com>

Showing 1 changed file with 11 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap5/hwinit.c
Diff comments   View file @ 69c789f
... ... @@ -425,6 +425,17 @@
425 425 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
426 426 u32 cpu_variant, u32 cpu_rev)
427 427 {
  428 +
  429 +#ifdef CONFIG_ARM_ERRATA_801819
  430 + /*
  431 + * DRA72x processors are uniprocessors and DONOT have
  432 + * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
  433 + * Extensions) Hence the erratum workaround is not applicable for
  434 + * DRA72x processors.
  435 + */
  436 + if (is_dra72x())
  437 + acr &= ~((0x3 << 23) | (0x3 << 25));
  438 +#endif
428 439 omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
429 440 }