Commit 6a235bb87bfe4a80554c07b2da3679f12167083d
Committed by
Daniel Schwierzeck
Daniel Schwierzeck
1 parent
0642f485dc
Exists in
smarc_8mq_lf_v2020.04
and in
17 other branches
MIPS: add support for Broadcom MIPS BCM63268 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Showing 3 changed files with 126 additions and 0 deletions Side-by-side Diff
arch/mips/dts/brcm,bcm63268.dtsi
| 1 | +/* | |
| 2 | + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#include <dt-bindings/gpio/gpio.h> | |
| 8 | +#include "skeleton.dtsi" | |
| 9 | + | |
| 10 | +/ { | |
| 11 | + compatible = "brcm,bcm63268"; | |
| 12 | + | |
| 13 | + cpus { | |
| 14 | + reg = <0x10000000 0x4>; | |
| 15 | + #address-cells = <1>; | |
| 16 | + #size-cells = <0>; | |
| 17 | + u-boot,dm-pre-reloc; | |
| 18 | + | |
| 19 | + cpu@0 { | |
| 20 | + compatible = "brcm,bcm63268-cpu", "mips,mips4Kc"; | |
| 21 | + device_type = "cpu"; | |
| 22 | + reg = <0>; | |
| 23 | + u-boot,dm-pre-reloc; | |
| 24 | + }; | |
| 25 | + | |
| 26 | + cpu@1 { | |
| 27 | + compatible = "brcm,bcm63268-cpu", "mips,mips4Kc"; | |
| 28 | + device_type = "cpu"; | |
| 29 | + reg = <1>; | |
| 30 | + u-boot,dm-pre-reloc; | |
| 31 | + }; | |
| 32 | + }; | |
| 33 | + | |
| 34 | + clocks { | |
| 35 | + compatible = "simple-bus"; | |
| 36 | + #address-cells = <1>; | |
| 37 | + #size-cells = <1>; | |
| 38 | + u-boot,dm-pre-reloc; | |
| 39 | + | |
| 40 | + periph_osc: periph-osc { | |
| 41 | + compatible = "fixed-clock"; | |
| 42 | + #clock-cells = <0>; | |
| 43 | + clock-frequency = <50000000>; | |
| 44 | + u-boot,dm-pre-reloc; | |
| 45 | + }; | |
| 46 | + }; | |
| 47 | + | |
| 48 | + ubus { | |
| 49 | + compatible = "simple-bus"; | |
| 50 | + #address-cells = <1>; | |
| 51 | + #size-cells = <1>; | |
| 52 | + u-boot,dm-pre-reloc; | |
| 53 | + | |
| 54 | + pll_cntl: syscon@10000008 { | |
| 55 | + compatible = "syscon"; | |
| 56 | + reg = <0x10000008 0x4>; | |
| 57 | + }; | |
| 58 | + | |
| 59 | + syscon-reboot { | |
| 60 | + compatible = "syscon-reboot"; | |
| 61 | + regmap = <&pll_cntl>; | |
| 62 | + offset = <0x0>; | |
| 63 | + mask = <0x1>; | |
| 64 | + }; | |
| 65 | + | |
| 66 | + uart0: serial@10000180 { | |
| 67 | + compatible = "brcm,bcm6345-uart"; | |
| 68 | + reg = <0x10000180 0x18>; | |
| 69 | + clocks = <&periph_osc>; | |
| 70 | + | |
| 71 | + status = "disabled"; | |
| 72 | + }; | |
| 73 | + | |
| 74 | + uart1: serial@100001a0 { | |
| 75 | + compatible = "brcm,bcm6345-uart"; | |
| 76 | + reg = <0x100001a0 0x18>; | |
| 77 | + clocks = <&periph_osc>; | |
| 78 | + | |
| 79 | + status = "disabled"; | |
| 80 | + }; | |
| 81 | + | |
| 82 | + memory-controller@10003000 { | |
| 83 | + compatible = "brcm,bcm6328-mc"; | |
| 84 | + reg = <0x10003000 0x1000>; | |
| 85 | + u-boot,dm-pre-reloc; | |
| 86 | + }; | |
| 87 | + }; | |
| 88 | +}; |
arch/mips/mach-bmips/Kconfig
| ... | ... | @@ -4,6 +4,7 @@ |
| 4 | 4 | config SYS_SOC |
| 5 | 5 | default "bcm6328" if SOC_BMIPS_BCM6328 |
| 6 | 6 | default "bcm6358" if SOC_BMIPS_BCM6358 |
| 7 | + default "bcm63268" if SOC_BMIPS_BCM63268 | |
| 7 | 8 | |
| 8 | 9 | choice |
| 9 | 10 | prompt "Broadcom MIPS SoC select" |
| ... | ... | @@ -29,6 +30,18 @@ |
| 29 | 30 | select SYSRESET_SYSCON |
| 30 | 31 | help |
| 31 | 32 | This supports BMIPS BCM6358 family including BCM6358 and BCM6359. |
| 33 | + | |
| 34 | +config SOC_BMIPS_BCM63268 | |
| 35 | + bool "BMIPS BCM63268 family" | |
| 36 | + select SUPPORTS_BIG_ENDIAN | |
| 37 | + select SUPPORTS_CPU_MIPS32_R1 | |
| 38 | + select MIPS_TUNE_4KC | |
| 39 | + select MIPS_L1_CACHE_SHIFT_4 | |
| 40 | + select SWAP_IO_SPACE | |
| 41 | + select SYSRESET_SYSCON | |
| 42 | + help | |
| 43 | + This supports BMIPS BCM63268 family including BCM63168, BCM63169, | |
| 44 | + BCM63268 and BCM63269. | |
| 32 | 45 | |
| 33 | 46 | endchoice |
| 34 | 47 |
include/configs/bmips_bcm63268.h
| 1 | +/* | |
| 2 | + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#ifndef __CONFIG_BMIPS_BCM63268_H | |
| 8 | +#define __CONFIG_BMIPS_BCM63268_H | |
| 9 | + | |
| 10 | +/* CPU */ | |
| 11 | +#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 | |
| 12 | + | |
| 13 | +/* RAM */ | |
| 14 | +#define CONFIG_NR_DRAM_BANKS 1 | |
| 15 | +#define CONFIG_SYS_SDRAM_BASE 0x80000000 | |
| 16 | + | |
| 17 | +/* U-Boot */ | |
| 18 | +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 | |
| 19 | + | |
| 20 | +#if defined(CONFIG_BMIPS_BOOT_RAM) | |
| 21 | +#define CONFIG_SKIP_LOWLEVEL_INIT | |
| 22 | +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 | |
| 23 | +#endif | |
| 24 | + | |
| 25 | +#endif /* __CONFIG_BMIPS_BCM63268_H */ |