Eric Lee / smarc-uboot

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Commit 6a8f5581f2b7b8be0b192f794a33a4bf6224f5fa

Authored by Ye Li
1 parent 02b8787d0d
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-19541 imx8mm_evk: Add imx8mm DDR4 EVK CPU board support 

Add DDR4 init codes, u-boot dtb and defconfig to support DDR4 EVK.
The DDR4 EVK removed eMMC and Flexspi, but use NAND instead. Current
codes support to boot from SD and enable NAND access in regular u-boot.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>

Showing 22 changed files with 4824 additions and 7 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ 6a8f558
... ... @@ -462,6 +462,7 @@
462 462 fsl-imx8mq-ddr3l-arm2.dtb \
463 463 fsl-imx8mq-ddr4-arm2.dtb \
464 464 fsl-imx8mq-phanbell.dtb \
  465 + fsl-imx8mm-ddr4-evk.dtb \
465 466 fsl-imx8mm-ddr4-val.dtb \
466 467 fsl-imx8mm-evk.dtb
467 468  
arch/arm/dts/fsl-imx8mm-ddr4-evk.dts
Diff comments   View file @ 6a8f558
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 + /*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +#include "fsl-imx8mm-evk.dts"
  7 +
  8 +/ {
  9 + model = "FSL i.MX8MM DDR4 EVK board";
  10 +};
  11 +
  12 +&usdhc3 {
  13 + status = "disabled";
  14 +};
  15 +
  16 +&flexspi0{
  17 + status = "disabled";
  18 +};
arch/arm/mach-imx/imx8m/Kconfig
Diff comments   View file @ 6a8f558
... ... @@ -48,6 +48,11 @@
48 48 select SUPPORT_SPL
49 49 select IMX8M_LPDDR4
50 50  
  51 +config TARGET_IMX8MM_DDR4_EVK
  52 + bool "imx8mm validation board"
  53 + select IMX8MM
  54 + select SUPPORT_SPL
  55 +
51 56 endchoice
52 57  
53 58 config SYS_SOC
board/freescale/imx8mm_evk/Kconfig
Diff comments   View file @ 6a8f558
1   -if TARGET_IMX8MM_EVK
  1 +if TARGET_IMX8MM_EVK || TARGET_IMX8MM_DDR4_EVK
2 2  
3 3 config SYS_BOARD
4 4 default "imx8mm_evk"
board/freescale/imx8mm_evk/Makefile
Diff comments   View file @ 6a8f558
... ... @@ -8,6 +8,10 @@
8 8  
9 9 ifdef CONFIG_SPL_BUILD
10 10 obj-y += spl.o
  11 +ifdef CONFIG_IMX8M_LPDDR4
11 12 obj-y += lpddr4_timing.o
  13 +else
  14 +obj-y += ddr/
  15 +endif
12 16 endif
board/freescale/imx8mm_evk/ddr/Makefile
Diff comments   View file @ 6a8f558
  1 +#
  2 +# Copyright 2018 NXP
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +ifdef CONFIG_SPL_BUILD
  8 +obj-y += helper.o
  9 +obj-y += wait_ddrphy_training_complete.o
  10 +obj-$(CONFIG_TARGET_IMX8MM_DDR4_EVK) += ddr4/
  11 +endif
board/freescale/imx8mm_evk/ddr/ddr.h
Diff comments   View file @ 6a8f558
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + * Common file for ddr code
  6 + */
  7 +
  8 +#ifndef __M845S_DDR_H_
  9 +#define __M845S_DDR_H_
  10 +
  11 +#ifdef DDR_DEBUG
  12 +#define ddr_dbg(fmt, ...) printf("DDR: debug:" fmt "\n", ##__VA_ARGS__)
  13 +#else
  14 +#define ddr_dbg(fmt, ...)
  15 +#endif
  16 +
  17 +/*******************************************************************
  18 + Desc: user data type
  19 +
  20 + *******************************************************************/
  21 +enum fw_type {
  22 + FW_1D_IMAGE,
  23 + FW_2D_IMAGE,
  24 +};
  25 +/*******************************************************************
  26 + Desc: prototype
  27 +
  28 + *******************************************************************/
  29 +void ddr_init(void);
  30 +void ddr_load_train_code(enum fw_type type);
  31 +void wait_ddrphy_training_complete(void);
  32 +void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(unsigned int pstate);
  33 +void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void);
  34 +void dwc_ddrphy_phyinit_userCustom_customPostTrain(void);
  35 +void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(void);
  36 +void dwc_ddrphy_phyinit_userCustom_A_bringupPower(void);
  37 +void dwc_ddrphy_phyinit_userCustom_overrideUserInput(void);
  38 +void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned int run_2D);
  39 +void dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void);
  40 +
  41 +/*******************************************************************
  42 + Desc: definition
  43 +
  44 + *******************************************************************/
  45 +static inline void reg32_write(unsigned long addr, u32 val)
  46 +{
  47 + writel(val, addr);
  48 +}
  49 +
  50 +static inline uint32_t reg32_read(unsigned long addr)
  51 +{
  52 + return readl(addr);
  53 +}
  54 +
  55 +static inline void reg32setbit(unsigned long addr, u32 bit)
  56 +{
  57 + setbits_le32(addr, (1 << bit));
  58 +}
  59 +#endif
board/freescale/imx8mm_evk/ddr/ddr4/Makefile
Diff comments   View file @ 6a8f558
  1 +#
  2 +# Copyright 2018 NXP
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +ifdef CONFIG_SPL_BUILD
  8 +obj-y += ddr4_phyinit_task.o
  9 +obj-y += ddr4_phyinit_2400_400_100_2r_fw09.o
  10 +obj-y += ddr4_swffc_fw09.o
  11 +obj-y += save_1d2d_trained_csr_ddr4_p012.o
  12 +obj-y += restore_1d2d_trained_csr_ddr4_p012.o
  13 +endif
board/freescale/imx8mm_evk/ddr/ddr4/anamix_common.h
Diff comments   View file @ 6a8f558
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef ANAMIX_COMMON_TMP_H
  8 +#define ANAMIX_COMMON_TMP_H
  9 +
  10 +/*ANAMIX Address Definition*/
  11 +#define ANAMIX_PLL_BASE_ADDR 0x30360000
  12 +#define ANAMIX_OSC_BASE_ADDR 0x30270000
  13 +#define ANAMIX_TSN_BASE_ADDR 0x30260000
  14 +
  15 +/* PLL TOP REG */
  16 +#define AUDIO_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x00)
  17 +#define AUDIO_PLL1_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x04)
  18 +#define AUDIO_PLL1_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x08)
  19 +#define AUDIO_PLL1_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x0c)
  20 +#define AUDIO_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x10)
  21 +#define AUDIO_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x14)
  22 +#define AUDIO_PLL2_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x18)
  23 +#define AUDIO_PLL2_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x1c)
  24 +#define AUDIO_PLL2_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x20)
  25 +#define AUDIO_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x24)
  26 +#define VIDEO_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x28)
  27 +#define VIDEO_PLL1_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x2c)
  28 +#define VIDEO_PLL1_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x30)
  29 +#define VIDEO_PLL1_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x34)
  30 +#define VIDEO_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x38)
  31 +#define VIDEO_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x3c)
  32 +#define VIDEO_PLL2_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x40)
  33 +#define VIDEO_PLL2_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x44)
  34 +#define VIDEO_PLL2_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x48)
  35 +#define VIDEO_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x4c)
  36 +#define DRAM_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x50)
  37 +#define DRAM_PLL_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x54)
  38 +#define DRAM_PLL_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x58)
  39 +#define DRAM_PLL_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x5c)
  40 +#define DRAM_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60)
  41 +#define GPU_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64)
  42 +#define GPU_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68)
  43 +#define GPU_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x6c)
  44 +#define GPU_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x70)
  45 +#define VPU_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x74)
  46 +#define VPU_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x78)
  47 +#define VPU_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x7c)
  48 +#define VPU_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x80)
  49 +#define ARM_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x84)
  50 +#define ARM_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x88)
  51 +#define ARM_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x8c)
  52 +#define ARM_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x90)
  53 +#define SYS_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x94)
  54 +#define SYS_PLL1_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x98)
  55 +#define SYS_PLL1_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x9c)
  56 +#define SYS_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x100)
  57 +#define SYS_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x104)
  58 +#define SYS_PLL2_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x108)
  59 +#define SYS_PLL2_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x10c)
  60 +#define SYS_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x110)
  61 +#define SYS_PLL3_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x114)
  62 +#define SYS_PLL3_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x118)
  63 +#define SYS_PLL3_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x11c)
  64 +#define SYS_PLL3_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x120)
  65 +#define ANAMIX_MISC_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x124)
  66 +#define ANAMIX_CLK_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x128)
  67 +
  68 +/* TMP SNSR REG */
  69 +#define TER_ADDR (ANAMIX_TSN_BASE_ADDR + 0x00)
  70 +#define TSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x04)
  71 +#define TIER_ADDR (ANAMIX_TSN_BASE_ADDR + 0x08)
  72 +#define TIDR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x0c)
  73 +#define TMHTITR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x10)
  74 +#define TMHTATR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x14)
  75 +#define TMHTACTR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x18)
  76 +#define TSCR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x1c)
  77 +#define TRITSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x20)
  78 +#define TRATSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x24)
  79 +#define TASR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x28)
  80 +#define TTMC_ADDR (ANAMIX_TSN_BASE_ADDR + 0x2c)
  81 +
  82 +/* OSC */
  83 +#define SYS_OSCNML_CTL0_ADDR (ANAMIX_OSC_BASE_ADDR + 0x00)
  84 +#define SYS_OSCNML_CTL1_ADDR (ANAMIX_OSC_BASE_ADDR + 0x04)
  85 +#define HDMI_OSCNML_CTL0_ADDR (ANAMIX_OSC_BASE_ADDR + 0x8000)
  86 +#define HDMI_OSCNML_CTL1_ADDR (ANAMIX_OSC_BASE_ADDR + 0x8004)
  87 +
  88 +#endif
board/freescale/imx8mm_evk/ddr/ddr4/ddr4_define.h
Diff comments   View file @ 6a8f558
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __DDR4_CONFIG_H__
  8 +#define __DDR4_CONFIG_H__
  9 +
  10 +#include "../ddr.h"
  11 +
  12 +#define DDR_ONE_RANK
  13 +#define RUN_ON_SILICON
  14 +#define DDR4_SW_FFC
  15 +#define ENABLE_RETENTION
  16 +
  17 +#define DRAM_VREF 0x1f
  18 +
  19 +#define SAVE_DDRPHY_TRAIN_ADDR 0x184000
  20 +
  21 +/* choose p2 state data rate, define just one of below macro */
  22 +#define PLLBYPASS_400MBPS
  23 +
  24 +/* //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// */
  25 +/* for DDR4 */
  26 +/* Note:DQ SI RON=40ohm, RTT=48ohm */
  27 +/* CA SI RON=40ohm, RTT=65ohm */
  28 +/* //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// */
  29 +/* for DDR RTT NOM/PARK */
  30 +#define DDR4_ODT_DIS 0
  31 +#define DDR4_ODT_60 1
  32 +#define DDR4_ODT_120 2
  33 +#define DDR4_ODT_40 3
  34 +#define DDR4_ODT_240 4
  35 +#define DDR4_ODT_48 5
  36 +#define DDR4_ODT_80 6
  37 +#define DDR4_ODT_34 7
  38 +
  39 +/* for DDR RON */
  40 +#define DDR4_RON_34 0
  41 +#define DDR4_RON_48 1
  42 +#define DDR4_RON_40 2
  43 +#define DDR4_RON_RES 3
  44 +
  45 +/* for DDR RTT write */
  46 +#define DDR4_RTT_WR_DIS 0
  47 +#define DDR4_RTT_WR_120 1
  48 +#define DDR4_RTT_WR_240 2
  49 +#define DDR4_RTT_WR_HZ 3
  50 +#define DDR4_RTT_WR_80 4
  51 +
  52 +/* for DDR4 PHY data RON */
  53 +#define DDR4_PHY_DATA_RON_34 0xeba
  54 +#define DDR4_PHY_DATA_RON_40 0xe38
  55 +#define DDR4_PHY_DATA_RON_48 ((0x1a << 6) | 0x1a)
  56 +#define DDR4_PHY_DATA_RON_60 ((0x18 << 6) | 0x18)
  57 +#define DDR4_PHY_DATA_RON_80 ((0x0a << 6) | 0x0a)
  58 +#define DDR4_PHY_DATA_RON_120 ((0x08 << 6) | 0x08)
  59 +#define DDR4_PHY_DATA_RON_240 ((0x02<<6)|0x02)
  60 +
  61 +/* for DDR4 PHY data RTT */
  62 +#define DDR4_PHY_DATA_RTT_34 0x3a
  63 +#define DDR4_PHY_DATA_RTT_40 0x38
  64 +#define DDR4_PHY_DATA_RTT_48 0x1a
  65 +#define DDR4_PHY_DATA_RTT_60 0x18
  66 +#define DDR4_PHY_DATA_RTT_80 0x0a
  67 +#define DDR4_PHY_DATA_RTT_120 0x08
  68 +#define DDR4_PHY_DATA_RTT_240 0x02
  69 +
  70 +/* for DDR4 PHY address RON */
  71 +#define DDR4_PHY_ADDR_RON_30 ((0x07 << 5) | 0x07)
  72 +#define DDR4_PHY_ADDR_RON_40 0x63
  73 +#define DDR4_PHY_ADDR_RON_60 ((0x01 << 5) | 0x01)
  74 +#define DDR4_PHY_ADDR_RON_120 ((0x00 << 5) | 0x00)
  75 +
  76 +#define DDR4_PHY_ADDR_RON DDR4_PHY_ADDR_RON_40
  77 +
  78 +/* read DDR4 */
  79 +#ifdef DDR_ONE_RANK
  80 +#define DDR4_RON DDR4_RON_34
  81 +#define DDR4_PHY_DATA_RTT DDR4_PHY_DATA_RTT_48
  82 +#define DDR4_PHYREF_VALUE 91
  83 +#else
  84 +#define DDR4_RON DDR4_RON_40
  85 +#define DDR4_PHY_DATA_RTT DDR4_PHY_DATA_RTT_48
  86 +#define DDR4_PHYREF_VALUE 93
  87 +#endif
  88 +
  89 +/* write DDR4 */
  90 +#ifdef DDR_ONE_RANK
  91 +/* one lank */
  92 +#define DDR4_PHY_DATA_RON DDR4_PHY_DATA_RON_34
  93 +#define DDR4_RTT_NOM DDR4_ODT_60
  94 +#define DDR4_RTT_WR DDR4_RTT_WR_DIS
  95 +#define DDR4_RTT_PARK DDR4_ODT_DIS
  96 +#define DDR4_MR6_VALUE 0x0d
  97 +#else
  98 +/* two lank */
  99 +#define DDR4_PHY_DATA_RON DDR4_PHY_DATA_RON_40
  100 +#define DDR4_RTT_NOM DDR4_ODT_60
  101 +#define DDR4_RTT_WR DDR4_RTT_WR_DIS
  102 +#define DDR4_RTT_PARK DDR4_ODT_DIS
  103 +#define DDR4_MR6_VALUE 0x10
  104 +#endif
  105 +
  106 +/* voltage:delay */
  107 +#define DDR4_2D_WEIGHT (31 << 8 | 127)
  108 +
  109 +#define ANAMIX_PLL_BASE_ADDR 0x30360000
  110 +#define HW_DRAM_PLL_CFG0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60)
  111 +#define HW_DRAM_PLL_CFG1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64)
  112 +#define HW_DRAM_PLL_CFG2_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68)
  113 +#define GPC_PU_PWRHSK 0x303A01FC
  114 +#define GPC_TOP_CONFIG_OFFSET 0x0000
  115 +#define AIPS1_ARB_BASE_ADDR 0x30000000
  116 +#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
  117 +#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x200000)
  118 +#define CCM_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x180000)
  119 +#define CCM_SRC_CTRL_OFFSET (CCM_IPS_BASE_ADDR + 0x800)
  120 +#define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET + 0x10 * n)
  121 +
  122 +
  123 +#define dwc_ddrphy_apb_wr(addr, data) reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
  124 +#define dwc_ddrphy_apb_rd(addr) (reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr)))
  125 +#define reg32clrbit(addr, bitpos) reg32_write((addr), (reg32_read((addr)) & (0xFFFFFFFF ^ (1 << (bitpos)))))
  126 +#define DDR_CSD1_BASE_ADDR 0x40000000
  127 +#define DDR_CSD2_BASE_ADDR 0x80000000
  128 +
  129 +void restore_1d2d_trained_csr_ddr4_p012(unsigned int addr);
  130 +void save_1d2d_trained_csr_ddr4_p012(unsigned int addr);
  131 +void ddr4_mr_write(unsigned int mr, unsigned int data, unsigned int read, unsigned int rank);
  132 +void ddr4_phyinit_train_sw_ffc(unsigned int Train2D);
  133 +
  134 +#endif
board/freescale/imx8mm_evk/ddr/ddr4/ddr4_phyinit_2400_400_100_2r_fw09.c
Diff comments   View file @ 6a8f558
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <errno.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch/ddr.h>
  11 +#include <asm/arch/clock.h>
  12 +#include "ddr4_define.h"
  13 +
  14 +extern unsigned int after_retention;
  15 +extern unsigned int mr_value[3][7];
  16 +
  17 +void ddr4_phyinit_train_sw_ffc(unsigned int Train2D)
  18 +{
  19 + /* [dwc_ddrphy_phyinit_main] Start of dwc_ddrphy_phyinit_main() */
  20 + /* [dwc_ddrphy_phyinit_sequence] Start of dwc_ddrphy_phyinit_sequence() */
  21 + /* [dwc_ddrphy_phyinit_initStruct] Start of dwc_ddrphy_phyinit_initStruct() */
  22 + /* [dwc_ddrphy_phyinit_initStruct] End of dwc_ddrphy_phyinit_initStruct() */
  23 + /* [dwc_ddrphy_phyinit_setDefault] Start of dwc_ddrphy_phyinit_setDefault() */
  24 + /* [dwc_ddrphy_phyinit_setDefault] End of dwc_ddrphy_phyinit_setDefault() */
  25 +
  26 +
  27 + /* ############################################################## */
  28 + /* */
  29 + /* dwc_ddrphy_phyinit_userCustom_overrideUserInput is a user-editable function. */
  30 + /* */
  31 + /* See PhyInit App Note for detailed description and function usage */
  32 + /* */
  33 + /* ############################################################## */
  34 +
  35 + dwc_ddrphy_phyinit_userCustom_overrideUserInput ();
  36 + /* */
  37 + /* [dwc_ddrphy_phyinit_userCustom_overrideUserInput] End of dwc_ddrphy_phyinit_userCustom_overrideUserInput() */
  38 +
  39 +
  40 + /* ############################################################## */
  41 + /* */
  42 + /* Step (A) : Bring up VDD, VDDQ, and VAA */
  43 + /* */
  44 + /* See PhyInit App Note for detailed description and function usage */
  45 + /* */
  46 + /* ############################################################## */
  47 +
  48 +
  49 + dwc_ddrphy_phyinit_userCustom_A_bringupPower ();
  50 +
  51 + /* [dwc_ddrphy_phyinit_userCustom_A_bringupPower] End of dwc_ddrphy_phyinit_userCustom_A_bringupPower() */
  52 + /* [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] Start of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy() */
  53 + /* */
  54 + /* */
  55 + /* ############################################################## */
  56 + /* */
  57 + /* Step (B) Start Clocks and Reset the PHY */
  58 + /* */
  59 + /* See PhyInit App Note for detailed description and function usage */
  60 + /* */
  61 + /* ############################################################## */
  62 + /* */
  63 + /* */
  64 + dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy ();
  65 +
  66 + /* [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] End of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy() */
  67 + /* */
  68 +
  69 + /* ############################################################## */
  70 + /* */
  71 + /* Step (C) Initialize PHY Configuration */
  72 + /* */
  73 + /* Load the required PHY configuration registers for the appropriate mode and memory configuration */
  74 + /* */
  75 + /* ############################################################## */
  76 + /* */
  77 +
  78 + /* [phyinit_C_initPhyConfig] Start of dwc_ddrphy_phyinit_C_initPhyConfig() */
  79 + /* */
  80 + /* ############################################################## */
  81 + /* TxPreDrvMode[2] = 0 */
  82 + /* ############################################################## */
  83 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxSlewRate::TxPreDrvMode to 0x2 */
  84 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxSlewRate::TxPreP to 0xd */
  85 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxSlewRate::TxPreN to 0xf */
  86 + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */
  87 + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
  88 +
  89 + dwc_ddrphy_apb_wr(0x1005f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */
  90 + dwc_ddrphy_apb_wr(0x1015f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */
  91 + dwc_ddrphy_apb_wr(0x1105f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */
  92 + dwc_ddrphy_apb_wr(0x1115f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */
  93 + dwc_ddrphy_apb_wr(0x1205f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */
  94 + dwc_ddrphy_apb_wr(0x1215f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */
  95 + dwc_ddrphy_apb_wr(0x1305f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */
  96 + dwc_ddrphy_apb_wr(0x1315f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */
  97 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxSlewRate::TxPreDrvMode to 0x2 */
  98 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxSlewRate::TxPreP to 0xd */
  99 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxSlewRate::TxPreN to 0xf */
  100 + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */
  101 + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
  102 +
  103 + dwc_ddrphy_apb_wr(0x11005f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p1 */
  104 + dwc_ddrphy_apb_wr(0x11015f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p1 */
  105 + dwc_ddrphy_apb_wr(0x11105f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p1 */
  106 + dwc_ddrphy_apb_wr(0x11115f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p1 */
  107 + dwc_ddrphy_apb_wr(0x11205f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p1 */
  108 + dwc_ddrphy_apb_wr(0x11215f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p1 */
  109 + dwc_ddrphy_apb_wr(0x11305f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p1 */
  110 + dwc_ddrphy_apb_wr(0x11315f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p1 */
  111 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxSlewRate::TxPreDrvMode to 0x2 */
  112 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxSlewRate::TxPreP to 0xd */
  113 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxSlewRate::TxPreN to 0xf */
  114 + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */
  115 + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
  116 +
  117 + dwc_ddrphy_apb_wr(0x21005f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p2 */
  118 + dwc_ddrphy_apb_wr(0x21015f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p2 */
  119 + dwc_ddrphy_apb_wr(0x21105f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p2 */
  120 + dwc_ddrphy_apb_wr(0x21115f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p2 */
  121 + dwc_ddrphy_apb_wr(0x21205f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p2 */
  122 + dwc_ddrphy_apb_wr(0x21215f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p2 */
  123 + dwc_ddrphy_apb_wr(0x21305f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p2 */
  124 + dwc_ddrphy_apb_wr(0x21315f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p2 */
  125 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=0 */
  126 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=0 */
  127 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=0 */
  128 + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
  129 + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
  130 +
  131 + dwc_ddrphy_apb_wr(0x55, 0x355); /* DWC_DDRPHYA_ANIB0_ATxSlewRate */
  132 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=1 */
  133 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=1 */
  134 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=1 */
  135 + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
  136 + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
  137 +
  138 + dwc_ddrphy_apb_wr(0x1055, 0x355); /* DWC_DDRPHYA_ANIB1_ATxSlewRate */
  139 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=2 */
  140 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=2 */
  141 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=2 */
  142 + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
  143 + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
  144 +
  145 + dwc_ddrphy_apb_wr(0x2055, 0x355); /* DWC_DDRPHYA_ANIB2_ATxSlewRate */
  146 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=3 */
  147 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=3 */
  148 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=3 */
  149 + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
  150 + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
  151 +
  152 + dwc_ddrphy_apb_wr(0x3055, 0x355); /* DWC_DDRPHYA_ANIB3_ATxSlewRate */
  153 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x0, ANIB=4 */
  154 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=4 */
  155 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=4 */
  156 + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
  157 + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
  158 +
  159 + dwc_ddrphy_apb_wr(0x4055, 0x55); /* DWC_DDRPHYA_ANIB4_ATxSlewRate */
  160 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x0, ANIB=5 */
  161 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=5 */
  162 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=5 */
  163 + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
  164 + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
  165 +
  166 + dwc_ddrphy_apb_wr(0x5055, 0x55); /* DWC_DDRPHYA_ANIB5_ATxSlewRate */
  167 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=6 */
  168 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=6 */
  169 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=6 */
  170 + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
  171 + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
  172 +
  173 + dwc_ddrphy_apb_wr(0x6055, 0x355); /* DWC_DDRPHYA_ANIB6_ATxSlewRate */
  174 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=7 */
  175 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=7 */
  176 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=7 */
  177 + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
  178 + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
  179 +
  180 + dwc_ddrphy_apb_wr(0x7055, 0x355); /* DWC_DDRPHYA_ANIB7_ATxSlewRate */
  181 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=8 */
  182 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=8 */
  183 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=8 */
  184 + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
  185 + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
  186 +
  187 + dwc_ddrphy_apb_wr(0x8055, 0x355); /* DWC_DDRPHYA_ANIB8_ATxSlewRate */
  188 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=9 */
  189 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=9 */
  190 + /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=9 */
  191 + /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
  192 + /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
  193 +
  194 + dwc_ddrphy_apb_wr(0x9055, 0x355); /* DWC_DDRPHYA_ANIB9_ATxSlewRate */
  195 + dwc_ddrphy_apb_wr(0x200c5, 0xa); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */
  196 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming PllCtrl2 to a based on DfiClk frequency = 600. */
  197 + dwc_ddrphy_apb_wr(0x1200c5, 0x7); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p1 */
  198 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming PllCtrl2 to 7 based on DfiClk frequency = 100. */
  199 + dwc_ddrphy_apb_wr(0x2200c5, 0x7); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p2 */
  200 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming PllCtrl2 to 7 based on DfiClk frequency = 25. */
  201 + /* */
  202 + /* ############################################################## */
  203 + /* */
  204 + /* Program ARdPtrInitVal based on Frequency and PLL Bypass inputs */
  205 + /* The values programmed here assume ideal properties of DfiClk */
  206 + /* and Pclk including: */
  207 + /* - DfiClk skew */
  208 + /* - DfiClk jitter */
  209 + /* - DfiClk PVT variations */
  210 + /* - Pclk skew */
  211 + /* - Pclk jitter */
  212 + /* */
  213 + /* PLL Bypassed mode: */
  214 + /* For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 2-6 */
  215 + /* For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-6 */
  216 + /* */
  217 + /* PLL Enabled mode: */
  218 + /* For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-6 */
  219 + /* For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 0-6 */
  220 + /* */
  221 + /* ############################################################## */
  222 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming ARdPtrInitVal to 0x2 */
  223 + dwc_ddrphy_apb_wr(0x2002e, 0x2); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */
  224 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming ARdPtrInitVal to 0x2 */
  225 + dwc_ddrphy_apb_wr(0x12002e, 0x2); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p1 */
  226 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming ARdPtrInitVal to 0x2 */
  227 + dwc_ddrphy_apb_wr(0x22002e, 0x2); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p2 */
  228 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */
  229 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */
  230 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */
  231 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */
  232 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */
  233 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */
  234 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl to 0x8 */
  235 + dwc_ddrphy_apb_wr(0x20024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */
  236 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DbyteDllModeCntrl to 0x2 */
  237 + dwc_ddrphy_apb_wr(0x2003a, 0x2); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
  238 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */
  239 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */
  240 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */
  241 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */
  242 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */
  243 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */
  244 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl to 0x8 */
  245 + dwc_ddrphy_apb_wr(0x120024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p1 */
  246 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DbyteDllModeCntrl to 0x2 */
  247 + dwc_ddrphy_apb_wr(0x2003a, 0x2); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
  248 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */
  249 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */
  250 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */
  251 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */
  252 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */
  253 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */
  254 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl to 0x8 */
  255 + dwc_ddrphy_apb_wr(0x220024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p2 */
  256 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DbyteDllModeCntrl to 0x2 */
  257 + dwc_ddrphy_apb_wr(0x2003a, 0x2); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
  258 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming ProcOdtTimeCtl to 0x6 */
  259 + dwc_ddrphy_apb_wr(0x20056, 0x6); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */
  260 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming ProcOdtTimeCtl to 0xa */
  261 + dwc_ddrphy_apb_wr(0x120056, 0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p1 */
  262 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming ProcOdtTimeCtl to 0xa */
  263 + dwc_ddrphy_apb_wr(0x220056, 0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p2 */
  264 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxOdtDrvStren::ODTStrenP to 0x1a */
  265 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxOdtDrvStren::ODTStrenN to 0x0 */
  266 + dwc_ddrphy_apb_wr(0x1004d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */
  267 + dwc_ddrphy_apb_wr(0x1014d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */
  268 + dwc_ddrphy_apb_wr(0x1104d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */
  269 + dwc_ddrphy_apb_wr(0x1114d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */
  270 + dwc_ddrphy_apb_wr(0x1204d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */
  271 + dwc_ddrphy_apb_wr(0x1214d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */
  272 + dwc_ddrphy_apb_wr(0x1304d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */
  273 + dwc_ddrphy_apb_wr(0x1314d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */
  274 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxOdtDrvStren::ODTStrenP to 0x1a */
  275 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxOdtDrvStren::ODTStrenN to 0x0 */
  276 + dwc_ddrphy_apb_wr(0x11004d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p1 */
  277 + dwc_ddrphy_apb_wr(0x11014d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p1 */
  278 + dwc_ddrphy_apb_wr(0x11104d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p1 */
  279 + dwc_ddrphy_apb_wr(0x11114d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p1 */
  280 + dwc_ddrphy_apb_wr(0x11204d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p1 */
  281 + dwc_ddrphy_apb_wr(0x11214d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p1 */
  282 + dwc_ddrphy_apb_wr(0x11304d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p1 */
  283 + dwc_ddrphy_apb_wr(0x11314d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p1 */
  284 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxOdtDrvStren::ODTStrenP to 0x1a */
  285 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxOdtDrvStren::ODTStrenN to 0x0 */
  286 + dwc_ddrphy_apb_wr(0x21004d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p2 */
  287 + dwc_ddrphy_apb_wr(0x21014d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p2 */
  288 + dwc_ddrphy_apb_wr(0x21104d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p2 */
  289 + dwc_ddrphy_apb_wr(0x21114d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p2 */
  290 + dwc_ddrphy_apb_wr(0x21204d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p2 */
  291 + dwc_ddrphy_apb_wr(0x21214d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p2 */
  292 + dwc_ddrphy_apb_wr(0x21304d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p2 */
  293 + dwc_ddrphy_apb_wr(0x21314d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p2 */
  294 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */
  295 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */
  296 + dwc_ddrphy_apb_wr(0x10049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */
  297 + dwc_ddrphy_apb_wr(0x10149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */
  298 + dwc_ddrphy_apb_wr(0x11049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */
  299 + dwc_ddrphy_apb_wr(0x11149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */
  300 + dwc_ddrphy_apb_wr(0x12049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */
  301 + dwc_ddrphy_apb_wr(0x12149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */
  302 + dwc_ddrphy_apb_wr(0x13049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */
  303 + dwc_ddrphy_apb_wr(0x13149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */
  304 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */
  305 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */
  306 + dwc_ddrphy_apb_wr(0x110049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p1 */
  307 + dwc_ddrphy_apb_wr(0x110149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p1 */
  308 + dwc_ddrphy_apb_wr(0x111049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p1 */
  309 + dwc_ddrphy_apb_wr(0x111149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p1 */
  310 + dwc_ddrphy_apb_wr(0x112049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p1 */
  311 + dwc_ddrphy_apb_wr(0x112149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p1 */
  312 + dwc_ddrphy_apb_wr(0x113049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p1 */
  313 + dwc_ddrphy_apb_wr(0x113149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p1 */
  314 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */
  315 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */
  316 + dwc_ddrphy_apb_wr(0x210049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p2 */
  317 + dwc_ddrphy_apb_wr(0x210149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p2 */
  318 + dwc_ddrphy_apb_wr(0x211049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p2 */
  319 + dwc_ddrphy_apb_wr(0x211149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p2 */
  320 + dwc_ddrphy_apb_wr(0x212049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p2 */
  321 + dwc_ddrphy_apb_wr(0x212149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p2 */
  322 + dwc_ddrphy_apb_wr(0x213049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p2 */
  323 + dwc_ddrphy_apb_wr(0x213149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p2 */
  324 + /* [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenP to 0x3 */
  325 + /* [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenN to 0x3 */
  326 + dwc_ddrphy_apb_wr(0x43, 0x63); /* DWC_DDRPHYA_ANIB0_ATxImpedance */
  327 + dwc_ddrphy_apb_wr(0x1043, 0x63); /* DWC_DDRPHYA_ANIB1_ATxImpedance */
  328 + dwc_ddrphy_apb_wr(0x2043, 0x63); /* DWC_DDRPHYA_ANIB2_ATxImpedance */
  329 + dwc_ddrphy_apb_wr(0x3043, 0x63); /* DWC_DDRPHYA_ANIB3_ATxImpedance */
  330 + dwc_ddrphy_apb_wr(0x4043, 0x63); /* DWC_DDRPHYA_ANIB4_ATxImpedance */
  331 + dwc_ddrphy_apb_wr(0x5043, 0x63); /* DWC_DDRPHYA_ANIB5_ATxImpedance */
  332 + dwc_ddrphy_apb_wr(0x6043, 0x63); /* DWC_DDRPHYA_ANIB6_ATxImpedance */
  333 + dwc_ddrphy_apb_wr(0x7043, 0x63); /* DWC_DDRPHYA_ANIB7_ATxImpedance */
  334 + dwc_ddrphy_apb_wr(0x8043, 0x63); /* DWC_DDRPHYA_ANIB8_ATxImpedance */
  335 + dwc_ddrphy_apb_wr(0x9043, 0x63); /* DWC_DDRPHYA_ANIB9_ATxImpedance */
  336 + /* [phyinit_C_initPhyConfig] Programming DfiMode to 0x5 */
  337 + dwc_ddrphy_apb_wr(0x20018, 0x5); /* DWC_DDRPHYA_MASTER0_DfiMode */
  338 + /* [phyinit_C_initPhyConfig] Programming DfiCAMode to 0x2 */
  339 + dwc_ddrphy_apb_wr(0x20075, 0x2); /* DWC_DDRPHYA_MASTER0_DfiCAMode */
  340 + /* [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPd50 to 0x0 */
  341 + /* [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPu50 to 0x0 */
  342 + dwc_ddrphy_apb_wr(0x20050, 0x0); /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */
  343 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x258 */
  344 + dwc_ddrphy_apb_wr(0x20008, 0x258); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */
  345 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x64 */
  346 + dwc_ddrphy_apb_wr(0x120008, 0x64); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p1 */
  347 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x19 */
  348 + dwc_ddrphy_apb_wr(0x220008, 0x19); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p2 */
  349 + /* [phyinit_C_initPhyConfig] Programming CalRate::CalInterval to 0x9 */
  350 + /* [phyinit_C_initPhyConfig] Programming CalRate::CalOnce to 0x0 */
  351 + dwc_ddrphy_apb_wr(0x20088, 0x9); /* DWC_DDRPHYA_MASTER0_CalRate */
  352 + /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */
  353 + /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x4d */
  354 + /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0x268 */
  355 + dwc_ddrphy_apb_wr(0x200b2, 0x268); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */
  356 + /* [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x3 */
  357 + /* [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl to 0x5b1 */
  358 + dwc_ddrphy_apb_wr(0x10043, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */
  359 + dwc_ddrphy_apb_wr(0x10143, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */
  360 + dwc_ddrphy_apb_wr(0x11043, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */
  361 + dwc_ddrphy_apb_wr(0x11143, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */
  362 + dwc_ddrphy_apb_wr(0x12043, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */
  363 + dwc_ddrphy_apb_wr(0x12143, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */
  364 + dwc_ddrphy_apb_wr(0x13043, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */
  365 + dwc_ddrphy_apb_wr(0x13143, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */
  366 + /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */
  367 + /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal::GlobalVrefInDAC to 0x4d */
  368 + /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal to 0x268 */
  369 + dwc_ddrphy_apb_wr(0x1200b2, 0x268); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p1 */
  370 + /* [phyinit_C_initPhyConfig] Pstate=1, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x3 */
  371 + /* [phyinit_C_initPhyConfig] Pstate=1, Programming DqDqsRcvCntrl to 0x5b1 */
  372 + dwc_ddrphy_apb_wr(0x110043, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p1 */
  373 + dwc_ddrphy_apb_wr(0x110143, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p1 */
  374 + dwc_ddrphy_apb_wr(0x111043, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p1 */
  375 + dwc_ddrphy_apb_wr(0x111143, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p1 */
  376 + dwc_ddrphy_apb_wr(0x112043, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p1 */
  377 + dwc_ddrphy_apb_wr(0x112143, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p1 */
  378 + dwc_ddrphy_apb_wr(0x113043, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p1 */
  379 + dwc_ddrphy_apb_wr(0x113143, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p1 */
  380 + /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */
  381 + /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal::GlobalVrefInDAC to 0x4d */
  382 + /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal to 0x268 */
  383 + dwc_ddrphy_apb_wr(0x2200b2, 0x268); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p2 */
  384 + /* [phyinit_C_initPhyConfig] Pstate=2, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x3 */
  385 + /* [phyinit_C_initPhyConfig] Pstate=2, Programming DqDqsRcvCntrl to 0x5b1 */
  386 + dwc_ddrphy_apb_wr(0x210043, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p2 */
  387 + dwc_ddrphy_apb_wr(0x210143, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p2 */
  388 + dwc_ddrphy_apb_wr(0x211043, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p2 */
  389 + dwc_ddrphy_apb_wr(0x211143, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p2 */
  390 + dwc_ddrphy_apb_wr(0x212043, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p2 */
  391 + dwc_ddrphy_apb_wr(0x212143, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p2 */
  392 + dwc_ddrphy_apb_wr(0x213043, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p2 */
  393 + dwc_ddrphy_apb_wr(0x213143, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p2 */
  394 + /* [phyinit_C_initPhyConfig] Programming MemAlertControl::MALERTVrefLevel to 0x29 */
  395 + /* [phyinit_C_initPhyConfig] Programming MemAlertControl::MALERTPuStren to 0x5 */
  396 + /* [phyinit_C_initPhyConfig] Programming MemAlertControl to 0x7529 */
  397 + /* [phyinit_C_initPhyConfig] Programming MemAlertControl2::MALERTSyncBypass to 0x0 */
  398 + dwc_ddrphy_apb_wr(0x2005b, 0x7529); /* DWC_DDRPHYA_MASTER0_MemAlertControl */
  399 + dwc_ddrphy_apb_wr(0x2005c, 0x0); /* DWC_DDRPHYA_MASTER0_MemAlertControl2 */
  400 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DfiFreqRatio_p0 to 0x1 */
  401 + dwc_ddrphy_apb_wr(0x200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */
  402 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DfiFreqRatio_p1 to 0x1 */
  403 + dwc_ddrphy_apb_wr(0x1200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p1 */
  404 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DfiFreqRatio_p2 to 0x1 */
  405 + dwc_ddrphy_apb_wr(0x2200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p2 */
  406 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TristateModeCA::DisDynAdrTri_p0 to 0x1 */
  407 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TristateModeCA::DDR2TMode_p0 to 0x0 */
  408 + dwc_ddrphy_apb_wr(0x20019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */
  409 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TristateModeCA::DisDynAdrTri_p1 to 0x1 */
  410 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TristateModeCA::DDR2TMode_p1 to 0x0 */
  411 + dwc_ddrphy_apb_wr(0x120019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p1 */
  412 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TristateModeCA::DisDynAdrTri_p2 to 0x1 */
  413 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TristateModeCA::DDR2TMode_p2 to 0x0 */
  414 + dwc_ddrphy_apb_wr(0x220019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p2 */
  415 + /* [phyinit_C_initPhyConfig] Programming DfiFreqXlat* */
  416 + dwc_ddrphy_apb_wr(0x200f0, 0x5665); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */
  417 + dwc_ddrphy_apb_wr(0x200f1, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */
  418 + dwc_ddrphy_apb_wr(0x200f2, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */
  419 + dwc_ddrphy_apb_wr(0x200f3, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */
  420 + dwc_ddrphy_apb_wr(0x200f4, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */
  421 + dwc_ddrphy_apb_wr(0x200f5, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */
  422 + dwc_ddrphy_apb_wr(0x200f6, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */
  423 + dwc_ddrphy_apb_wr(0x200f7, 0xf000); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */
  424 + /* [phyinit_C_initPhyConfig] Programming MasterX4Config::X4TG to 0x0 */
  425 + dwc_ddrphy_apb_wr(0x20025, 0x0); /* DWC_DDRPHYA_MASTER0_MasterX4Config */
  426 + /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DMIPinPresent::RdDbiEnabled to 0x0 */
  427 + dwc_ddrphy_apb_wr(0x2002d, 0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */
  428 + /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DMIPinPresent::RdDbiEnabled to 0x0 */
  429 + dwc_ddrphy_apb_wr(0x12002d, 0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p1 */
  430 + /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DMIPinPresent::RdDbiEnabled to 0x0 */
  431 + dwc_ddrphy_apb_wr(0x22002d, 0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p2 */
  432 + /* [phyinit_C_initPhyConfig] End of dwc_ddrphy_phyinit_C_initPhyConfig() */
  433 + /* */
  434 + /* */
  435 + /* ############################################################## */
  436 + /* */
  437 + /* dwc_ddrphy_phyihunit_userCustom_customPreTrain is a user-editable function. */
  438 + /* */
  439 + /* See PhyInit App Note for detailed description and function usage */
  440 + /* */
  441 + /* ############################################################## */
  442 + ddr_dbg("add 845S pll setting in phyinit\n");
  443 + /* [phyinit_userCustom_customPreTrain] Start of dwc_ddrphy_phyinit_userCustom_customPreTrain() */
  444 + dwc_ddrphy_apb_wr(0x200c7, 0x21); /* DWC_DDRPHYA_MASTER0_PllCtrl1_p0 */
  445 + dwc_ddrphy_apb_wr(0x200ca, 0x24); /* DWC_DDRPHYA_MASTER0_PllTestMode_p0 */
  446 + /* [phyinit_userCustom_customPreTrain] End of dwc_ddrphy_phyinit_userCustom_customPreTrain() */
  447 + /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=0) */
  448 + /* */
  449 + /* */
  450 + /* ############################################################## */
  451 + /* */
  452 + /* (D) Load the 1D IMEM image */
  453 + /* */
  454 + /* This function loads the training firmware IMEM image into the SRAM. */
  455 + /* See PhyInit App Note for detailed description and function usage */
  456 + /* */
  457 + /* ############################################################## */
  458 + /* */
  459 + /* */
  460 + /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Programming MemResetL to 0x2 */
  461 + if (!after_retention) {
  462 + dwc_ddrphy_apb_wr(0x20060, 0x2);
  463 +
  464 + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4/ddr4_pmu_train_imem.incv */
  465 +
  466 + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
  467 + /* This allows the memory controller unrestricted access to the configuration CSRs. */
  468 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  469 + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x50000 size 0x4000 */
  470 + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x4000 */
  471 + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
  472 + /* This allows the firmware unrestricted access to the configuration CSRs. */
  473 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  474 + /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] End of dwc_ddrphy_phyinit_D_loadIMEM() */
  475 + /* */
  476 + /* */
  477 + /* ############################################################## */
  478 + /* */
  479 + /* Step (E) Set the PHY input clocks to the desired frequency for pstate 0 */
  480 + /* */
  481 + /* See PhyInit App Note for detailed description and function usage */
  482 + /* */
  483 + /* ############################################################## */
  484 + /* */
  485 + /* dwc_ddrphy_phyinit_userCustom_E_setDfiClk (0); */
  486 +
  487 + /* */
  488 + /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */
  489 + /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=0) */
  490 +
  491 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  492 + /* for test on silicon, load 1D dmem/imem here */
  493 +#ifdef CONFIG_SPL_VSI_FW_LOADING
  494 + load_train_1d_code();
  495 +#else
  496 + ddr_load_train_code(FW_1D_IMAGE);
  497 +#endif
  498 + ddr_dbg("start 1d train\n");
  499 +
  500 + /* */
  501 + /* ############################################################## */
  502 + /* */
  503 + /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */
  504 + /* */
  505 + /* See PhyInit App Note for detailed description and function usage */
  506 + /* */
  507 + /* ############################################################## */
  508 + /* */
  509 + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4/ddr4_pmu_train_dmem.incv */
  510 +
  511 + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
  512 + /* This allows the memory controller unrestricted access to the configuration CSRs. */
  513 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  514 + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */
  515 +#ifdef RUN_ON_SILICON
  516 + dwc_ddrphy_apb_wr(0x54000, 0x0);
  517 +#else
  518 + dwc_ddrphy_apb_wr(0x54000, 0x600);
  519 +#endif
  520 + dwc_ddrphy_apb_wr(0x54001, 0x0);
  521 + dwc_ddrphy_apb_wr(0x54002, 0x0);
  522 + dwc_ddrphy_apb_wr(0x54003, 0x960);
  523 + dwc_ddrphy_apb_wr(0x54004, 0x2);
  524 + dwc_ddrphy_apb_wr(0x54005, 0x0);
  525 + dwc_ddrphy_apb_wr(0x54006, 0x25e);
  526 + dwc_ddrphy_apb_wr(0x54007, 0x2000);
  527 +#ifdef DDR_ONE_RANK
  528 + dwc_ddrphy_apb_wr(0x54008, 0x101);
  529 + dwc_ddrphy_apb_wr(0x54009, 0x0);
  530 +#else
  531 + dwc_ddrphy_apb_wr(0x54008, 0x303);
  532 + dwc_ddrphy_apb_wr(0x54009, 0x200);/* no addr mirror, 0x200 addr mirror */
  533 +#endif
  534 + dwc_ddrphy_apb_wr(0x5400a, 0x0);
  535 +#ifdef RUN_ON_SILICON
  536 + dwc_ddrphy_apb_wr(0x5400b, 0x31f);
  537 +#else
  538 + dwc_ddrphy_apb_wr(0x5400b, 0x1);
  539 +#endif
  540 + dwc_ddrphy_apb_wr(0x5400c, 0xc8);
  541 + dwc_ddrphy_apb_wr(0x5400d, 0x0);
  542 + dwc_ddrphy_apb_wr(0x5400e, 0x0);
  543 + dwc_ddrphy_apb_wr(0x5400f, 0x0);
  544 + dwc_ddrphy_apb_wr(0x54010, 0x0);
  545 + dwc_ddrphy_apb_wr(0x54011, 0x0);
  546 + dwc_ddrphy_apb_wr(0x54012, 0x1);
  547 + dwc_ddrphy_apb_wr(0x5402f, mr_value[0][0]);
  548 + dwc_ddrphy_apb_wr(0x54030, mr_value[0][1]);
  549 + dwc_ddrphy_apb_wr(0x54031, mr_value[0][2]);
  550 + dwc_ddrphy_apb_wr(0x54032, mr_value[0][3]);
  551 + dwc_ddrphy_apb_wr(0x54033, mr_value[0][4]);
  552 + dwc_ddrphy_apb_wr(0x54034, mr_value[0][5]);
  553 + dwc_ddrphy_apb_wr(0x54035, mr_value[0][6]);
  554 +
  555 +#ifdef DDR_ONE_RANK
  556 + dwc_ddrphy_apb_wr(0x54036, 0x101);
  557 +#else
  558 + dwc_ddrphy_apb_wr(0x54036, 0x103);
  559 +#endif
  560 + dwc_ddrphy_apb_wr(0x54037, 0x0);
  561 + dwc_ddrphy_apb_wr(0x54038, 0x0);
  562 + dwc_ddrphy_apb_wr(0x54039, 0x0);
  563 + dwc_ddrphy_apb_wr(0x5403a, 0x0);
  564 + dwc_ddrphy_apb_wr(0x5403b, 0x0);
  565 + dwc_ddrphy_apb_wr(0x5403c, 0x0);
  566 + dwc_ddrphy_apb_wr(0x5403d, 0x0);
  567 + dwc_ddrphy_apb_wr(0x5403e, 0x0);
  568 + dwc_ddrphy_apb_wr(0x5403f, 0x1221);
  569 + dwc_ddrphy_apb_wr(0x541fc, 0x100);
  570 + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */
  571 + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
  572 + /* This allows the firmware unrestricted access to the configuration CSRs. */
  573 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  574 + /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */
  575 + /* */
  576 + /* */
  577 + /* ############################################################## */
  578 + /* */
  579 + /* (G) Execute the Training Firmware */
  580 + /* */
  581 + /* See PhyInit App Note for detailed description and function usage */
  582 + /* */
  583 + /* ############################################################## */
  584 + /* */
  585 + /* */
  586 + /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */
  587 + /* ResetToMicro fields to 1 (all other fields should be zero). */
  588 + /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */
  589 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  590 + dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  591 + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  592 + /* */
  593 + /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */
  594 + dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  595 + /* */
  596 + /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */
  597 + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. */
  598 + /* Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */
  599 + dwc_ddrphy_phyinit_userCustom_G_waitFwDone ();
  600 +
  601 + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */
  602 + /* 4. Halt the microcontroller." */
  603 + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  604 + /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */
  605 + /* */
  606 + /* */
  607 + /* ############################################################## */
  608 + /* */
  609 + /* (H) Read the Message Block results */
  610 + /* */
  611 + /* The procedure is as follows: */
  612 + /* */
  613 + /* ############################################################## */
  614 + /* */
  615 + /* */
  616 + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
  617 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  618 + /* */
  619 + /* 2. Read the Firmware Message Block to obtain the results from the training. */
  620 + /* This can be accomplished by issuing APB read commands to the DMEM addresses. */
  621 + /* Example: */
  622 + /* if (Train2D) */
  623 + /* { */
  624 + /* _read_2d_message_block_outputs_ */
  625 + /* } */
  626 + /* else */
  627 + /* { */
  628 + /* _read_1d_message_block_outputs_ */
  629 + /* } */
  630 + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0);
  631 +
  632 + /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */
  633 + /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
  634 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  635 + /* 4. If training is required at another frequency, repeat the operations starting at step (E). */
  636 + /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */
  637 + /* */
  638 + /* */
  639 + /* ############################################################## */
  640 + /* */
  641 + /* Step (E) Set the PHY input clocks to the desired frequency for pstate 1 */
  642 + /* */
  643 + /* See PhyInit App Note for detailed description and function usage */
  644 + /* */
  645 + /* ############################################################## */
  646 + /* */
  647 +#ifdef DDR4_SW_FFC
  648 + dwc_ddrphy_phyinit_userCustom_E_setDfiClk (1);
  649 +
  650 + /* */
  651 + /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */
  652 + /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=1, Train2D=0) */
  653 + /* */
  654 + /* */
  655 + /* ############################################################## */
  656 + /* */
  657 + /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */
  658 + /* */
  659 + /* See PhyInit App Note for detailed description and function usage */
  660 + /* */
  661 + /* ############################################################## */
  662 + /* */
  663 + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4/ddr4_pmu_train_dmem.incv */
  664 +
  665 + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
  666 + /* This allows the memory controller unrestricted access to the configuration CSRs. */
  667 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  668 + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */
  669 +#ifdef RUN_ON_SILICON
  670 + dwc_ddrphy_apb_wr(0x54000, 0x0);
  671 +#else
  672 + dwc_ddrphy_apb_wr(0x54000, 0x600);
  673 +#endif
  674 + dwc_ddrphy_apb_wr(0x54001, 0x0);
  675 + dwc_ddrphy_apb_wr(0x54002, 0x101);
  676 + dwc_ddrphy_apb_wr(0x54003, 0x190);
  677 + dwc_ddrphy_apb_wr(0x54004, 0x2);
  678 + dwc_ddrphy_apb_wr(0x54005, 0x0);
  679 + dwc_ddrphy_apb_wr(0x54006, 0x25e);
  680 + dwc_ddrphy_apb_wr(0x54007, 0x2000);
  681 +#ifdef DDR_ONE_RANK
  682 + dwc_ddrphy_apb_wr(0x54008, 0x101);
  683 + dwc_ddrphy_apb_wr(0x54009, 0x0);
  684 +#else
  685 + dwc_ddrphy_apb_wr(0x54008, 0x303);
  686 + dwc_ddrphy_apb_wr(0x54009, 0x200);
  687 +#endif
  688 + dwc_ddrphy_apb_wr(0x5400a, 0x0);
  689 +#ifdef RUN_ON_SILICON
  690 + dwc_ddrphy_apb_wr(0x5400b, 0x21f);
  691 +#else
  692 + dwc_ddrphy_apb_wr(0x5400b, 0x5);
  693 +#endif
  694 + dwc_ddrphy_apb_wr(0x5400c, 0xc8);
  695 + dwc_ddrphy_apb_wr(0x5400d, 0x0);
  696 + dwc_ddrphy_apb_wr(0x5400e, 0x0);
  697 + dwc_ddrphy_apb_wr(0x5400f, 0x0);
  698 + dwc_ddrphy_apb_wr(0x54010, 0x0);
  699 + dwc_ddrphy_apb_wr(0x54011, 0x0);
  700 + dwc_ddrphy_apb_wr(0x54012, 0x1);
  701 + dwc_ddrphy_apb_wr(0x5402f, mr_value[1][0]);
  702 + dwc_ddrphy_apb_wr(0x54030, mr_value[1][1]);
  703 + dwc_ddrphy_apb_wr(0x54031, mr_value[1][2]);
  704 + dwc_ddrphy_apb_wr(0x54032, mr_value[1][3]);
  705 + dwc_ddrphy_apb_wr(0x54033, mr_value[1][4]);
  706 + dwc_ddrphy_apb_wr(0x54034, mr_value[1][5]);
  707 + dwc_ddrphy_apb_wr(0x54035, mr_value[1][6]);
  708 +
  709 +#ifdef DDR_ONE_RANK
  710 + dwc_ddrphy_apb_wr(0x54036, 0x101);
  711 +#else
  712 + dwc_ddrphy_apb_wr(0x54036, 0x103);
  713 +#endif
  714 + dwc_ddrphy_apb_wr(0x54037, 0x0);
  715 + dwc_ddrphy_apb_wr(0x54038, 0x0);
  716 + dwc_ddrphy_apb_wr(0x54039, 0x0);
  717 + dwc_ddrphy_apb_wr(0x5403a, 0x0);
  718 + dwc_ddrphy_apb_wr(0x5403b, 0x0);
  719 + dwc_ddrphy_apb_wr(0x5403c, 0x0);
  720 + dwc_ddrphy_apb_wr(0x5403d, 0x0);
  721 + dwc_ddrphy_apb_wr(0x5403e, 0x0);
  722 + dwc_ddrphy_apb_wr(0x5403f, 0x1221);
  723 + dwc_ddrphy_apb_wr(0x541fc, 0x100);
  724 + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */
  725 + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
  726 + /* This allows the firmware unrestricted access to the configuration CSRs. */
  727 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  728 + /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */
  729 + /* */
  730 + /* */
  731 + /* ############################################################## */
  732 + /* */
  733 + /* (G) Execute the Training Firmware */
  734 + /* */
  735 + /* See PhyInit App Note for detailed description and function usage */
  736 + /* */
  737 + /* ############################################################## */
  738 + /* */
  739 + /* */
  740 + /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */
  741 + /* ResetToMicro fields to 1 (all other fields should be zero). */
  742 + /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */
  743 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  744 + dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  745 + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  746 + /* */
  747 + /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */
  748 + dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  749 + /* */
  750 + /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */
  751 + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */
  752 + dwc_ddrphy_phyinit_userCustom_G_waitFwDone ();
  753 +
  754 + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */
  755 + /* 4. Halt the microcontroller." */
  756 + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  757 + /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */
  758 + /* */
  759 + /* */
  760 + /* ############################################################## */
  761 + /* */
  762 + /* (H) Read the Message Block results */
  763 + /* */
  764 + /* The procedure is as follows: */
  765 + /* */
  766 + /* ############################################################## */
  767 + /* */
  768 + /* */
  769 + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
  770 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  771 + /* */
  772 + /* 2. Read the Firmware Message Block to obtain the results from the training. */
  773 + /* This can be accomplished by issuing APB read commands to the DMEM addresses. */
  774 + /* Example: */
  775 + /* if (Train2D) */
  776 + /* { */
  777 + /* _read_2d_message_block_outputs_ */
  778 + /* } */
  779 + /* else */
  780 + /* { */
  781 + /* _read_1d_message_block_outputs_ */
  782 + /* } */
  783 + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0);
  784 +
  785 + /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */
  786 + /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
  787 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  788 + /* 4. If training is required at another frequency, repeat the operations starting at step (E). */
  789 + /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */
  790 + /* */
  791 + /* */
  792 + /* ############################################################## */
  793 + /* */
  794 + /* Step (E) Set the PHY input clocks to the desired frequency for pstate 2 */
  795 + /* */
  796 + /* See PhyInit App Note for detailed description and function usage */
  797 + /* */
  798 + /* ############################################################## */
  799 + /* */
  800 + dwc_ddrphy_phyinit_userCustom_E_setDfiClk (2);
  801 +
  802 + /* */
  803 + /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */
  804 + /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=2, Train2D=0) */
  805 + /* */
  806 + /* */
  807 + /* ############################################################## */
  808 + /* */
  809 + /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */
  810 + /* */
  811 + /* See PhyInit App Note for detailed description and function usage */
  812 + /* */
  813 + /* ############################################################## */
  814 + /* */
  815 + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4/ddr4_pmu_train_dmem.incv */
  816 +
  817 + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
  818 + /* This allows the memory controller unrestricted access to the configuration CSRs. */
  819 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  820 + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */
  821 +#ifdef RUN_ON_SILICON
  822 + dwc_ddrphy_apb_wr(0x54000, 0x0);
  823 +#else
  824 + dwc_ddrphy_apb_wr(0x54000, 0x600);
  825 +#endif
  826 + dwc_ddrphy_apb_wr(0x54001, 0x0);
  827 + dwc_ddrphy_apb_wr(0x54002, 0x102);
  828 + dwc_ddrphy_apb_wr(0x54003, 0x64);
  829 + dwc_ddrphy_apb_wr(0x54004, 0x2);
  830 + dwc_ddrphy_apb_wr(0x54005, 0x0);
  831 + dwc_ddrphy_apb_wr(0x54006, 0x25e);
  832 + dwc_ddrphy_apb_wr(0x54007, 0x2000);
  833 +#ifdef DDR_ONE_RANK
  834 + dwc_ddrphy_apb_wr(0x54008, 0x101);
  835 + dwc_ddrphy_apb_wr(0x54009, 0x0);
  836 +#else
  837 + dwc_ddrphy_apb_wr(0x54008, 0x303);
  838 + dwc_ddrphy_apb_wr(0x54009, 0x200);
  839 +#endif
  840 + dwc_ddrphy_apb_wr(0x5400a, 0x0);
  841 +#ifdef RUN_ON_SILICON
  842 + dwc_ddrphy_apb_wr(0x5400b, 0x21f);
  843 +#else
  844 + dwc_ddrphy_apb_wr(0x5400b, 0x5);
  845 +#endif
  846 + dwc_ddrphy_apb_wr(0x5400c, 0xc8);
  847 + dwc_ddrphy_apb_wr(0x5400d, 0x0);
  848 + dwc_ddrphy_apb_wr(0x5400e, 0x0);
  849 + dwc_ddrphy_apb_wr(0x5400f, 0x0);
  850 + dwc_ddrphy_apb_wr(0x54010, 0x0);
  851 + dwc_ddrphy_apb_wr(0x54011, 0x0);
  852 + dwc_ddrphy_apb_wr(0x54012, 0x1);
  853 + dwc_ddrphy_apb_wr(0x5402f, mr_value[2][0]);
  854 + dwc_ddrphy_apb_wr(0x54030, mr_value[2][1]);
  855 + dwc_ddrphy_apb_wr(0x54031, mr_value[2][2]);
  856 + dwc_ddrphy_apb_wr(0x54032, mr_value[2][3]);
  857 + dwc_ddrphy_apb_wr(0x54033, mr_value[2][4]);
  858 + dwc_ddrphy_apb_wr(0x54034, mr_value[2][5]);
  859 + dwc_ddrphy_apb_wr(0x54035, mr_value[2][6]);
  860 +
  861 +#ifdef DDR_ONE_RANK
  862 + dwc_ddrphy_apb_wr(0x54036, 0x101);
  863 +#else
  864 + dwc_ddrphy_apb_wr(0x54036, 0x103);
  865 +#endif
  866 + dwc_ddrphy_apb_wr(0x54037, 0x0);
  867 + dwc_ddrphy_apb_wr(0x54038, 0x0);
  868 + dwc_ddrphy_apb_wr(0x54039, 0x0);
  869 + dwc_ddrphy_apb_wr(0x5403a, 0x0);
  870 + dwc_ddrphy_apb_wr(0x5403b, 0x0);
  871 + dwc_ddrphy_apb_wr(0x5403c, 0x0);
  872 + dwc_ddrphy_apb_wr(0x5403d, 0x0);
  873 + dwc_ddrphy_apb_wr(0x5403e, 0x0);
  874 + dwc_ddrphy_apb_wr(0x5403f, 0x1221);
  875 + dwc_ddrphy_apb_wr(0x541fc, 0x100);
  876 + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */
  877 + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
  878 + /* This allows the firmware unrestricted access to the configuration CSRs. */
  879 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  880 + /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */
  881 + /* */
  882 + /* */
  883 + /* ############################################################## */
  884 + /* */
  885 + /* (G) Execute the Training Firmware */
  886 + /* */
  887 + /* See PhyInit App Note for detailed description and function usage */
  888 + /* */
  889 + /* ############################################################## */
  890 + /* */
  891 + /* */
  892 + /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */
  893 + /* ResetToMicro fields to 1 (all other fields should be zero). */
  894 + /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */
  895 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  896 + dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  897 + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  898 + /* */
  899 + /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */
  900 + dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  901 + /* */
  902 + /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */
  903 + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */
  904 + dwc_ddrphy_phyinit_userCustom_G_waitFwDone ();
  905 +
  906 + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */
  907 + /* 4. Halt the microcontroller." */
  908 + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  909 + /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */
  910 + /* */
  911 + /* */
  912 + /* ############################################################## */
  913 + /* */
  914 + /* (H) Read the Message Block results */
  915 + /* */
  916 + /* The procedure is as follows: */
  917 + /* */
  918 + /* ############################################################## */
  919 + /* */
  920 + /* */
  921 + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
  922 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  923 + /* */
  924 + /* 2. Read the Firmware Message Block to obtain the results from the training. */
  925 + /* This can be accomplished by issuing APB read commands to the DMEM addresses. */
  926 + /* Example: */
  927 + /* if (Train2D) */
  928 + /* { */
  929 + /* _read_2d_message_block_outputs_ */
  930 + /* } */
  931 + /* else */
  932 + /* { */
  933 + /* _read_1d_message_block_outputs_ */
  934 + /* } */
  935 + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0);
  936 +
  937 + /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */
  938 + /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
  939 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  940 + /* 4. If training is required at another frequency, repeat the operations starting at step (E). */
  941 + /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */
  942 + /* */
  943 + /* */
  944 + /* ############################################################## */
  945 + /* */
  946 + /* Step (E) Set the PHY input clocks to the desired frequency for pstate 0 */
  947 + /* */
  948 + /* See PhyInit App Note for detailed description and function usage */
  949 + /* */
  950 + /* ############################################################## */
  951 + /* */
  952 + dwc_ddrphy_phyinit_userCustom_E_setDfiClk (0);
  953 +#endif /* DDR4_SW_FFC */
  954 +
  955 + /* */
  956 + /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */
  957 + /* [dwc_ddrphy_phyinit_D_loadIMEM, 2D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=1) */
  958 + /* */
  959 + /* */
  960 + /* ############################################################## */
  961 + /* */
  962 + /* (D) Load the 2D IMEM image */
  963 + /* */
  964 + /* This function loads the training firmware IMEM image into the SRAM. */
  965 + /* See PhyInit App Note for detailed description and function usage */
  966 + /* */
  967 + /* ############################################################## */
  968 + /* */
  969 + /* */
  970 + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4_2d/ddr4_2d_pmu_train_imem.incv */
  971 +
  972 + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
  973 + /* This allows the memory controller unrestricted access to the configuration CSRs. */
  974 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  975 + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x50000 size 0x4000 */
  976 + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x4000 */
  977 + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
  978 + /* This allows the firmware unrestricted access to the configuration CSRs. */
  979 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  980 + /* [dwc_ddrphy_phyinit_D_loadIMEM, 2D] End of dwc_ddrphy_phyinit_D_loadIMEM() */
  981 + /* [phyinit_F_loadDMEM, 2D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=1) */
  982 + /* */
  983 + /* */
  984 + /* ############################################################## */
  985 + /* */
  986 + /* (F) Load the 2D DMEM image and write the 2D Message Block parameters for the training firmware */
  987 + /* */
  988 + /* See PhyInit App Note for detailed description and function usage */
  989 + /* */
  990 + /* ############################################################## */
  991 + /* */
  992 + /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4_2d/ddr4_2d_pmu_train_dmem.incv */
  993 +
  994 + ddr_dbg("C: 1D training done!!! \n");
  995 +
  996 + if (Train2D) {
  997 + /* for test on silicon, load 2D dmem/imem here */
  998 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  999 +#ifdef CONFIG_SPL_VSI_FW_LOADING
  1000 + load_train_2d_code();
  1001 +#else
  1002 + ddr_load_train_code(FW_2D_IMAGE);
  1003 +#endif
  1004 + ddr_dbg("start 2d train\n");
  1005 +
  1006 + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
  1007 + /* This allows the memory controller unrestricted access to the configuration CSRs. */
  1008 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  1009 + /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x2d6 */
  1010 +#ifdef RUN_ON_SILICON
  1011 + dwc_ddrphy_apb_wr(0x54000, 0x0);
  1012 +#else
  1013 + dwc_ddrphy_apb_wr(0x54000, 0x600);
  1014 +#endif
  1015 + dwc_ddrphy_apb_wr(0x54001, 0x0);
  1016 + dwc_ddrphy_apb_wr(0x54002, 0x0);
  1017 + dwc_ddrphy_apb_wr(0x54003, 0x960);
  1018 + dwc_ddrphy_apb_wr(0x54004, 0x2);
  1019 + dwc_ddrphy_apb_wr(0x54005, 0x0);
  1020 + dwc_ddrphy_apb_wr(0x54006, 0x25e);
  1021 + dwc_ddrphy_apb_wr(0x54007, 0x2000);
  1022 +#ifdef DDR_ONE_RANK
  1023 + dwc_ddrphy_apb_wr(0x54008, 0x101);
  1024 + dwc_ddrphy_apb_wr(0x54009, 0x0);
  1025 +#else
  1026 + dwc_ddrphy_apb_wr(0x54008, 0x303);
  1027 + dwc_ddrphy_apb_wr(0x54009, 0x200);
  1028 +#endif
  1029 + dwc_ddrphy_apb_wr(0x5400a, 0x0);
  1030 +#ifdef RUN_ON_SILICON
  1031 + dwc_ddrphy_apb_wr(0x5400b, 0x61);
  1032 +#else
  1033 + dwc_ddrphy_apb_wr(0x5400b, 0x1);
  1034 +#endif
  1035 + dwc_ddrphy_apb_wr(0x5400c, 0xc8);
  1036 + dwc_ddrphy_apb_wr(0x5400d, 0x100);
  1037 + dwc_ddrphy_apb_wr(0x5400e, 0x1f7f);
  1038 + dwc_ddrphy_apb_wr(0x5400f, 0x0);
  1039 + dwc_ddrphy_apb_wr(0x54010, 0x0);
  1040 + dwc_ddrphy_apb_wr(0x54011, 0x0);
  1041 + dwc_ddrphy_apb_wr(0x54012, 0x1);
  1042 + dwc_ddrphy_apb_wr(0x5402f, mr_value[0][0]);
  1043 + dwc_ddrphy_apb_wr(0x54030, mr_value[0][1]);
  1044 + dwc_ddrphy_apb_wr(0x54031, mr_value[0][2]);
  1045 + dwc_ddrphy_apb_wr(0x54032, mr_value[0][3]);
  1046 + dwc_ddrphy_apb_wr(0x54033, mr_value[0][4]);
  1047 + dwc_ddrphy_apb_wr(0x54034, mr_value[0][5]);
  1048 + dwc_ddrphy_apb_wr(0x54035, mr_value[0][6]);
  1049 +#ifdef DDR_ONE_RANK
  1050 + dwc_ddrphy_apb_wr(0x54036, 0x101);
  1051 +#else
  1052 + dwc_ddrphy_apb_wr(0x54036, 0x103);
  1053 +#endif
  1054 + dwc_ddrphy_apb_wr(0x54037, 0x0);
  1055 + dwc_ddrphy_apb_wr(0x54038, 0x0);
  1056 + dwc_ddrphy_apb_wr(0x54039, 0x0);
  1057 + dwc_ddrphy_apb_wr(0x5403a, 0x0);
  1058 + dwc_ddrphy_apb_wr(0x5403b, 0x0);
  1059 + dwc_ddrphy_apb_wr(0x5403c, 0x0);
  1060 + dwc_ddrphy_apb_wr(0x5403d, 0x0);
  1061 + dwc_ddrphy_apb_wr(0x5403e, 0x0);
  1062 + dwc_ddrphy_apb_wr(0x5403f, 0x1221);
  1063 + dwc_ddrphy_apb_wr(0x541fc, 0x100);
  1064 + /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x2d6 */
  1065 + /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
  1066 + /* This allows the firmware unrestricted access to the configuration CSRs. */
  1067 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  1068 + /* [phyinit_F_loadDMEM, 2D] End of dwc_ddrphy_phyinit_F_loadDMEM() */
  1069 + /* */
  1070 + /* */
  1071 + /* ############################################################## */
  1072 + /* */
  1073 + /* (G) Execute the Training Firmware */
  1074 + /* */
  1075 + /* See PhyInit App Note for detailed description and function usage */
  1076 + /* */
  1077 + /* ############################################################## */
  1078 + /* */
  1079 + /* */
  1080 + /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */
  1081 + /* ResetToMicro fields to 1 (all other fields should be zero). */
  1082 + /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */
  1083 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  1084 + dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  1085 + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  1086 + /* */
  1087 + /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */
  1088 + dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  1089 + /* */
  1090 + /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */
  1091 + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */
  1092 + dwc_ddrphy_phyinit_userCustom_G_waitFwDone ();
  1093 +
  1094 + /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */
  1095 + /* 4. Halt the microcontroller." */
  1096 + dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
  1097 + /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */
  1098 + /* */
  1099 + /* */
  1100 + /* ############################################################## */
  1101 + /* */
  1102 + /* (H) Read the Message Block results */
  1103 + /* */
  1104 + /* The procedure is as follows: */
  1105 + /* */
  1106 + /* ############################################################## */
  1107 + /* */
  1108 + /* */
  1109 + /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
  1110 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  1111 + /* */
  1112 + /* 2. Read the Firmware Message Block to obtain the results from the training. */
  1113 + /* This can be accomplished by issuing APB read commands to the DMEM addresses. */
  1114 + /* Example: */
  1115 + /* if (Train2D) */
  1116 + /* { */
  1117 + /* _read_2d_message_block_outputs_ */
  1118 + /* } */
  1119 + /* else */
  1120 + /* { */
  1121 + /* _read_1d_message_block_outputs_ */
  1122 + /* } */
  1123 + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (1);
  1124 +
  1125 + /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */
  1126 + /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
  1127 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  1128 + /* 4. If training is required at another frequency, repeat the operations starting at step (E). */
  1129 + /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */
  1130 + /* [phyinit_I_loadPIEImage] Start of dwc_ddrphy_phyinit_I_loadPIEImage() */
  1131 + ddr_dbg("2D training done!!!!\n");
  1132 +
  1133 + } /* Train2D */
  1134 + } /* !after_retention */
  1135 +#ifdef ENABLE_RETENTION
  1136 + else { /* after_retention */
  1137 + restore_1d2d_trained_csr_ddr4_p012(SAVE_DDRPHY_TRAIN_ADDR);
  1138 + } /* after_retention */
  1139 +#endif
  1140 +
  1141 + /* */
  1142 + /* */
  1143 + /* ############################################################## */
  1144 + /* */
  1145 + /* (I) Load PHY Init Engine Image */
  1146 + /* */
  1147 + /* Load the PHY Initialization Engine memory with the provided initialization sequence. */
  1148 + /* See PhyInit App Note for detailed description and function usage */
  1149 + /* */
  1150 + /* */
  1151 + /* ############################################################## */
  1152 + /* */
  1153 + /* */
  1154 + /* Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
  1155 + /* This allows the memory controller unrestricted access to the configuration CSRs. */
  1156 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  1157 + /* [phyinit_I_loadPIEImage] Programming PIE Production Code */
  1158 + dwc_ddrphy_apb_wr(0x90000, 0x10); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */
  1159 + dwc_ddrphy_apb_wr(0x90001, 0x400); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */
  1160 + dwc_ddrphy_apb_wr(0x90002, 0x10e); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */
  1161 + dwc_ddrphy_apb_wr(0x90003, 0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */
  1162 + dwc_ddrphy_apb_wr(0x90004, 0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */
  1163 + dwc_ddrphy_apb_wr(0x90005, 0x8); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */
  1164 + dwc_ddrphy_apb_wr(0x90029, 0xb); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */
  1165 + dwc_ddrphy_apb_wr(0x9002a, 0x480); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */
  1166 + dwc_ddrphy_apb_wr(0x9002b, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */
  1167 + dwc_ddrphy_apb_wr(0x9002c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */
  1168 + dwc_ddrphy_apb_wr(0x9002d, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */
  1169 + dwc_ddrphy_apb_wr(0x9002e, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */
  1170 + dwc_ddrphy_apb_wr(0x9002f, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */
  1171 + dwc_ddrphy_apb_wr(0x90030, 0x478); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */
  1172 + dwc_ddrphy_apb_wr(0x90031, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */
  1173 + dwc_ddrphy_apb_wr(0x90032, 0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */
  1174 + dwc_ddrphy_apb_wr(0x90033, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */
  1175 + dwc_ddrphy_apb_wr(0x90034, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */
  1176 + dwc_ddrphy_apb_wr(0x90035, 0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */
  1177 + dwc_ddrphy_apb_wr(0x90036, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */
  1178 + dwc_ddrphy_apb_wr(0x90037, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */
  1179 + dwc_ddrphy_apb_wr(0x90038, 0x44); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */
  1180 + dwc_ddrphy_apb_wr(0x90039, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */
  1181 + dwc_ddrphy_apb_wr(0x9003a, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */
  1182 + dwc_ddrphy_apb_wr(0x9003b, 0x14f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */
  1183 + dwc_ddrphy_apb_wr(0x9003c, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */
  1184 + dwc_ddrphy_apb_wr(0x9003d, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */
  1185 + dwc_ddrphy_apb_wr(0x9003e, 0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */
  1186 + dwc_ddrphy_apb_wr(0x9003f, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */
  1187 + dwc_ddrphy_apb_wr(0x90040, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */
  1188 + dwc_ddrphy_apb_wr(0x90041, 0x4f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */
  1189 + dwc_ddrphy_apb_wr(0x90042, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */
  1190 + dwc_ddrphy_apb_wr(0x90043, 0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */
  1191 + dwc_ddrphy_apb_wr(0x90044, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */
  1192 + dwc_ddrphy_apb_wr(0x90045, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */
  1193 + dwc_ddrphy_apb_wr(0x90046, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */
  1194 + dwc_ddrphy_apb_wr(0x90047, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */
  1195 + dwc_ddrphy_apb_wr(0x90048, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */
  1196 + dwc_ddrphy_apb_wr(0x90049, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */
  1197 + dwc_ddrphy_apb_wr(0x9004a, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */
  1198 + dwc_ddrphy_apb_wr(0x9004b, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */
  1199 + dwc_ddrphy_apb_wr(0x9004c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */
  1200 + dwc_ddrphy_apb_wr(0x9004d, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */
  1201 + dwc_ddrphy_apb_wr(0x9004e, 0x45a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */
  1202 + dwc_ddrphy_apb_wr(0x9004f, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */
  1203 + dwc_ddrphy_apb_wr(0x90050, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */
  1204 + dwc_ddrphy_apb_wr(0x90051, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */
  1205 + dwc_ddrphy_apb_wr(0x90052, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */
  1206 + dwc_ddrphy_apb_wr(0x90053, 0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */
  1207 + dwc_ddrphy_apb_wr(0x90054, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */
  1208 + dwc_ddrphy_apb_wr(0x90055, 0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */
  1209 + dwc_ddrphy_apb_wr(0x90056, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */
  1210 + dwc_ddrphy_apb_wr(0x90057, 0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */
  1211 + dwc_ddrphy_apb_wr(0x90058, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */
  1212 + dwc_ddrphy_apb_wr(0x90059, 0x40c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */
  1213 + dwc_ddrphy_apb_wr(0x9005a, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */
  1214 + dwc_ddrphy_apb_wr(0x9005b, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */
  1215 + dwc_ddrphy_apb_wr(0x9005c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */
  1216 + dwc_ddrphy_apb_wr(0x9005d, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */
  1217 + dwc_ddrphy_apb_wr(0x9005e, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */
  1218 + dwc_ddrphy_apb_wr(0x9005f, 0x4040); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */
  1219 + dwc_ddrphy_apb_wr(0x90060, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */
  1220 + dwc_ddrphy_apb_wr(0x90061, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */
  1221 + dwc_ddrphy_apb_wr(0x90062, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */
  1222 + dwc_ddrphy_apb_wr(0x90063, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */
  1223 + dwc_ddrphy_apb_wr(0x90064, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */
  1224 + dwc_ddrphy_apb_wr(0x90065, 0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */
  1225 + dwc_ddrphy_apb_wr(0x90066, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */
  1226 + dwc_ddrphy_apb_wr(0x90067, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */
  1227 + dwc_ddrphy_apb_wr(0x90068, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */
  1228 + dwc_ddrphy_apb_wr(0x90069, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */
  1229 + dwc_ddrphy_apb_wr(0x9006a, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */
  1230 + dwc_ddrphy_apb_wr(0x9006b, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */
  1231 + dwc_ddrphy_apb_wr(0x9006c, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */
  1232 + dwc_ddrphy_apb_wr(0x9006d, 0x78); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */
  1233 + dwc_ddrphy_apb_wr(0x9006e, 0x549); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */
  1234 + dwc_ddrphy_apb_wr(0x9006f, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */
  1235 + dwc_ddrphy_apb_wr(0x90070, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */
  1236 + dwc_ddrphy_apb_wr(0x90071, 0xd49); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */
  1237 + dwc_ddrphy_apb_wr(0x90072, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */
  1238 + dwc_ddrphy_apb_wr(0x90073, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */
  1239 + dwc_ddrphy_apb_wr(0x90074, 0x94a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */
  1240 + dwc_ddrphy_apb_wr(0x90075, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */
  1241 + dwc_ddrphy_apb_wr(0x90076, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */
  1242 + dwc_ddrphy_apb_wr(0x90077, 0x441); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */
  1243 + dwc_ddrphy_apb_wr(0x90078, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */
  1244 + dwc_ddrphy_apb_wr(0x90079, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */
  1245 + dwc_ddrphy_apb_wr(0x9007a, 0x42); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */
  1246 + dwc_ddrphy_apb_wr(0x9007b, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */
  1247 + dwc_ddrphy_apb_wr(0x9007c, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */
  1248 + dwc_ddrphy_apb_wr(0x9007d, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */
  1249 + dwc_ddrphy_apb_wr(0x9007e, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */
  1250 + dwc_ddrphy_apb_wr(0x9007f, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */
  1251 + dwc_ddrphy_apb_wr(0x90080, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */
  1252 + dwc_ddrphy_apb_wr(0x90081, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */
  1253 + dwc_ddrphy_apb_wr(0x90082, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */
  1254 + dwc_ddrphy_apb_wr(0x90083, 0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */
  1255 + dwc_ddrphy_apb_wr(0x90084, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */
  1256 + dwc_ddrphy_apb_wr(0x90085, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */
  1257 + dwc_ddrphy_apb_wr(0x90086, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */
  1258 + dwc_ddrphy_apb_wr(0x90087, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */
  1259 + dwc_ddrphy_apb_wr(0x90088, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */
  1260 + dwc_ddrphy_apb_wr(0x90089, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */
  1261 + dwc_ddrphy_apb_wr(0x9008a, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */
  1262 + dwc_ddrphy_apb_wr(0x9008b, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */
  1263 + dwc_ddrphy_apb_wr(0x9008c, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */
  1264 + dwc_ddrphy_apb_wr(0x9008d, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */
  1265 + dwc_ddrphy_apb_wr(0x9008e, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */
  1266 + dwc_ddrphy_apb_wr(0x9008f, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */
  1267 + dwc_ddrphy_apb_wr(0x90090, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */
  1268 + dwc_ddrphy_apb_wr(0x90091, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */
  1269 + dwc_ddrphy_apb_wr(0x90092, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */
  1270 + dwc_ddrphy_apb_wr(0x90093, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */
  1271 + dwc_ddrphy_apb_wr(0x90094, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */
  1272 + dwc_ddrphy_apb_wr(0x90095, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */
  1273 + dwc_ddrphy_apb_wr(0x90096, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */
  1274 + dwc_ddrphy_apb_wr(0x90097, 0x58); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */
  1275 + dwc_ddrphy_apb_wr(0x90098, 0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */
  1276 + dwc_ddrphy_apb_wr(0x90099, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */
  1277 + dwc_ddrphy_apb_wr(0x9009a, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */
  1278 + dwc_ddrphy_apb_wr(0x9009b, 0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */
  1279 + dwc_ddrphy_apb_wr(0x9009c, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */
  1280 + dwc_ddrphy_apb_wr(0x9009d, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */
  1281 + dwc_ddrphy_apb_wr(0x9009e, 0x7); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */
  1282 + dwc_ddrphy_apb_wr(0x9009f, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */
  1283 + dwc_ddrphy_apb_wr(0x900a0, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */
  1284 + dwc_ddrphy_apb_wr(0x900a1, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */
  1285 + dwc_ddrphy_apb_wr(0x900a2, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */
  1286 + dwc_ddrphy_apb_wr(0x900a3, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */
  1287 + dwc_ddrphy_apb_wr(0x900a4, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */
  1288 + dwc_ddrphy_apb_wr(0x900a5, 0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */
  1289 + dwc_ddrphy_apb_wr(0x900a6, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */
  1290 + dwc_ddrphy_apb_wr(0x900a7, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */
  1291 + dwc_ddrphy_apb_wr(0x900a8, 0x8138); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */
  1292 + dwc_ddrphy_apb_wr(0x900a9, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */
  1293 + dwc_ddrphy_apb_wr(0x900aa, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */
  1294 + dwc_ddrphy_apb_wr(0x900ab, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */
  1295 + dwc_ddrphy_apb_wr(0x900ac, 0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */
  1296 + dwc_ddrphy_apb_wr(0x900ad, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */
  1297 + dwc_ddrphy_apb_wr(0x900ae, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */
  1298 + dwc_ddrphy_apb_wr(0x900af, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */
  1299 + dwc_ddrphy_apb_wr(0x900b0, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */
  1300 + dwc_ddrphy_apb_wr(0x900b1, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */
  1301 + dwc_ddrphy_apb_wr(0x900b2, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */
  1302 + dwc_ddrphy_apb_wr(0x900b3, 0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */
  1303 + dwc_ddrphy_apb_wr(0x900b4, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */
  1304 + dwc_ddrphy_apb_wr(0x900b5, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */
  1305 + dwc_ddrphy_apb_wr(0x900b6, 0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */
  1306 + dwc_ddrphy_apb_wr(0x900b7, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */
  1307 + dwc_ddrphy_apb_wr(0x900b8, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */
  1308 + dwc_ddrphy_apb_wr(0x900b9, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */
  1309 + dwc_ddrphy_apb_wr(0x900ba, 0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */
  1310 + dwc_ddrphy_apb_wr(0x900bb, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */
  1311 + dwc_ddrphy_apb_wr(0x900bc, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */
  1312 + dwc_ddrphy_apb_wr(0x900bd, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */
  1313 + dwc_ddrphy_apb_wr(0x900be, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */
  1314 + dwc_ddrphy_apb_wr(0x900bf, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */
  1315 + dwc_ddrphy_apb_wr(0x900c0, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */
  1316 + dwc_ddrphy_apb_wr(0x900c1, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */
  1317 + dwc_ddrphy_apb_wr(0x900c2, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */
  1318 + dwc_ddrphy_apb_wr(0x900c3, 0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */
  1319 + dwc_ddrphy_apb_wr(0x900c4, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */
  1320 + dwc_ddrphy_apb_wr(0x900c5, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */
  1321 + dwc_ddrphy_apb_wr(0x900c6, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */
  1322 + dwc_ddrphy_apb_wr(0x900c7, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */
  1323 + dwc_ddrphy_apb_wr(0x900c8, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */
  1324 + dwc_ddrphy_apb_wr(0x900c9, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */
  1325 + dwc_ddrphy_apb_wr(0x900ca, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */
  1326 + dwc_ddrphy_apb_wr(0x900cb, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */
  1327 + dwc_ddrphy_apb_wr(0x900cc, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */
  1328 + dwc_ddrphy_apb_wr(0x900cd, 0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */
  1329 + dwc_ddrphy_apb_wr(0x90006, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */
  1330 + dwc_ddrphy_apb_wr(0x90007, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */
  1331 + dwc_ddrphy_apb_wr(0x90008, 0x8); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */
  1332 + dwc_ddrphy_apb_wr(0x90009, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */
  1333 + dwc_ddrphy_apb_wr(0x9000a, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */
  1334 + dwc_ddrphy_apb_wr(0x9000b, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */
  1335 + dwc_ddrphy_apb_wr(0xd00e7, 0x400); /* DWC_DDRPHYA_APBONLY0_SequencerOverride */
  1336 + dwc_ddrphy_apb_wr(0x90017, 0x0); /* DWC_DDRPHYA_INITENG0_StartVector0b0 */
  1337 + dwc_ddrphy_apb_wr(0x90026, 0x2c); /* DWC_DDRPHYA_INITENG0_StartVector0b15 */
  1338 + /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=1200MHz, Programming Seq0BDLY0 to 0x4b */
  1339 + dwc_ddrphy_apb_wr(0x2000b, 0x4b); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */
  1340 + /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=1200MHz, Programming Seq0BDLY1 to 0x96 */
  1341 + dwc_ddrphy_apb_wr(0x2000c, 0x96); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */
  1342 + /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=1200MHz, Programming Seq0BDLY2 to 0x5dc */
  1343 + dwc_ddrphy_apb_wr(0x2000d, 0x5dc); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */
  1344 + /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=1200MHz, Programming Seq0BDLY3 to 0x2c */
  1345 + dwc_ddrphy_apb_wr(0x2000e, 0x2c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */
  1346 + /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=200MHz, Programming Seq0BDLY0 to 0xc */
  1347 + dwc_ddrphy_apb_wr(0x12000b, 0xc); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 */
  1348 + /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=200MHz, Programming Seq0BDLY1 to 0x19 */
  1349 + dwc_ddrphy_apb_wr(0x12000c, 0x19); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 */
  1350 + /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=200MHz, Programming Seq0BDLY2 to 0xfa */
  1351 + dwc_ddrphy_apb_wr(0x12000d, 0xfa); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 */
  1352 + /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=200MHz, Programming Seq0BDLY3 to 0x10 */
  1353 + dwc_ddrphy_apb_wr(0x12000e, 0x10); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 */
  1354 + /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=50MHz, Programming Seq0BDLY0 to 0x3 */
  1355 + dwc_ddrphy_apb_wr(0x22000b, 0x3); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 */
  1356 + /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=50MHz, Programming Seq0BDLY1 to 0x6 */
  1357 + dwc_ddrphy_apb_wr(0x22000c, 0x6); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 */
  1358 + /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=50MHz, Programming Seq0BDLY2 to 0x3e */
  1359 + dwc_ddrphy_apb_wr(0x22000d, 0x3e); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 */
  1360 + /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=50MHz, Programming Seq0BDLY3 to 0x10 */
  1361 + dwc_ddrphy_apb_wr(0x22000e, 0x10); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 */
  1362 + dwc_ddrphy_apb_wr(0x9000c, 0x0); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */
  1363 + dwc_ddrphy_apb_wr(0x9000d, 0x173); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */
  1364 + dwc_ddrphy_apb_wr(0x9000e, 0x60); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */
  1365 + dwc_ddrphy_apb_wr(0x9000f, 0x6110); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */
  1366 + dwc_ddrphy_apb_wr(0x90010, 0x2152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */
  1367 + dwc_ddrphy_apb_wr(0x90011, 0xdfbd); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */
  1368 + dwc_ddrphy_apb_wr(0x90012, 0xffff); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */
  1369 + dwc_ddrphy_apb_wr(0x90013, 0x6152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */
  1370 + /* Disabling Ucclk (PMU) and Hclk (training hardware) */
  1371 + dwc_ddrphy_apb_wr(0xc0080, 0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
  1372 + /* Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
  1373 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  1374 + /* [phyinit_I_loadPIEImage] End of dwc_ddrphy_phyinit_I_loadPIEImage() */
  1375 + /* */
  1376 + /* */
  1377 + /* ############################################################## */
  1378 + /* */
  1379 + /* dwc_ddrphy_phyinit_userCustom_customPostTrain is a user-editable function. */
  1380 + /* */
  1381 + /* See PhyInit App Note for detailed description and function usage */
  1382 + /* */
  1383 + /* ############################################################## */
  1384 + /* */
  1385 + dwc_ddrphy_phyinit_userCustom_customPostTrain ();
  1386 +
  1387 + /* [dwc_ddrphy_phyinit_userCustom_customPostTrain] End of dwc_ddrphy_phyinit_userCustom_customPostTrain() */
  1388 + /* [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] Start of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() */
  1389 + /* */
  1390 + /* */
  1391 + /* ############################################################## */
  1392 + /* */
  1393 + /* (J) Initialize the PHY to Mission Mode through DFI Initialization */
  1394 + /* */
  1395 + /* Initialize the PHY to mission mode as follows: */
  1396 + /* */
  1397 + /* 1. Set the PHY input clocks to the desired frequency. */
  1398 + /* 2. Initialize the PHY to mission mode by performing DFI Initialization. */
  1399 + /* Please see the DFI specification for more information. See the DFI frequency bus encoding in section <XXX>. */
  1400 + /* Note: The PHY training firmware initializes the DRAM state. if skip */
  1401 + /* training is used, the DRAM state is not initialized. */
  1402 + /* */
  1403 + /* ############################################################## */
  1404 + /* */
  1405 + dwc_ddrphy_phyinit_userCustom_J_enterMissionMode ();
  1406 +
  1407 + /* */
  1408 + /* [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] End of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() */
  1409 + /* [dwc_ddrphy_phyinit_sequence] End of dwc_ddrphy_phyinit_sequence() */
  1410 + /* [dwc_ddrphy_phyinit_main] End of dwc_ddrphy_phyinit_main() */
  1411 +
  1412 + /* ---------------------------------------------------------------------- */
  1413 + /* save 1d2d training CSR */
  1414 + /* ---------------------------------------------------------------------- */
  1415 +#ifdef ENABLE_RETENTION
  1416 + if (!after_retention) {
  1417 + save_1d2d_trained_csr_ddr4_p012(SAVE_DDRPHY_TRAIN_ADDR);
  1418 + }
  1419 +#endif
  1420 +}
board/freescale/imx8mm_evk/ddr/ddr4/ddr4_phyinit_task.c
Diff comments   View file @ 6a8f558
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <errno.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch/ddr.h>
  11 +#include <asm/arch/clock.h>
  12 +#include "ddr4_define.h"
  13 +
  14 +extern unsigned int mr_value[3][7];
  15 +void dwc_ddrphy_phyinit_userCustom_E_setDfiClk (unsigned int pstate) {
  16 + if (pstate == 1) {
  17 + ddr_dbg("C: pstate1 ...\n");
  18 +#ifdef PLLBYPASS_250MBPS
  19 + dram_enable_bypass(DRAM_BYPASSCLK_250M);
  20 +#endif
  21 +#ifdef PLLBYPASS_400MBPS
  22 + dram_enable_bypass(DRAM_BYPASSCLK_400M);
  23 +#endif
  24 + } else if (pstate == 2) {
  25 + ddr_dbg("C: pstate2 ...\n");
  26 + dram_enable_bypass(DRAM_BYPASSCLK_100M);
  27 + } else {
  28 + ddr_dbg("C: pstate0 ...\n");
  29 + dram_pll_init(DRAM_PLL_OUT_600M);
  30 + dram_disable_bypass();
  31 + }
  32 +}
  33 +
  34 +void dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void)
  35 +{
  36 + wait_ddrphy_training_complete();
  37 +}
  38 +void dwc_ddrphy_phyinit_userCustom_overrideUserInput (void) {}
  39 +void dwc_ddrphy_phyinit_userCustom_A_bringupPower (void) {}
  40 +void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy (void) {}
  41 +void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned int Train2D) {}
  42 +void dwc_ddrphy_phyinit_userCustom_customPostTrain(void) {}
  43 +void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void) {}
  44 +
  45 +void ddr4_mr_write(unsigned int mr, unsigned int data, unsigned int read, unsigned int rank)
  46 +{
  47 + unsigned int tmp, mr_mirror, data_mirror;
  48 +
  49 + /* 1. Poll MRSTAT.mr_wr_busy until it is 0. This checks that there is no outstanding MR transaction. No */
  50 + /* writes should be performed to MRCTRL0 and MRCTRL1 if MRSTAT.mr_wr_busy = 1. */
  51 + do {
  52 + tmp = reg32_read(DDRC_MRSTAT(0));
  53 + } while (tmp & 0x1);
  54 +
  55 + /* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and (for MRWs) */
  56 + /* MRCTRL1.mr_data to define the MR transaction. */
  57 + /* (A3, A4), (A5, A6), (A7, A8), (BA0, BA1), (A11, A13), */
  58 + tmp = reg32_read(DDRC_DIMMCTL(0));
  59 + if ((tmp & 0x2) && (rank == 0x2)) {
  60 + mr_mirror = (mr & 0x4) | ((mr & 0x1) << 1) | ((mr & 0x2) >> 1);/* BA0, BA1 swap */
  61 + data_mirror = (data & 0x1607) | ((data & 0x8) << 1) | ((data & 0x10) >> 1) | ((data & 0x20) << 1) |
  62 + ((data & 0x40) >> 1) | ((data & 0x80) << 1) | ((data & 0x100) >> 1) | ((data & 0x800) << 2) | ((data & 0x2000) >> 2) ;
  63 + } else {
  64 + mr_mirror = mr;
  65 + data_mirror = data;
  66 + }
  67 +
  68 + reg32_write(DDRC_MRCTRL0(0), read | (mr_mirror << 12) | (rank << 4));
  69 + reg32_write(DDRC_MRCTRL1(0), data_mirror);
  70 +
  71 + /* 3. In a separate APB transaction, write the MRCTRL0.mr_wr to 1. This bit is self-clearing, and triggers */
  72 + /* the MR transaction. The uMCTL2 then asserts the MRSTAT.mr_wr_busy while it performs the MR */
  73 + /* transaction to SDRAM, and no further accesses can be initiated until it is deasserted. */
  74 + reg32setbit(DDRC_MRCTRL0(0), 31);
  75 + do {
  76 + tmp = reg32_read(DDRC_MRSTAT(0));
  77 + } while (tmp);
  78 +
  79 +}
board/freescale/imx8mm_evk/ddr/ddr4/ddr4_swffc_fw09.c
Diff comments   View file @ 6a8f558
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <errno.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch/ddr.h>
  11 +#include <asm/arch/clock.h>
  12 +#include "anamix_common.h"
  13 +#include "ddr4_define.h"
  14 +
  15 +unsigned int mr_value[3][7] = {
  16 + {0xa34, 0x105, 0x1028, 0x240, 0x200, 0x200, 0x814}, /* pstate0 MR */
  17 + {0x204, 0x104, 0x1000, 0x040, 0x200, 0x200, 0x014}, /* pstate1 MR */
  18 + {0x204, 0x104, 0x1000, 0x040, 0x200, 0x200, 0x014} }; /* pstate2 MR */
  19 +
  20 +static unsigned int cur_pstate;
  21 +unsigned int after_retention = 0;
  22 +
  23 +void ddr4_dll_change(unsigned int pstate);
  24 +void ddr4_dll_no_change(unsigned int pstate);
  25 +
  26 +void umctl2_cfg(void)
  27 +{
  28 +#ifdef DDR_ONE_RANK
  29 + reg32_write(DDRC_MSTR(0), 0x81040010);
  30 +#else
  31 + reg32_write(DDRC_MSTR(0), 0x83040010);
  32 +#endif
  33 +
  34 + reg32_write(DDRC_PWRCTL(0), 0x000000aa);
  35 + reg32_write(DDRC_PWRTMG(0), 0x00221306);
  36 +
  37 + reg32_write(DDRC_RFSHCTL0(0), 0x00c0a070);
  38 + reg32_write(DDRC_RFSHCTL1(0), 0x00010008);
  39 + reg32_write(DDRC_RFSHCTL3(0), 0x00000010);
  40 + reg32_write(DDRC_RFSHTMG(0), 0x004980f4);
  41 + reg32_write(DDRC_CRCPARCTL0(0), 0x00000000);
  42 + reg32_write(DDRC_CRCPARCTL1(0), 0x00001010);
  43 + reg32_write(DDRC_INIT0(0), 0xc0030002);
  44 + reg32_write(DDRC_INIT1(0), 0x00020009);
  45 + reg32_write(DDRC_INIT2(0), 0x0000350f);
  46 + reg32_write(DDRC_INIT3(0), (mr_value[0][0]<<16) | (mr_value[0][1]));
  47 + reg32_write(DDRC_INIT4(0), (mr_value[0][2]<<16) | (mr_value[0][3]));
  48 + reg32_write(DDRC_INIT5(0), 0x001103cb);
  49 + reg32_write(DDRC_INIT6(0), (mr_value[0][4]<<16) | (mr_value[0][5]));
  50 + reg32_write(DDRC_INIT7(0), mr_value[0][6]);
  51 + reg32_write(DDRC_DIMMCTL(0), 0x00000032);
  52 + reg32_write(DDRC_RANKCTL(0), 0x00000fc7);
  53 + reg32_write(DDRC_DRAMTMG0(0), 0x14132813);
  54 + reg32_write(DDRC_DRAMTMG1(0), 0x0004051b);
  55 + reg32_write(DDRC_DRAMTMG2(0), 0x0808030f);
  56 + reg32_write(DDRC_DRAMTMG3(0), 0x0000400c);
  57 + reg32_write(DDRC_DRAMTMG4(0), 0x08030409);
  58 + reg32_write(DDRC_DRAMTMG5(0), 0x0e090504);
  59 + reg32_write(DDRC_DRAMTMG6(0), 0x05030000);
  60 + reg32_write(DDRC_DRAMTMG7(0), 0x0000090e);
  61 + reg32_write(DDRC_DRAMTMG8(0), 0x0606700c);
  62 + reg32_write(DDRC_DRAMTMG9(0), 0x0002040c);
  63 + reg32_write(DDRC_DRAMTMG10(0), 0x000f0c07);
  64 + reg32_write(DDRC_DRAMTMG11(0), 0x1809011d);
  65 + reg32_write(DDRC_DRAMTMG12(0), 0x0000000d);
  66 + reg32_write(DDRC_DRAMTMG13(0), 0x2b000000);
  67 + reg32_write(DDRC_DRAMTMG14(0), 0x000000a4);
  68 + reg32_write(DDRC_DRAMTMG15(0), 0x00000000);
  69 + reg32_write(DDRC_DRAMTMG17(0), 0x00250078);
  70 + reg32_write(DDRC_ZQCTL0(0), 0x51000040);
  71 + reg32_write(DDRC_ZQCTL1(0), 0x00000070);
  72 + reg32_write(DDRC_ZQCTL2(0), 0x00000000);
  73 + reg32_write(DDRC_DFITMG0(0), 0x038b820b);
  74 + reg32_write(DDRC_DFITMG1(0), 0x02020103);
  75 + reg32_write(DDRC_DFILPCFG0(0), 0x07f04011); /* [8]dfi_lp_en_sr = 0 */
  76 + reg32_write(DDRC_DFILPCFG1(0), 0x000000b0);
  77 + reg32_write(DDRC_DFIUPD0(0), 0xe0400018);
  78 + reg32_write(DDRC_DFIUPD1(0), 0x0048005a);
  79 + reg32_write(DDRC_DFIUPD2(0), 0x80000000);
  80 + reg32_write(DDRC_DFIMISC(0), 0x00000001);
  81 + reg32_write(DDRC_DFITMG2(0), 0x00000b0b);
  82 + reg32_write(DDRC_DFITMG3(0), 0x00000001);
  83 + reg32_write(DDRC_DBICTL(0), 0x00000000);
  84 + reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000);
  85 +
  86 +#ifdef DDR_ONE_RANK
  87 + reg32_write(DDRC_ADDRMAP0(0), 0x0000001F);
  88 +#else
  89 + reg32_write(DDRC_ADDRMAP0(0), 0x00000017); /* [4:0]cs0: 6+23 */
  90 +#endif
  91 + reg32_write(DDRC_ADDRMAP1(0), 0x003F0909); /* [5:0] bank b0: 2+9; [13:8] b1: P3+9 ; [21:16] b2: 4+, unused */
  92 + reg32_write(DDRC_ADDRMAP2(0), 0x01010100); /* [3:0] col-b2: 2; [11:8] col-b3: 3+1; [19:16] col-b4: 4+1 ; [27:24] col-b5: 5+1 */
  93 + reg32_write(DDRC_ADDRMAP3(0), 0x01010101); /* [3:0] col-b6: 6+1; [11:8] col-b7: 7+1; [19:16] col-b8: 8+1 ; [27:24] col-b9: 9+1 */
  94 + reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f); /* col-b10, col-b11 not used */
  95 + reg32_write(DDRC_ADDRMAP5(0), 0x07070707); /* [3:0] row-b0: 6+7; [11:8] row-b1: 7+7; [19:16] row-b2_b10: 8~16+7; [27:24] row-b11: 17+7 */
  96 + reg32_write(DDRC_ADDRMAP6(0), 0x07070707); /* [3:0] row-b12:18+7; [11:8] row-b13: 19+7; [19:16] row-b14:20+7; [27:24] row-b15: 21+7 */
  97 + reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f); /* col-b10, col-b11 not used */
  98 + reg32_write(DDRC_ADDRMAP8(0), 0x00003F01); /* [5:0] bg-b0: 2+1; [13:8]bg-b1:3+, unused */
  99 + reg32_write(DDRC_ADDRMAP9(0), 0x0a020b06); /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
  100 + reg32_write(DDRC_ADDRMAP10(0), 0x0a0a0a0a);/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
  101 + reg32_write(DDRC_ADDRMAP11(0), 0x00000000);
  102 +
  103 + /* FREQ0: BL8, CL=16, CWL=16, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1, so wr_odt_hold=5+1+1=7 */
  104 + /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */
  105 + reg32_write(DDRC_ODTCFG(0), 0x07000600);
  106 +#ifdef DDR_ONE_RANK
  107 + reg32_write(DDRC_ODTMAP(0), 0x0001);
  108 +#else
  109 + reg32_write(DDRC_ODTMAP(0), 0x0201);/* disable ODT0x00001120); */
  110 +#endif
  111 + reg32_write(DDRC_SCHED(0), 0x317d1a07);
  112 + reg32_write(DDRC_SCHED1(0), 0x0000000f);
  113 + reg32_write(DDRC_PERFHPR1(0), 0x2a001b76);
  114 + reg32_write(DDRC_PERFLPR1(0), 0x7300b473);
  115 + reg32_write(DDRC_PERFWR1(0), 0x30000e06);
  116 + reg32_write(DDRC_DBG0(0), 0x00000014);
  117 + reg32_write(DDRC_DBG1(0), 0x00000000);
  118 + reg32_write(DDRC_DBGCMD(0), 0x00000000);
  119 + reg32_write(DDRC_SWCTL(0), 0x00000001);
  120 + reg32_write(DDRC_POISONCFG(0), 0x00000010);
  121 + reg32_write(DDRC_PCCFG(0), 0x00000100);/* bl_exp_mode=1 */
  122 + reg32_write(DDRC_PCFGR_0(0), 0x00013193);
  123 + reg32_write(DDRC_PCFGW_0(0), 0x00006096);
  124 + reg32_write(DDRC_PCTRL_0(0), 0x00000001);
  125 + reg32_write(DDRC_PCFGQOS0_0(0), 0x02000c00);
  126 + reg32_write(DDRC_PCFGQOS1_0(0), 0x003c00db);
  127 + reg32_write(DDRC_PCFGWQOS0_0(0), 0x00100009);
  128 + reg32_write(DDRC_PCFGWQOS1_0(0), 0x00000002);
  129 +
  130 +}
  131 +
  132 +void umctl2_freq1_cfg(void)
  133 +{
  134 + reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0021a0c0);
  135 +#ifdef PLLBYPASS_250MBPS
  136 + reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x000f0011);/* tREFI=7.8us */
  137 +#endif
  138 +#ifdef PLLBYPASS_400MBPS
  139 + reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x0018001a);/* tREFI=7.8us */
  140 +#endif
  141 +
  142 + reg32_write(DDRC_FREQ1_INIT3(0), (mr_value[1][0]<<16) | (mr_value[1][1]));
  143 + reg32_write(DDRC_FREQ1_INIT4(0), (mr_value[1][2]<<16) | (mr_value[1][3]));
  144 + reg32_write(DDRC_FREQ1_INIT6(0), (mr_value[1][4]<<16) | (mr_value[1][5]));
  145 + reg32_write(DDRC_FREQ1_INIT7(0), mr_value[1][6]);
  146 +#ifdef PLLBYPASS_250MBPS
  147 + reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0c0e0403);/* t_ras_max=9*7.8us, t_ras_min=35ns */
  148 +#endif
  149 +#ifdef PLLBYPASS_400MBPS
  150 + reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0c0e0604);/* t_ras_max=9*7.8us, t_ras_min=35ns */
  151 +#endif
  152 + reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x00030314);
  153 + reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x0505040a);
  154 + reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x0000400c);
  155 + reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x06040307); /* tRP=6 --> 7 */
  156 + reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x090d0202);
  157 + reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x0a070008);
  158 + reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x00000d09);
  159 + reg32_write(DDRC_FREQ1_DRAMTMG8(0), 0x08084b09);
  160 + reg32_write(DDRC_FREQ1_DRAMTMG9(0), 0x00020308);
  161 + reg32_write(DDRC_FREQ1_DRAMTMG10(0), 0x000f0d06);
  162 + reg32_write(DDRC_FREQ1_DRAMTMG11(0), 0x12060111);
  163 + reg32_write(DDRC_FREQ1_DRAMTMG12(0), 0x00000008);
  164 + reg32_write(DDRC_FREQ1_DRAMTMG13(0), 0x21000000);
  165 + reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x00000000);
  166 + reg32_write(DDRC_FREQ1_DRAMTMG15(0), 0x00000000);
  167 + reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x00c6007d);
  168 + reg32_write(DDRC_FREQ1_ZQCTL0(0), 0x51000040);
  169 + reg32_write(DDRC_FREQ1_DFITMG0(0), 0x03858204);
  170 + reg32_write(DDRC_FREQ1_DFITMG1(0), 0x00020103);
  171 + reg32_write(DDRC_FREQ1_DFITMG2(0), 0x00000504);
  172 + reg32_write(DDRC_FREQ1_DFITMG3(0), 0x00000001);
  173 + /* FREQ1: BL8, CL=10, CWL=9, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1 */
  174 + /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */
  175 + reg32_write(DDRC_FREQ1_ODTCFG(0), 0x07000601);
  176 +}
  177 +
  178 +void umctl2_freq2_cfg(void)
  179 +{
  180 + reg32_write(DDRC_FREQ2_RFSHCTL0(0), 0x0021a0c0);
  181 + reg32_write(DDRC_FREQ2_RFSHTMG(0), 0x0006000e);/* tREFI=7.8us */
  182 + reg32_write(DDRC_FREQ2_INIT3(0), (mr_value[2][0]<<16) | (mr_value[2][1]));
  183 + reg32_write(DDRC_FREQ2_INIT4(0), (mr_value[2][2]<<16) | (mr_value[2][3]));
  184 + reg32_write(DDRC_FREQ2_INIT6(0), (mr_value[2][4]<<16) | (mr_value[2][5]));
  185 + reg32_write(DDRC_FREQ2_INIT7(0), mr_value[2][6]);
  186 + reg32_write(DDRC_FREQ2_DRAMTMG0(0), 0x0c0e0101);/* t_ras_max=9*7.8us, t_ras_min=35ns */
  187 + reg32_write(DDRC_FREQ2_DRAMTMG1(0), 0x00030314);
  188 + reg32_write(DDRC_FREQ2_DRAMTMG2(0), 0x0505040a);
  189 + reg32_write(DDRC_FREQ2_DRAMTMG3(0), 0x0000400c);
  190 + reg32_write(DDRC_FREQ2_DRAMTMG4(0), 0x06040307); /* tRP=6 --> 7 */
  191 + reg32_write(DDRC_FREQ2_DRAMTMG5(0), 0x090d0202);
  192 + reg32_write(DDRC_FREQ2_DRAMTMG6(0), 0x0a070008);
  193 + reg32_write(DDRC_FREQ2_DRAMTMG7(0), 0x00000d09);
  194 + reg32_write(DDRC_FREQ2_DRAMTMG8(0), 0x08084b09);
  195 + reg32_write(DDRC_FREQ2_DRAMTMG9(0), 0x00020308);
  196 + reg32_write(DDRC_FREQ2_DRAMTMG10(0), 0x000f0d06);
  197 + reg32_write(DDRC_FREQ2_DRAMTMG11(0), 0x12060111);
  198 + reg32_write(DDRC_FREQ2_DRAMTMG12(0), 0x00000008);
  199 + reg32_write(DDRC_FREQ2_DRAMTMG13(0), 0x21000000);
  200 + reg32_write(DDRC_FREQ2_DRAMTMG14(0), 0x00000000);
  201 + reg32_write(DDRC_FREQ2_DRAMTMG15(0), 0x00000000);
  202 + reg32_write(DDRC_FREQ2_DRAMTMG17(0), 0x00c6007d);
  203 + reg32_write(DDRC_FREQ2_ZQCTL0(0), 0x51000040);
  204 + reg32_write(DDRC_FREQ2_DFITMG0(0), 0x03858204);
  205 + reg32_write(DDRC_FREQ2_DFITMG1(0), 0x00020103);
  206 + reg32_write(DDRC_FREQ2_DFITMG2(0), 0x00000504);
  207 + reg32_write(DDRC_FREQ2_DFITMG3(0), 0x00000001);
  208 + /* FREQ1: BL8, CL=10, CWL=9, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1 */
  209 + /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */
  210 + reg32_write(DDRC_FREQ2_ODTCFG(0), 0x07000601);
  211 +}
  212 +
  213 +
  214 +void ddr4_pub_train(void)
  215 +{
  216 + volatile unsigned int tmp_t;
  217 + after_retention = 0;
  218 +
  219 + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F); /* assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, [4]src_system_rst_b! */
  220 + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); /* deassert [4]src_system_rst_b! */
  221 +
  222 + /* change the clock source of dram_apb_clk_root */
  223 + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); /* to source 4 --800MHz/4 */
  224 +
  225 + /* DDR_PLL_CONFIG_600MHz(); */
  226 + dram_pll_init(DRAM_PLL_OUT_600M);
  227 + ddr_dbg("C: dram pll init finished\n");
  228 +
  229 + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
  230 + reg32setbit(0x303A00F8, 5);/* PU_PGC_SW_PUP_REQ */
  231 +
  232 + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */
  233 +
  234 + reg32_write(DDRC_DBG1(0), 0x00000001);
  235 + reg32_write(DDRC_PWRCTL(0), 0x00000001);
  236 +
  237 + while (0 != (0x7 & reg32_read(DDRC_STAT(0))))
  238 + ;
  239 +
  240 + ddr_dbg("C: cfg umctl2 regs ...\n");
  241 + umctl2_cfg();
  242 +#ifdef DDR4_SW_FFC
  243 + umctl2_freq1_cfg();
  244 + umctl2_freq2_cfg();
  245 +#endif
  246 +
  247 + reg32_write(DDRC_RFSHCTL3(0), 0x00000011);
  248 + /* RESET: <ctn> DEASSERTED */
  249 + /* RESET: <a Port 0 DEASSERTED(0) */
  250 + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
  251 + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
  252 +
  253 + reg32_write(DDRC_DBG1(0), 0x00000000);
  254 + reg32_write(DDRC_PWRCTL(0), 0x00000aa);
  255 + reg32_write(DDRC_SWCTL(0), 0x00000000);
  256 +
  257 + reg32_write(DDRC_DFIMISC(0), 0x00000000);
  258 +
  259 + ddr_dbg("C: phy training ...\n");
  260 + ddr4_phyinit_train_sw_ffc(1);/* for dvfs flow, 2D training is a must item */
  261 +
  262 + do {
  263 + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0x00020097);
  264 + ddr_dbg("C: Waiting CalBusy value = 0\n");
  265 + } while (tmp_t != 0);
  266 +
  267 + reg32_write(DDRC_DFIMISC(0), 0x00000020);
  268 +
  269 + /* wait DFISTAT.dfi_init_complete to 1 */
  270 + while (0 == (0x1 & reg32_read(DDRC_DFISTAT(0))))
  271 + ;
  272 +
  273 + /* clear DFIMISC.dfi_init_complete_en */
  274 + reg32_write(DDRC_DFIMISC(0), 0x00000000);
  275 + /* set DFIMISC.dfi_init_complete_en again */
  276 + reg32_write(DDRC_DFIMISC(0), 0x00000001);
  277 + reg32_write(DDRC_PWRCTL(0), 0x0000088);
  278 +
  279 + /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */
  280 + reg32_write(DDRC_SWCTL(0), 0x00000001);
  281 + /* wait SWSTAT.sw_done_ack to 1 */
  282 + while (0 == (0x1 & reg32_read(DDRC_SWSTAT(0))))
  283 + ;
  284 +
  285 + /* wait STAT to normal state */
  286 + while (0x1 != (0x7 & reg32_read(DDRC_STAT(0))))
  287 + ;
  288 +
  289 + reg32_write(DDRC_PWRCTL(0), 0x0000088);
  290 + reg32_write(DDRC_PCTRL_0(0), 0x00000001);
  291 + reg32_write(DDRC_RFSHCTL3(0), 0x00000010); /* dis_auto-refresh is set to 0 */
  292 +}
  293 +
  294 +void ddr4_switch_freq(unsigned int pstate)
  295 +{
  296 + if ((pstate != 0 && cur_pstate == 0) || (pstate == 0 && cur_pstate != 0)) {
  297 + ddr4_dll_change(pstate);
  298 + } else {
  299 + ddr4_dll_no_change(pstate);
  300 + ddr_dbg("dll no change\n");
  301 + }
  302 + cur_pstate = pstate;
  303 +}
  304 +
  305 +void dram_all_mr_cfg(unsigned int pstate)
  306 +{
  307 + unsigned int i;
  308 + /* 15. Perform MRS commands as required to re-program timing registers in the SDRAM for the new */
  309 + /* frequency (in particular, CL, CWL and WR may need to be changed). */
  310 + for (i = 0; i < 7; i++)
  311 + ddr4_mr_write(i, mr_value[pstate][i], 0, 0x1);
  312 +
  313 +#ifndef DDR_ONE_RANK
  314 + for (i = 0; i < 7; i++)
  315 + ddr4_mr_write(i, mr_value[pstate][i], 0, 0x2);
  316 +#endif
  317 +}
  318 +
  319 +void sw_pstate(unsigned int pstate)
  320 +{
  321 + volatile unsigned int tmp;
  322 + unsigned int i;
  323 + /* the the following software programming sequence to switch from DLL-on to DLL-off, or reverse: */
  324 + reg32_write(DDRC_SWCTL(0), 0x0000);
  325 + /* 12. Change the clock frequency to the desired value. */
  326 + /* 13. Update any registers which may be required to change for the new frequency. This includes quasidynamic and dynamic registers. This includes both uMCTL2 registers and PHY registers. */
  327 + reg32_write(DDRC_DFIMISC(0), 0x00000000);
  328 + reg32_write(DDRC_MSTR2(0), pstate);/* UMCTL2_REGS_FREQ1 */
  329 + reg32setbit(DDRC_MSTR(0), 29);
  330 +
  331 + /* dvfs.18. Toggle RFSHCTL3.refresh_update_level to allow the new refresh-related register values to */
  332 + /* propagate to the refresh logic. */
  333 + tmp = reg32_read(DDRC_RFSHCTL3(0));
  334 + if ((tmp & 0x2) == 0x2)
  335 + reg32_write(DDRC_RFSHCTL3(0), tmp & 0xFFFFFFFD);
  336 + else
  337 + reg32_write(DDRC_RFSHCTL3(0), tmp | 0x2);
  338 +
  339 + /* dvfs.19. If required, trigger the initialization in the PHY. If using the gen2 multiPHY, PLL initialization */
  340 + /* should be triggered at this point. See the PHY databook for details about the frequency change */
  341 + /* procedure. */
  342 + reg32_write(DDRC_DFIMISC(0), 0x00000000 | (pstate<<8));/* pstate1 */
  343 + reg32_write(DDRC_DFIMISC(0), 0x00000020 | (pstate<<8));
  344 +
  345 + /* wait DFISTAT.dfi_init_complete to 0 */
  346 + do {
  347 + tmp = 0x1 & reg32_read(DDRC_DFISTAT(0));
  348 + } while (tmp);
  349 +
  350 + dwc_ddrphy_phyinit_userCustom_E_setDfiClk(pstate);
  351 +
  352 + reg32_write(DDRC_DFIMISC(0), 0x00000000 | (pstate<<8));
  353 + /* wait DFISTAT.dfi_init_complete to 1 */
  354 + do {
  355 + tmp = 0x1 & reg32_read(DDRC_DFISTAT(0));
  356 + } while (!tmp);
  357 +
  358 + /* When changing frequencies the controller may violate the JEDEC requirement that no */
  359 + /* more than 16 refreshes should be issued within 2*tREFI. These extra refreshes are not */
  360 + /* expected to cause a problem in the SDRAM. This issue can be avoided by waiting for at */
  361 + /* least 2*tREFI before exiting self-refresh in step 19. */
  362 + for (i = 20; i > 0; i--)
  363 + ;
  364 + ddr_dbg("C: waiting for 2*tREFI (2*7.8us)\n");
  365 +
  366 + /* 14. Exit the self-refresh state by setting PWRCTL.selfref_sw = 0. */
  367 + reg32clrbit(DDRC_PWRCTL(0), 5);
  368 + do {
  369 + tmp = 0x3f & (reg32_read((DDRC_STAT(0))));
  370 + ddr_dbg("C: waiting for exit Self Refresh\n");
  371 + } while (tmp == 0x23);
  372 +}
  373 +
  374 +void ddr4_dll_change(unsigned int pstate)
  375 +{
  376 + volatile unsigned int tmp;
  377 + enum DLL_STATE { NO_CHANGE = 0, ON2OFF = 1, OFF2ON = 2} dll_sw; /* 0-no change, 1-on2off, 2-off2on.; */
  378 +
  379 + if (pstate != 0 && cur_pstate == 0) {
  380 + dll_sw = ON2OFF;
  381 + ddr_dbg("dll ON2OFF\n");
  382 + } else if (pstate == 0 && cur_pstate != 0) {
  383 + dll_sw = OFF2ON;
  384 + ddr_dbg("dll OFF2ON\n");
  385 + } else {
  386 + dll_sw = NO_CHANGE;
  387 + }
  388 +
  389 + /* the the following software programming sequence to switch from DLL-on to DLL-off, or reverse: */
  390 + reg32_write(DDRC_SWCTL(0), 0x0000);
  391 +
  392 + /* 1. Set the DBG1.dis_hif = 1. This prevents further reads/writes being received on the HIF. */
  393 + reg32setbit(DDRC_DBG1(0), 1);
  394 + /* 2. Set ZQCTL0.dis_auto_zq=1, to disable automatic generation of ZQCS/MPC(ZQ calibration) */
  395 + /* commands */
  396 + if (pstate == 1)
  397 + reg32setbit(DDRC_FREQ1_ZQCTL0(0), 31);
  398 + else if (pstate == 2)
  399 + reg32setbit(DDRC_FREQ2_ZQCTL0(0), 31);
  400 + else
  401 + reg32setbit(DDRC_ZQCTL0(0), 31);
  402 +
  403 + /* 3. Set RFSHCTL3.dis_auto_refresh=1, to disable automatic refreshes */
  404 + reg32setbit(DDRC_RFSHCTL3(0), 0);
  405 + /* 4. Ensure all commands have been flushed from the uMCTL2 by polling */
  406 + /* DBGCAM.wr_data_pipeline_empty, DBGCAM.rd_data_pipeline_empty1, */
  407 + /* DBGCAM.dbg_wr_q_depth, DBGCAM.dbg_lpr_q_depth, DBGCAM.dbg_rd_q_empty, */
  408 + /* DBGCAM.dbg_wr_q_empty. */
  409 + do {
  410 + tmp = 0x06000000 & reg32_read(DDRC_DBGCAM(0));
  411 + } while (tmp != 0x06000000);
  412 + reg32_write(DDRC_PCTRL_0(0), 0x00000000);
  413 + /* 5. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to disable RTT_NOM: */
  414 + /* a. DDR3: Write 0 to MR1[9], MR1[6] and MR1[2] */
  415 + /* b. DDR4: Write 0 to MR1[10:8] */
  416 + if (mr_value[pstate][1] & 0x700) {
  417 + ddr4_mr_write(1, mr_value[pstate][1] & 0xF8FF, 0, 0x1);
  418 +#ifndef DDR_ONE_RANK
  419 + ddr4_mr_write(1, mr_value[pstate][1] & 0xF8FF, 0, 0x2);
  420 +#endif
  421 + }
  422 + /* 6. For DDR4 only: Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to write 0 to */
  423 + /* MR5[8:6] to disable RTT_PARK */
  424 + if (mr_value[pstate][5] & 0x1C0) {
  425 + ddr4_mr_write(5, mr_value[pstate][5] & 0xFE3F, 0, 0x1);
  426 +#ifndef DDR_ONE_RANK
  427 + ddr4_mr_write(5, mr_value[pstate][5] & 0xFE3F, 0, 0x2);
  428 +#endif
  429 + }
  430 +
  431 + if (dll_sw == ON2OFF) {
  432 + /* 7. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to write 0 to MR2[11:9], to */
  433 + /* disable RTT_WR (and therefore disable dynamic ODT). This applies for both DDR3 and DDR4. */
  434 + if (mr_value[pstate][2] & 0xE00) {
  435 + ddr4_mr_write(2, mr_value[pstate][2] & 0xF1FF, 0, 0x1);
  436 +#ifndef DDR_ONE_RANK
  437 + ddr4_mr_write(2, mr_value[pstate][2] & 0xF1FF, 0, 0x2);
  438 +#endif
  439 + }
  440 + /* 8. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to disable the DLL. The */
  441 + /* timing of this MRS is automatically handled by the uMCTL2. */
  442 + /* a. DDR3: Write 1 to MR1[0] */
  443 + /* b. DDR4: Write 0 to MR1[0] */
  444 + ddr4_mr_write(1, mr_value[pstate][1] & 0xFFFE, 0, 0x1);
  445 +#ifndef DDR_ONE_RANK
  446 + ddr4_mr_write(1, mr_value[pstate][1] & 0xFFFE, 0, 0x2);
  447 +#endif
  448 + }
  449 +
  450 + /* 9. Put the SDRAM into self-refresh mode by setting PWRCTL.selfref_sw = 1, and polling */
  451 + /* STAT.operating_mode to ensure the DDRC has entered self-refresh. */
  452 + reg32setbit(DDRC_PWRCTL(0), 5);
  453 + /* 10. Wait until STAT.operating_mode[1:0]==11 indicating that the DWC_ddr_umctl2 core is in selfrefresh mode. Ensure transition to self-refresh was due to software by checking that */
  454 + /* STAT.selfref_type[1:0]=2`b10. */
  455 + do {
  456 + tmp = 0x3f & (reg32_read((DDRC_STAT(0))));
  457 + ddr_dbg("C: wait DRAM in Self Refresh\n");
  458 + } while (tmp != 0x23);
  459 +
  460 + /* 11. Set the MSTR.dll_off_mode = 1 or 0. */
  461 + if (dll_sw == ON2OFF)
  462 + reg32setbit(DDRC_MSTR(0), 15);
  463 +
  464 + if (dll_sw == OFF2ON)
  465 + reg32clrbit(DDRC_MSTR(0), 15);
  466 +
  467 + sw_pstate(pstate);
  468 +
  469 + /* DRAM dll enable */
  470 + if (dll_sw == OFF2ON) {
  471 + ddr4_mr_write(1, mr_value[pstate][1] | 0x1, 0, 0x1);
  472 +#ifndef DDR_ONE_RANK
  473 + ddr4_mr_write(1, mr_value[pstate][1] | 0x1, 0, 0x2);
  474 +#endif
  475 + /* DRAM dll reset, self-clear */
  476 + ddr4_mr_write(0, mr_value[pstate][0] | 0x100, 0, 0x1);
  477 +#ifndef DDR_ONE_RANK
  478 + ddr4_mr_write(0, mr_value[pstate][0] | 0x100, 0, 0x2);
  479 +#endif
  480 + }
  481 +
  482 + dram_all_mr_cfg(pstate);
  483 +
  484 + /* 16. Re-enable automatic generation of ZQCS/MPC(ZQ calibration) commands, by setting */
  485 + /* ZQCTL0.dis_auto_zq=0 if they were previously disabled */
  486 + if (pstate == 1)
  487 + reg32clrbit(DDRC_FREQ1_ZQCTL0(0), 31);
  488 + else if (pstate == 2)
  489 + reg32clrbit(DDRC_FREQ2_ZQCTL0(0), 31);
  490 + else
  491 + reg32clrbit(DDRC_ZQCTL0(0), 31);
  492 +
  493 + /* 17. Re-enable automatic refreshes (RFSHCTL3.dis_auto_refresh = 0) if they have been previously */
  494 + /* disabled. */
  495 + reg32clrbit(DDRC_RFSHCTL3(0), 0);
  496 + /* 18. Restore ZQCTL0.dis_srx_zqcl */
  497 + /* 19. Write DBG1.dis_hif = 0 to re-enable reads and writes. */
  498 + reg32clrbit(DDRC_DBG1(0), 1);
  499 +
  500 + reg32_write(DDRC_PCTRL_0(0), 0x00000001);
  501 + /* 27. Write 1 to SBRCTL.scrub_en. Enable SBR if desired, only required if SBR instantiated. */
  502 +
  503 + /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */
  504 + reg32_write(DDRC_SWCTL(0), 0x0001);
  505 +
  506 + /* wait SWSTAT.sw_done_ack to 1 */
  507 + do {
  508 + tmp = 0x1 & reg32_read(DDRC_SWSTAT(0));
  509 + } while (!tmp);
  510 +}
  511 +
  512 +void ddr4_dll_no_change(unsigned int pstate)
  513 +{
  514 + volatile unsigned int tmp;
  515 + /* ------------------------------------------------------------------------------------- */
  516 + /* change to pstate1 */
  517 + /* ------------------------------------------------------------------------------------- */
  518 + /* 1. Program one of UMCTL2_REGS_FREQ1/2/3, whichever you prefer, timing register-set with the */
  519 + /* timing settings required for the alternative clock frequency. */
  520 + /* set SWCTL.sw_done to disable quasi-dynamic register programming outside reset. */
  521 + reg32_write(DDRC_SWCTL(0), 0x0000);
  522 +
  523 + /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */
  524 + /* wait SWSTAT.sw_done_ack to 1 */
  525 +
  526 + /* 2. Write 0 to PCTRL_n.port_en. This blocks AXI port(s) from taking any transaction (blocks traffic on */
  527 + /* AXI ports). */
  528 + reg32_write(DDRC_PCTRL_0(0), 0x00000000);
  529 + /* 3. Poll PSTAT.rd_port_busy_n=0 and PSTAT.wr_port_busy_n=0. Wait until all AXI ports are idle (the */
  530 + /* uMCTL2 core has to be idle). */
  531 + do {
  532 + tmp = reg32_read(DDRC_PSTAT(0));
  533 + } while (tmp & 0x10001);
  534 +
  535 + /* 4. Write 0 to SBRCTL.scrub_en. Disable SBR, required only if SBR instantiated. */
  536 + /* 5. Poll SBRSTAT.scrub_busy=0. Indicates that there are no outstanding SBR read commands (required */
  537 + /* only if SBR instantiated). */
  538 + /* 6. Set DERATEEN.derate_enable = 0, if DERATEEN.derate_eanble = 1 and the read latency (RL) value */
  539 + /* needs to change after the frequency change (LPDDR2/3/4 only). */
  540 + /* 7. Set DBG1.dis_hif=1 so that no new commands will be accepted by the uMCTL2. */
  541 + reg32setbit(DDRC_DBG1(0), 1);
  542 + /* 8. Poll DBGCAM.dbg_wr_q_empty and DBGCAM.dbg_rd_q_empty to ensure that write and read data */
  543 + /* buffers are empty. */
  544 + do {
  545 + tmp = 0x06000000 & reg32_read(DDRC_DBGCAM(0));
  546 + } while (tmp != 0x06000000);
  547 + /* 9. For DDR4, update MR6 with the new tDLLK value via the Mode Register Write signals */
  548 + /* (MRCTRL0.mr_x/MRCTRL1.mr_x). */
  549 + /* 10. Set DFILPCFG0.dfi_lp_en_sr = 0, if DFILPCFG0.dfi_lp_en_sr = 1, and wait until DFISTAT.dfi_lp_ack */
  550 + /* = 0. */
  551 + /* 11. If DFI PHY Master interface is active in uMCTL2 (DFIPHYMSTR.phymstr_en == 1'b1) then disable it */
  552 + /* by programming DFIPHYMSTR.phymstr_en = 1'b0. */
  553 + /* 12. Wait until STAT.operating_mode[1:0]!=11 indicating that the DWC_ddr_umctl2 controller is not in */
  554 + /* self-refresh mode. */
  555 + tmp = 0x3 & (reg32_read((DDRC_STAT(0))));
  556 + if (tmp == 0x3) {
  557 + ddr_dbg("C: Error DRAM should not in Self Refresh\n");
  558 + ddr_dbg("vt_error\n");
  559 + }
  560 + /* 13. Assert PWRCTL.selfref_sw for the DWC_ddr_umctl2 core to enter the self-refresh mode. */
  561 + reg32setbit(DDRC_PWRCTL(0), 5);
  562 + /* 14. Wait until STAT.operating_mode[1:0]==11 indicating that the DWC_ddr_umctl2 core is in selfrefresh mode. Ensure transition to self-refresh was due to software by checking that STAT.selfref_type[1:0]=2'b10. */
  563 + do {
  564 + tmp = 0x3f & (reg32_read((DDRC_STAT(0))));
  565 + ddr_dbg("C: DRAM in Self Refresh\n");
  566 + } while (tmp != 0x23);
  567 +
  568 + sw_pstate(pstate);
  569 + dram_all_mr_cfg(pstate);
  570 +
  571 +
  572 + /* 23. Enable HIF commands by setting DBG1.dis_hif=0. */
  573 + reg32clrbit(DDRC_DBG1(0), 1);
  574 + /* 24. Reset DERATEEN.derate_enable = 1 if DERATEEN.derate_enable has been set to 0 in step 6. */
  575 + /* 25. If DFI PHY Master interface was active in uMCTL2 (DFIPHYMSTR.phymstr_en == 1'b1) before the */
  576 + /* step 11 then enable it back by programming DFIPHYMSTR.phymstr_en = 1'b1. */
  577 + /* 26. Write 1 to PCTRL_n.port_en. AXI port(s) are no longer blocked from taking transactions (Re-enable */
  578 + /* traffic on AXI ports). */
  579 + reg32_write(DDRC_PCTRL_0(0), 0x00000001);
  580 + /* 27. Write 1 to SBRCTL.scrub_en. Enable SBR if desired, only required if SBR instantiated. */
  581 +
  582 +
  583 +
  584 + /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */
  585 + reg32_write(DDRC_SWCTL(0), 0x0001);
  586 +
  587 + /* wait SWSTAT.sw_done_ack to 1 */
  588 + do {
  589 + tmp = 0x1 & reg32_read(DDRC_SWSTAT(0));
  590 + } while (!tmp);
  591 +
  592 +
  593 +}
  594 +
  595 +void ddr_init(void)
  596 +{
  597 + /* initialize DDR4-2400 (umctl2@800MHz) */
  598 + ddr4_pub_train();
  599 +}
board/freescale/imx8mm_evk/ddr/ddr4/restore_1d2d_trained_csr_ddr4_p012.c
Diff comments   View file @ 6a8f558
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <errno.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch/ddr.h>
  11 +#include <asm/arch/clock.h>
  12 +#include "ddr4_define.h"
  13 +
  14 +#ifdef ENABLE_RETENTION
  15 +static const unsigned int restore_csr[] = {
  16 + 0x200b2,
  17 + 0x1200b2,
  18 + 0x2200b2,
  19 + 0x200cb,
  20 +#ifdef RUN_ON_SILICON
  21 + 0x10043,
  22 + 0x110043,
  23 + 0x210043,
  24 + 0x10143,
  25 + 0x110143,
  26 + 0x210143,
  27 + 0x11043,
  28 + 0x111043,
  29 + 0x211043,
  30 + 0x11143,
  31 + 0x111143,
  32 + 0x211143,
  33 + 0x12043,
  34 + 0x112043,
  35 + 0x212043,
  36 + 0x12143,
  37 + 0x112143,
  38 + 0x212143,
  39 + 0x13043,
  40 + 0x113043,
  41 + 0x213043,
  42 + 0x13143,
  43 + 0x113143,
  44 + 0x213143,
  45 + 0x80,
  46 + 0x100080,
  47 + 0x200080,
  48 + 0x1080,
  49 + 0x101080,
  50 + 0x201080,
  51 + 0x2080,
  52 + 0x102080,
  53 + 0x202080,
  54 + 0x3080,
  55 + 0x103080,
  56 + 0x203080,
  57 + 0x4080,
  58 + 0x104080,
  59 + 0x204080,
  60 + 0x5080,
  61 + 0x105080,
  62 + 0x205080,
  63 + 0x6080,
  64 + 0x106080,
  65 + 0x206080,
  66 + 0x7080,
  67 + 0x107080,
  68 + 0x207080,
  69 + 0x8080,
  70 + 0x108080,
  71 + 0x208080,
  72 + 0x9080,
  73 + 0x109080,
  74 + 0x209080,
  75 + 0x10080,
  76 + 0x110080,
  77 + 0x210080,
  78 + 0x10180,
  79 + 0x110180,
  80 + 0x210180,
  81 + 0x10081,
  82 + 0x110081,
  83 + 0x210081,
  84 + 0x10181,
  85 + 0x110181,
  86 + 0x210181,
  87 + 0x10082,
  88 + 0x110082,
  89 + 0x210082,
  90 + 0x10182,
  91 + 0x110182,
  92 + 0x210182,
  93 + 0x10083,
  94 + 0x110083,
  95 + 0x210083,
  96 + 0x10183,
  97 + 0x110183,
  98 + 0x210183,
  99 + 0x11080,
  100 + 0x111080,
  101 + 0x211080,
  102 + 0x11180,
  103 + 0x111180,
  104 + 0x211180,
  105 + 0x11081,
  106 + 0x111081,
  107 + 0x211081,
  108 + 0x11181,
  109 + 0x111181,
  110 + 0x211181,
  111 + 0x11082,
  112 + 0x111082,
  113 + 0x211082,
  114 + 0x11182,
  115 + 0x111182,
  116 + 0x211182,
  117 + 0x11083,
  118 + 0x111083,
  119 + 0x211083,
  120 + 0x11183,
  121 + 0x111183,
  122 + 0x211183,
  123 + 0x12080,
  124 + 0x112080,
  125 + 0x212080,
  126 + 0x12180,
  127 + 0x112180,
  128 + 0x212180,
  129 + 0x12081,
  130 + 0x112081,
  131 + 0x212081,
  132 + 0x12181,
  133 + 0x112181,
  134 + 0x212181,
  135 + 0x12082,
  136 + 0x112082,
  137 + 0x212082,
  138 + 0x12182,
  139 + 0x112182,
  140 + 0x212182,
  141 + 0x12083,
  142 + 0x112083,
  143 + 0x212083,
  144 + 0x12183,
  145 + 0x112183,
  146 + 0x212183,
  147 + 0x13080,
  148 + 0x113080,
  149 + 0x213080,
  150 + 0x13180,
  151 + 0x113180,
  152 + 0x213180,
  153 + 0x13081,
  154 + 0x113081,
  155 + 0x213081,
  156 + 0x13181,
  157 + 0x113181,
  158 + 0x213181,
  159 + 0x13082,
  160 + 0x113082,
  161 + 0x213082,
  162 + 0x13182,
  163 + 0x113182,
  164 + 0x213182,
  165 + 0x13083,
  166 + 0x113083,
  167 + 0x213083,
  168 + 0x13183,
  169 + 0x113183,
  170 + 0x213183,
  171 + 0x100d0,
  172 + 0x1100d0,
  173 + 0x2100d0,
  174 + 0x101d0,
  175 + 0x1101d0,
  176 + 0x2101d0,
  177 + 0x100d1,
  178 + 0x1100d1,
  179 + 0x2100d1,
  180 + 0x101d1,
  181 + 0x1101d1,
  182 + 0x2101d1,
  183 + 0x100d2,
  184 + 0x1100d2,
  185 + 0x2100d2,
  186 + 0x101d2,
  187 + 0x1101d2,
  188 + 0x2101d2,
  189 + 0x100d3,
  190 + 0x1100d3,
  191 + 0x2100d3,
  192 + 0x101d3,
  193 + 0x1101d3,
  194 + 0x2101d3,
  195 + 0x110d0,
  196 + 0x1110d0,
  197 + 0x2110d0,
  198 + 0x111d0,
  199 + 0x1111d0,
  200 + 0x2111d0,
  201 + 0x110d1,
  202 + 0x1110d1,
  203 + 0x2110d1,
  204 + 0x111d1,
  205 + 0x1111d1,
  206 + 0x2111d1,
  207 + 0x110d2,
  208 + 0x1110d2,
  209 + 0x2110d2,
  210 + 0x111d2,
  211 + 0x1111d2,
  212 + 0x2111d2,
  213 + 0x110d3,
  214 + 0x1110d3,
  215 + 0x2110d3,
  216 + 0x111d3,
  217 + 0x1111d3,
  218 + 0x2111d3,
  219 + 0x120d0,
  220 + 0x1120d0,
  221 + 0x2120d0,
  222 + 0x121d0,
  223 + 0x1121d0,
  224 + 0x2121d0,
  225 + 0x120d1,
  226 + 0x1120d1,
  227 + 0x2120d1,
  228 + 0x121d1,
  229 + 0x1121d1,
  230 + 0x2121d1,
  231 + 0x120d2,
  232 + 0x1120d2,
  233 + 0x2120d2,
  234 + 0x121d2,
  235 + 0x1121d2,
  236 + 0x2121d2,
  237 + 0x120d3,
  238 + 0x1120d3,
  239 + 0x2120d3,
  240 + 0x121d3,
  241 + 0x1121d3,
  242 + 0x2121d3,
  243 + 0x130d0,
  244 + 0x1130d0,
  245 + 0x2130d0,
  246 + 0x131d0,
  247 + 0x1131d0,
  248 + 0x2131d0,
  249 + 0x130d1,
  250 + 0x1130d1,
  251 + 0x2130d1,
  252 + 0x131d1,
  253 + 0x1131d1,
  254 + 0x2131d1,
  255 + 0x130d2,
  256 + 0x1130d2,
  257 + 0x2130d2,
  258 + 0x131d2,
  259 + 0x1131d2,
  260 + 0x2131d2,
  261 + 0x130d3,
  262 + 0x1130d3,
  263 + 0x2130d3,
  264 + 0x131d3,
  265 + 0x1131d3,
  266 + 0x2131d3,
  267 + 0x10068,
  268 + 0x10168,
  269 + 0x10268,
  270 + 0x10368,
  271 + 0x10468,
  272 + 0x10568,
  273 + 0x10668,
  274 + 0x10768,
  275 + 0x10868,
  276 + 0x10069,
  277 + 0x10169,
  278 + 0x10269,
  279 + 0x10369,
  280 + 0x10469,
  281 + 0x10569,
  282 + 0x10669,
  283 + 0x10769,
  284 + 0x10869,
  285 + 0x1006a,
  286 + 0x1016a,
  287 + 0x1026a,
  288 + 0x1036a,
  289 + 0x1046a,
  290 + 0x1056a,
  291 + 0x1066a,
  292 + 0x1076a,
  293 + 0x1086a,
  294 + 0x1006b,
  295 + 0x1016b,
  296 + 0x1026b,
  297 + 0x1036b,
  298 + 0x1046b,
  299 + 0x1056b,
  300 + 0x1066b,
  301 + 0x1076b,
  302 + 0x1086b,
  303 + 0x11068,
  304 + 0x11168,
  305 + 0x11268,
  306 + 0x11368,
  307 + 0x11468,
  308 + 0x11568,
  309 + 0x11668,
  310 + 0x11768,
  311 + 0x11868,
  312 + 0x11069,
  313 + 0x11169,
  314 + 0x11269,
  315 + 0x11369,
  316 + 0x11469,
  317 + 0x11569,
  318 + 0x11669,
  319 + 0x11769,
  320 + 0x11869,
  321 + 0x1106a,
  322 + 0x1116a,
  323 + 0x1126a,
  324 + 0x1136a,
  325 + 0x1146a,
  326 + 0x1156a,
  327 + 0x1166a,
  328 + 0x1176a,
  329 + 0x1186a,
  330 + 0x1106b,
  331 + 0x1116b,
  332 + 0x1126b,
  333 + 0x1136b,
  334 + 0x1146b,
  335 + 0x1156b,
  336 + 0x1166b,
  337 + 0x1176b,
  338 + 0x1186b,
  339 + 0x12068,
  340 + 0x12168,
  341 + 0x12268,
  342 + 0x12368,
  343 + 0x12468,
  344 + 0x12568,
  345 + 0x12668,
  346 + 0x12768,
  347 + 0x12868,
  348 + 0x12069,
  349 + 0x12169,
  350 + 0x12269,
  351 + 0x12369,
  352 + 0x12469,
  353 + 0x12569,
  354 + 0x12669,
  355 + 0x12769,
  356 + 0x12869,
  357 + 0x1206a,
  358 + 0x1216a,
  359 + 0x1226a,
  360 + 0x1236a,
  361 + 0x1246a,
  362 + 0x1256a,
  363 + 0x1266a,
  364 + 0x1276a,
  365 + 0x1286a,
  366 + 0x1206b,
  367 + 0x1216b,
  368 + 0x1226b,
  369 + 0x1236b,
  370 + 0x1246b,
  371 + 0x1256b,
  372 + 0x1266b,
  373 + 0x1276b,
  374 + 0x1286b,
  375 + 0x13068,
  376 + 0x13168,
  377 + 0x13268,
  378 + 0x13368,
  379 + 0x13468,
  380 + 0x13568,
  381 + 0x13668,
  382 + 0x13768,
  383 + 0x13868,
  384 + 0x13069,
  385 + 0x13169,
  386 + 0x13269,
  387 + 0x13369,
  388 + 0x13469,
  389 + 0x13569,
  390 + 0x13669,
  391 + 0x13769,
  392 + 0x13869,
  393 + 0x1306a,
  394 + 0x1316a,
  395 + 0x1326a,
  396 + 0x1336a,
  397 + 0x1346a,
  398 + 0x1356a,
  399 + 0x1366a,
  400 + 0x1376a,
  401 + 0x1386a,
  402 + 0x1306b,
  403 + 0x1316b,
  404 + 0x1326b,
  405 + 0x1336b,
  406 + 0x1346b,
  407 + 0x1356b,
  408 + 0x1366b,
  409 + 0x1376b,
  410 + 0x1386b,
  411 + 0x1008c,
  412 + 0x11008c,
  413 + 0x21008c,
  414 + 0x1018c,
  415 + 0x11018c,
  416 + 0x21018c,
  417 + 0x1008d,
  418 + 0x11008d,
  419 + 0x21008d,
  420 + 0x1018d,
  421 + 0x11018d,
  422 + 0x21018d,
  423 + 0x1008e,
  424 + 0x11008e,
  425 + 0x21008e,
  426 + 0x1018e,
  427 + 0x11018e,
  428 + 0x21018e,
  429 + 0x1008f,
  430 + 0x11008f,
  431 + 0x21008f,
  432 + 0x1018f,
  433 + 0x11018f,
  434 + 0x21018f,
  435 + 0x1108c,
  436 + 0x11108c,
  437 + 0x21108c,
  438 + 0x1118c,
  439 + 0x11118c,
  440 + 0x21118c,
  441 + 0x1108d,
  442 + 0x11108d,
  443 + 0x21108d,
  444 + 0x1118d,
  445 + 0x11118d,
  446 + 0x21118d,
  447 + 0x1108e,
  448 + 0x11108e,
  449 + 0x21108e,
  450 + 0x1118e,
  451 + 0x11118e,
  452 + 0x21118e,
  453 + 0x1108f,
  454 + 0x11108f,
  455 + 0x21108f,
  456 + 0x1118f,
  457 + 0x11118f,
  458 + 0x21118f,
  459 + 0x1208c,
  460 + 0x11208c,
  461 + 0x21208c,
  462 + 0x1218c,
  463 + 0x11218c,
  464 + 0x21218c,
  465 + 0x1208d,
  466 + 0x11208d,
  467 + 0x21208d,
  468 + 0x1218d,
  469 + 0x11218d,
  470 + 0x21218d,
  471 + 0x1208e,
  472 + 0x11208e,
  473 + 0x21208e,
  474 + 0x1218e,
  475 + 0x11218e,
  476 + 0x21218e,
  477 + 0x1208f,
  478 + 0x11208f,
  479 + 0x21208f,
  480 + 0x1218f,
  481 + 0x11218f,
  482 + 0x21218f,
  483 + 0x1308c,
  484 + 0x11308c,
  485 + 0x21308c,
  486 + 0x1318c,
  487 + 0x11318c,
  488 + 0x21318c,
  489 + 0x1308d,
  490 + 0x11308d,
  491 + 0x21308d,
  492 + 0x1318d,
  493 + 0x11318d,
  494 + 0x21318d,
  495 + 0x1308e,
  496 + 0x11308e,
  497 + 0x21308e,
  498 + 0x1318e,
  499 + 0x11318e,
  500 + 0x21318e,
  501 + 0x1308f,
  502 + 0x11308f,
  503 + 0x21308f,
  504 + 0x1318f,
  505 + 0x11318f,
  506 + 0x21318f,
  507 + 0x100c0,
  508 + 0x1100c0,
  509 + 0x2100c0,
  510 + 0x101c0,
  511 + 0x1101c0,
  512 + 0x2101c0,
  513 + 0x102c0,
  514 + 0x1102c0,
  515 + 0x2102c0,
  516 + 0x103c0,
  517 + 0x1103c0,
  518 + 0x2103c0,
  519 + 0x104c0,
  520 + 0x1104c0,
  521 + 0x2104c0,
  522 + 0x105c0,
  523 + 0x1105c0,
  524 + 0x2105c0,
  525 + 0x106c0,
  526 + 0x1106c0,
  527 + 0x2106c0,
  528 + 0x107c0,
  529 + 0x1107c0,
  530 + 0x2107c0,
  531 + 0x108c0,
  532 + 0x1108c0,
  533 + 0x2108c0,
  534 + 0x100c1,
  535 + 0x1100c1,
  536 + 0x2100c1,
  537 + 0x101c1,
  538 + 0x1101c1,
  539 + 0x2101c1,
  540 + 0x102c1,
  541 + 0x1102c1,
  542 + 0x2102c1,
  543 + 0x103c1,
  544 + 0x1103c1,
  545 + 0x2103c1,
  546 + 0x104c1,
  547 + 0x1104c1,
  548 + 0x2104c1,
  549 + 0x105c1,
  550 + 0x1105c1,
  551 + 0x2105c1,
  552 + 0x106c1,
  553 + 0x1106c1,
  554 + 0x2106c1,
  555 + 0x107c1,
  556 + 0x1107c1,
  557 + 0x2107c1,
  558 + 0x108c1,
  559 + 0x1108c1,
  560 + 0x2108c1,
  561 + 0x100c2,
  562 + 0x1100c2,
  563 + 0x2100c2,
  564 + 0x101c2,
  565 + 0x1101c2,
  566 + 0x2101c2,
  567 + 0x102c2,
  568 + 0x1102c2,
  569 + 0x2102c2,
  570 + 0x103c2,
  571 + 0x1103c2,
  572 + 0x2103c2,
  573 + 0x104c2,
  574 + 0x1104c2,
  575 + 0x2104c2,
  576 + 0x105c2,
  577 + 0x1105c2,
  578 + 0x2105c2,
  579 + 0x106c2,
  580 + 0x1106c2,
  581 + 0x2106c2,
  582 + 0x107c2,
  583 + 0x1107c2,
  584 + 0x2107c2,
  585 + 0x108c2,
  586 + 0x1108c2,
  587 + 0x2108c2,
  588 + 0x100c3,
  589 + 0x1100c3,
  590 + 0x2100c3,
  591 + 0x101c3,
  592 + 0x1101c3,
  593 + 0x2101c3,
  594 + 0x102c3,
  595 + 0x1102c3,
  596 + 0x2102c3,
  597 + 0x103c3,
  598 + 0x1103c3,
  599 + 0x2103c3,
  600 + 0x104c3,
  601 + 0x1104c3,
  602 + 0x2104c3,
  603 + 0x105c3,
  604 + 0x1105c3,
  605 + 0x2105c3,
  606 + 0x106c3,
  607 + 0x1106c3,
  608 + 0x2106c3,
  609 + 0x107c3,
  610 + 0x1107c3,
  611 + 0x2107c3,
  612 + 0x108c3,
  613 + 0x1108c3,
  614 + 0x2108c3,
  615 + 0x110c0,
  616 + 0x1110c0,
  617 + 0x2110c0,
  618 + 0x111c0,
  619 + 0x1111c0,
  620 + 0x2111c0,
  621 + 0x112c0,
  622 + 0x1112c0,
  623 + 0x2112c0,
  624 + 0x113c0,
  625 + 0x1113c0,
  626 + 0x2113c0,
  627 + 0x114c0,
  628 + 0x1114c0,
  629 + 0x2114c0,
  630 + 0x115c0,
  631 + 0x1115c0,
  632 + 0x2115c0,
  633 + 0x116c0,
  634 + 0x1116c0,
  635 + 0x2116c0,
  636 + 0x117c0,
  637 + 0x1117c0,
  638 + 0x2117c0,
  639 + 0x118c0,
  640 + 0x1118c0,
  641 + 0x2118c0,
  642 + 0x110c1,
  643 + 0x1110c1,
  644 + 0x2110c1,
  645 + 0x111c1,
  646 + 0x1111c1,
  647 + 0x2111c1,
  648 + 0x112c1,
  649 + 0x1112c1,
  650 + 0x2112c1,
  651 + 0x113c1,
  652 + 0x1113c1,
  653 + 0x2113c1,
  654 + 0x114c1,
  655 + 0x1114c1,
  656 + 0x2114c1,
  657 + 0x115c1,
  658 + 0x1115c1,
  659 + 0x2115c1,
  660 + 0x116c1,
  661 + 0x1116c1,
  662 + 0x2116c1,
  663 + 0x117c1,
  664 + 0x1117c1,
  665 + 0x2117c1,
  666 + 0x118c1,
  667 + 0x1118c1,
  668 + 0x2118c1,
  669 + 0x110c2,
  670 + 0x1110c2,
  671 + 0x2110c2,
  672 + 0x111c2,
  673 + 0x1111c2,
  674 + 0x2111c2,
  675 + 0x112c2,
  676 + 0x1112c2,
  677 + 0x2112c2,
  678 + 0x113c2,
  679 + 0x1113c2,
  680 + 0x2113c2,
  681 + 0x114c2,
  682 + 0x1114c2,
  683 + 0x2114c2,
  684 + 0x115c2,
  685 + 0x1115c2,
  686 + 0x2115c2,
  687 + 0x116c2,
  688 + 0x1116c2,
  689 + 0x2116c2,
  690 + 0x117c2,
  691 + 0x1117c2,
  692 + 0x2117c2,
  693 + 0x118c2,
  694 + 0x1118c2,
  695 + 0x2118c2,
  696 + 0x110c3,
  697 + 0x1110c3,
  698 + 0x2110c3,
  699 + 0x111c3,
  700 + 0x1111c3,
  701 + 0x2111c3,
  702 + 0x112c3,
  703 + 0x1112c3,
  704 + 0x2112c3,
  705 + 0x113c3,
  706 + 0x1113c3,
  707 + 0x2113c3,
  708 + 0x114c3,
  709 + 0x1114c3,
  710 + 0x2114c3,
  711 + 0x115c3,
  712 + 0x1115c3,
  713 + 0x2115c3,
  714 + 0x116c3,
  715 + 0x1116c3,
  716 + 0x2116c3,
  717 + 0x117c3,
  718 + 0x1117c3,
  719 + 0x2117c3,
  720 + 0x118c3,
  721 + 0x1118c3,
  722 + 0x2118c3,
  723 + 0x120c0,
  724 + 0x1120c0,
  725 + 0x2120c0,
  726 + 0x121c0,
  727 + 0x1121c0,
  728 + 0x2121c0,
  729 + 0x122c0,
  730 + 0x1122c0,
  731 + 0x2122c0,
  732 + 0x123c0,
  733 + 0x1123c0,
  734 + 0x2123c0,
  735 + 0x124c0,
  736 + 0x1124c0,
  737 + 0x2124c0,
  738 + 0x125c0,
  739 + 0x1125c0,
  740 + 0x2125c0,
  741 + 0x126c0,
  742 + 0x1126c0,
  743 + 0x2126c0,
  744 + 0x127c0,
  745 + 0x1127c0,
  746 + 0x2127c0,
  747 + 0x128c0,
  748 + 0x1128c0,
  749 + 0x2128c0,
  750 + 0x120c1,
  751 + 0x1120c1,
  752 + 0x2120c1,
  753 + 0x121c1,
  754 + 0x1121c1,
  755 + 0x2121c1,
  756 + 0x122c1,
  757 + 0x1122c1,
  758 + 0x2122c1,
  759 + 0x123c1,
  760 + 0x1123c1,
  761 + 0x2123c1,
  762 + 0x124c1,
  763 + 0x1124c1,
  764 + 0x2124c1,
  765 + 0x125c1,
  766 + 0x1125c1,
  767 + 0x2125c1,
  768 + 0x126c1,
  769 + 0x1126c1,
  770 + 0x2126c1,
  771 + 0x127c1,
  772 + 0x1127c1,
  773 + 0x2127c1,
  774 + 0x128c1,
  775 + 0x1128c1,
  776 + 0x2128c1,
  777 + 0x120c2,
  778 + 0x1120c2,
  779 + 0x2120c2,
  780 + 0x121c2,
  781 + 0x1121c2,
  782 + 0x2121c2,
  783 + 0x122c2,
  784 + 0x1122c2,
  785 + 0x2122c2,
  786 + 0x123c2,
  787 + 0x1123c2,
  788 + 0x2123c2,
  789 + 0x124c2,
  790 + 0x1124c2,
  791 + 0x2124c2,
  792 + 0x125c2,
  793 + 0x1125c2,
  794 + 0x2125c2,
  795 + 0x126c2,
  796 + 0x1126c2,
  797 + 0x2126c2,
  798 + 0x127c2,
  799 + 0x1127c2,
  800 + 0x2127c2,
  801 + 0x128c2,
  802 + 0x1128c2,
  803 + 0x2128c2,
  804 + 0x120c3,
  805 + 0x1120c3,
  806 + 0x2120c3,
  807 + 0x121c3,
  808 + 0x1121c3,
  809 + 0x2121c3,
  810 + 0x122c3,
  811 + 0x1122c3,
  812 + 0x2122c3,
  813 + 0x123c3,
  814 + 0x1123c3,
  815 + 0x2123c3,
  816 + 0x124c3,
  817 + 0x1124c3,
  818 + 0x2124c3,
  819 + 0x125c3,
  820 + 0x1125c3,
  821 + 0x2125c3,
  822 + 0x126c3,
  823 + 0x1126c3,
  824 + 0x2126c3,
  825 + 0x127c3,
  826 + 0x1127c3,
  827 + 0x2127c3,
  828 + 0x128c3,
  829 + 0x1128c3,
  830 + 0x2128c3,
  831 + 0x130c0,
  832 + 0x1130c0,
  833 + 0x2130c0,
  834 + 0x131c0,
  835 + 0x1131c0,
  836 + 0x2131c0,
  837 + 0x132c0,
  838 + 0x1132c0,
  839 + 0x2132c0,
  840 + 0x133c0,
  841 + 0x1133c0,
  842 + 0x2133c0,
  843 + 0x134c0,
  844 + 0x1134c0,
  845 + 0x2134c0,
  846 + 0x135c0,
  847 + 0x1135c0,
  848 + 0x2135c0,
  849 + 0x136c0,
  850 + 0x1136c0,
  851 + 0x2136c0,
  852 + 0x137c0,
  853 + 0x1137c0,
  854 + 0x2137c0,
  855 + 0x138c0,
  856 + 0x1138c0,
  857 + 0x2138c0,
  858 + 0x130c1,
  859 + 0x1130c1,
  860 + 0x2130c1,
  861 + 0x131c1,
  862 + 0x1131c1,
  863 + 0x2131c1,
  864 + 0x132c1,
  865 + 0x1132c1,
  866 + 0x2132c1,
  867 + 0x133c1,
  868 + 0x1133c1,
  869 + 0x2133c1,
  870 + 0x134c1,
  871 + 0x1134c1,
  872 + 0x2134c1,
  873 + 0x135c1,
  874 + 0x1135c1,
  875 + 0x2135c1,
  876 + 0x136c1,
  877 + 0x1136c1,
  878 + 0x2136c1,
  879 + 0x137c1,
  880 + 0x1137c1,
  881 + 0x2137c1,
  882 + 0x138c1,
  883 + 0x1138c1,
  884 + 0x2138c1,
  885 + 0x130c2,
  886 + 0x1130c2,
  887 + 0x2130c2,
  888 + 0x131c2,
  889 + 0x1131c2,
  890 + 0x2131c2,
  891 + 0x132c2,
  892 + 0x1132c2,
  893 + 0x2132c2,
  894 + 0x133c2,
  895 + 0x1133c2,
  896 + 0x2133c2,
  897 + 0x134c2,
  898 + 0x1134c2,
  899 + 0x2134c2,
  900 + 0x135c2,
  901 + 0x1135c2,
  902 + 0x2135c2,
  903 + 0x136c2,
  904 + 0x1136c2,
  905 + 0x2136c2,
  906 + 0x137c2,
  907 + 0x1137c2,
  908 + 0x2137c2,
  909 + 0x138c2,
  910 + 0x1138c2,
  911 + 0x2138c2,
  912 + 0x130c3,
  913 + 0x1130c3,
  914 + 0x2130c3,
  915 + 0x131c3,
  916 + 0x1131c3,
  917 + 0x2131c3,
  918 + 0x132c3,
  919 + 0x1132c3,
  920 + 0x2132c3,
  921 + 0x133c3,
  922 + 0x1133c3,
  923 + 0x2133c3,
  924 + 0x134c3,
  925 + 0x1134c3,
  926 + 0x2134c3,
  927 + 0x135c3,
  928 + 0x1135c3,
  929 + 0x2135c3,
  930 + 0x136c3,
  931 + 0x1136c3,
  932 + 0x2136c3,
  933 + 0x137c3,
  934 + 0x1137c3,
  935 + 0x2137c3,
  936 + 0x138c3,
  937 + 0x1138c3,
  938 + 0x2138c3,
  939 + 0x10020,
  940 + 0x110020,
  941 + 0x210020,
  942 + 0x11020,
  943 + 0x111020,
  944 + 0x211020,
  945 + 0x12020,
  946 + 0x112020,
  947 + 0x212020,
  948 + 0x13020,
  949 + 0x113020,
  950 + 0x213020,
  951 + 0x2007d,
  952 + 0x12007d,
  953 + 0x22007d,
  954 + 0x10040,
  955 + 0x10140,
  956 + 0x10240,
  957 + 0x10340,
  958 + 0x10440,
  959 + 0x10540,
  960 + 0x10640,
  961 + 0x10740,
  962 + 0x10840,
  963 + 0x10030,
  964 + 0x10130,
  965 + 0x10230,
  966 + 0x10330,
  967 + 0x10430,
  968 + 0x10530,
  969 + 0x10630,
  970 + 0x10730,
  971 + 0x10830,
  972 + 0x11040,
  973 + 0x11140,
  974 + 0x11240,
  975 + 0x11340,
  976 + 0x11440,
  977 + 0x11540,
  978 + 0x11640,
  979 + 0x11740,
  980 + 0x11840,
  981 + 0x11030,
  982 + 0x11130,
  983 + 0x11230,
  984 + 0x11330,
  985 + 0x11430,
  986 + 0x11530,
  987 + 0x11630,
  988 + 0x11730,
  989 + 0x11830,
  990 + 0x12040,
  991 + 0x12140,
  992 + 0x12240,
  993 + 0x12340,
  994 + 0x12440,
  995 + 0x12540,
  996 + 0x12640,
  997 + 0x12740,
  998 + 0x12840,
  999 + 0x12030,
  1000 + 0x12130,
  1001 + 0x12230,
  1002 + 0x12330,
  1003 + 0x12430,
  1004 + 0x12530,
  1005 + 0x12630,
  1006 + 0x12730,
  1007 + 0x12830,
  1008 + 0x13040,
  1009 + 0x13140,
  1010 + 0x13240,
  1011 + 0x13340,
  1012 + 0x13440,
  1013 + 0x13540,
  1014 + 0x13640,
  1015 + 0x13740,
  1016 + 0x13840,
  1017 + 0x13030,
  1018 + 0x13130,
  1019 + 0x13230,
  1020 + 0x13330,
  1021 + 0x13430,
  1022 + 0x13530,
  1023 + 0x13630,
  1024 + 0x13730,
  1025 + 0x13830,
  1026 +#endif
  1027 + 0
  1028 +};
  1029 +
  1030 +void restore_1d2d_trained_csr_ddr4_p012(unsigned int addr)
  1031 +{
  1032 + unsigned int i;
  1033 +
  1034 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  1035 + for (i = 0; restore_csr[i] != 0; i++) {
  1036 + dwc_ddrphy_apb_wr(restore_csr[i], reg32_read(addr + (i << 2)));
  1037 + }
  1038 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  1039 +
  1040 + ddr_dbg("restore 1d2d training registers done \n");
  1041 +}
  1042 +#endif
board/freescale/imx8mm_evk/ddr/ddr4/save_1d2d_trained_csr_ddr4_p012.c
Diff comments   View file @ 6a8f558
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <errno.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch/ddr.h>
  11 +#include <asm/arch/clock.h>
  12 +#include "ddr4_define.h"
  13 +
  14 +#ifdef ENABLE_RETENTION
  15 +static const unsigned int save_csr[] = {
  16 + 0x200b2,
  17 + 0x1200b2,
  18 + 0x2200b2,
  19 + 0x200cb,
  20 +#ifdef RUN_ON_SILICON
  21 + 0x10043,
  22 + 0x110043,
  23 + 0x210043,
  24 + 0x10143,
  25 + 0x110143,
  26 + 0x210143,
  27 + 0x11043,
  28 + 0x111043,
  29 + 0x211043,
  30 + 0x11143,
  31 + 0x111143,
  32 + 0x211143,
  33 + 0x12043,
  34 + 0x112043,
  35 + 0x212043,
  36 + 0x12143,
  37 + 0x112143,
  38 + 0x212143,
  39 + 0x13043,
  40 + 0x113043,
  41 + 0x213043,
  42 + 0x13143,
  43 + 0x113143,
  44 + 0x213143,
  45 + 0x80,
  46 + 0x100080,
  47 + 0x200080,
  48 + 0x1080,
  49 + 0x101080,
  50 + 0x201080,
  51 + 0x2080,
  52 + 0x102080,
  53 + 0x202080,
  54 + 0x3080,
  55 + 0x103080,
  56 + 0x203080,
  57 + 0x4080,
  58 + 0x104080,
  59 + 0x204080,
  60 + 0x5080,
  61 + 0x105080,
  62 + 0x205080,
  63 + 0x6080,
  64 + 0x106080,
  65 + 0x206080,
  66 + 0x7080,
  67 + 0x107080,
  68 + 0x207080,
  69 + 0x8080,
  70 + 0x108080,
  71 + 0x208080,
  72 + 0x9080,
  73 + 0x109080,
  74 + 0x209080,
  75 + 0x10080,
  76 + 0x110080,
  77 + 0x210080,
  78 + 0x10180,
  79 + 0x110180,
  80 + 0x210180,
  81 + 0x10081,
  82 + 0x110081,
  83 + 0x210081,
  84 + 0x10181,
  85 + 0x110181,
  86 + 0x210181,
  87 + 0x10082,
  88 + 0x110082,
  89 + 0x210082,
  90 + 0x10182,
  91 + 0x110182,
  92 + 0x210182,
  93 + 0x10083,
  94 + 0x110083,
  95 + 0x210083,
  96 + 0x10183,
  97 + 0x110183,
  98 + 0x210183,
  99 + 0x11080,
  100 + 0x111080,
  101 + 0x211080,
  102 + 0x11180,
  103 + 0x111180,
  104 + 0x211180,
  105 + 0x11081,
  106 + 0x111081,
  107 + 0x211081,
  108 + 0x11181,
  109 + 0x111181,
  110 + 0x211181,
  111 + 0x11082,
  112 + 0x111082,
  113 + 0x211082,
  114 + 0x11182,
  115 + 0x111182,
  116 + 0x211182,
  117 + 0x11083,
  118 + 0x111083,
  119 + 0x211083,
  120 + 0x11183,
  121 + 0x111183,
  122 + 0x211183,
  123 + 0x12080,
  124 + 0x112080,
  125 + 0x212080,
  126 + 0x12180,
  127 + 0x112180,
  128 + 0x212180,
  129 + 0x12081,
  130 + 0x112081,
  131 + 0x212081,
  132 + 0x12181,
  133 + 0x112181,
  134 + 0x212181,
  135 + 0x12082,
  136 + 0x112082,
  137 + 0x212082,
  138 + 0x12182,
  139 + 0x112182,
  140 + 0x212182,
  141 + 0x12083,
  142 + 0x112083,
  143 + 0x212083,
  144 + 0x12183,
  145 + 0x112183,
  146 + 0x212183,
  147 + 0x13080,
  148 + 0x113080,
  149 + 0x213080,
  150 + 0x13180,
  151 + 0x113180,
  152 + 0x213180,
  153 + 0x13081,
  154 + 0x113081,
  155 + 0x213081,
  156 + 0x13181,
  157 + 0x113181,
  158 + 0x213181,
  159 + 0x13082,
  160 + 0x113082,
  161 + 0x213082,
  162 + 0x13182,
  163 + 0x113182,
  164 + 0x213182,
  165 + 0x13083,
  166 + 0x113083,
  167 + 0x213083,
  168 + 0x13183,
  169 + 0x113183,
  170 + 0x213183,
  171 + 0x100d0,
  172 + 0x1100d0,
  173 + 0x2100d0,
  174 + 0x101d0,
  175 + 0x1101d0,
  176 + 0x2101d0,
  177 + 0x100d1,
  178 + 0x1100d1,
  179 + 0x2100d1,
  180 + 0x101d1,
  181 + 0x1101d1,
  182 + 0x2101d1,
  183 + 0x100d2,
  184 + 0x1100d2,
  185 + 0x2100d2,
  186 + 0x101d2,
  187 + 0x1101d2,
  188 + 0x2101d2,
  189 + 0x100d3,
  190 + 0x1100d3,
  191 + 0x2100d3,
  192 + 0x101d3,
  193 + 0x1101d3,
  194 + 0x2101d3,
  195 + 0x110d0,
  196 + 0x1110d0,
  197 + 0x2110d0,
  198 + 0x111d0,
  199 + 0x1111d0,
  200 + 0x2111d0,
  201 + 0x110d1,
  202 + 0x1110d1,
  203 + 0x2110d1,
  204 + 0x111d1,
  205 + 0x1111d1,
  206 + 0x2111d1,
  207 + 0x110d2,
  208 + 0x1110d2,
  209 + 0x2110d2,
  210 + 0x111d2,
  211 + 0x1111d2,
  212 + 0x2111d2,
  213 + 0x110d3,
  214 + 0x1110d3,
  215 + 0x2110d3,
  216 + 0x111d3,
  217 + 0x1111d3,
  218 + 0x2111d3,
  219 + 0x120d0,
  220 + 0x1120d0,
  221 + 0x2120d0,
  222 + 0x121d0,
  223 + 0x1121d0,
  224 + 0x2121d0,
  225 + 0x120d1,
  226 + 0x1120d1,
  227 + 0x2120d1,
  228 + 0x121d1,
  229 + 0x1121d1,
  230 + 0x2121d1,
  231 + 0x120d2,
  232 + 0x1120d2,
  233 + 0x2120d2,
  234 + 0x121d2,
  235 + 0x1121d2,
  236 + 0x2121d2,
  237 + 0x120d3,
  238 + 0x1120d3,
  239 + 0x2120d3,
  240 + 0x121d3,
  241 + 0x1121d3,
  242 + 0x2121d3,
  243 + 0x130d0,
  244 + 0x1130d0,
  245 + 0x2130d0,
  246 + 0x131d0,
  247 + 0x1131d0,
  248 + 0x2131d0,
  249 + 0x130d1,
  250 + 0x1130d1,
  251 + 0x2130d1,
  252 + 0x131d1,
  253 + 0x1131d1,
  254 + 0x2131d1,
  255 + 0x130d2,
  256 + 0x1130d2,
  257 + 0x2130d2,
  258 + 0x131d2,
  259 + 0x1131d2,
  260 + 0x2131d2,
  261 + 0x130d3,
  262 + 0x1130d3,
  263 + 0x2130d3,
  264 + 0x131d3,
  265 + 0x1131d3,
  266 + 0x2131d3,
  267 + 0x10068,
  268 + 0x10168,
  269 + 0x10268,
  270 + 0x10368,
  271 + 0x10468,
  272 + 0x10568,
  273 + 0x10668,
  274 + 0x10768,
  275 + 0x10868,
  276 + 0x10069,
  277 + 0x10169,
  278 + 0x10269,
  279 + 0x10369,
  280 + 0x10469,
  281 + 0x10569,
  282 + 0x10669,
  283 + 0x10769,
  284 + 0x10869,
  285 + 0x1006a,
  286 + 0x1016a,
  287 + 0x1026a,
  288 + 0x1036a,
  289 + 0x1046a,
  290 + 0x1056a,
  291 + 0x1066a,
  292 + 0x1076a,
  293 + 0x1086a,
  294 + 0x1006b,
  295 + 0x1016b,
  296 + 0x1026b,
  297 + 0x1036b,
  298 + 0x1046b,
  299 + 0x1056b,
  300 + 0x1066b,
  301 + 0x1076b,
  302 + 0x1086b,
  303 + 0x11068,
  304 + 0x11168,
  305 + 0x11268,
  306 + 0x11368,
  307 + 0x11468,
  308 + 0x11568,
  309 + 0x11668,
  310 + 0x11768,
  311 + 0x11868,
  312 + 0x11069,
  313 + 0x11169,
  314 + 0x11269,
  315 + 0x11369,
  316 + 0x11469,
  317 + 0x11569,
  318 + 0x11669,
  319 + 0x11769,
  320 + 0x11869,
  321 + 0x1106a,
  322 + 0x1116a,
  323 + 0x1126a,
  324 + 0x1136a,
  325 + 0x1146a,
  326 + 0x1156a,
  327 + 0x1166a,
  328 + 0x1176a,
  329 + 0x1186a,
  330 + 0x1106b,
  331 + 0x1116b,
  332 + 0x1126b,
  333 + 0x1136b,
  334 + 0x1146b,
  335 + 0x1156b,
  336 + 0x1166b,
  337 + 0x1176b,
  338 + 0x1186b,
  339 + 0x12068,
  340 + 0x12168,
  341 + 0x12268,
  342 + 0x12368,
  343 + 0x12468,
  344 + 0x12568,
  345 + 0x12668,
  346 + 0x12768,
  347 + 0x12868,
  348 + 0x12069,
  349 + 0x12169,
  350 + 0x12269,
  351 + 0x12369,
  352 + 0x12469,
  353 + 0x12569,
  354 + 0x12669,
  355 + 0x12769,
  356 + 0x12869,
  357 + 0x1206a,
  358 + 0x1216a,
  359 + 0x1226a,
  360 + 0x1236a,
  361 + 0x1246a,
  362 + 0x1256a,
  363 + 0x1266a,
  364 + 0x1276a,
  365 + 0x1286a,
  366 + 0x1206b,
  367 + 0x1216b,
  368 + 0x1226b,
  369 + 0x1236b,
  370 + 0x1246b,
  371 + 0x1256b,
  372 + 0x1266b,
  373 + 0x1276b,
  374 + 0x1286b,
  375 + 0x13068,
  376 + 0x13168,
  377 + 0x13268,
  378 + 0x13368,
  379 + 0x13468,
  380 + 0x13568,
  381 + 0x13668,
  382 + 0x13768,
  383 + 0x13868,
  384 + 0x13069,
  385 + 0x13169,
  386 + 0x13269,
  387 + 0x13369,
  388 + 0x13469,
  389 + 0x13569,
  390 + 0x13669,
  391 + 0x13769,
  392 + 0x13869,
  393 + 0x1306a,
  394 + 0x1316a,
  395 + 0x1326a,
  396 + 0x1336a,
  397 + 0x1346a,
  398 + 0x1356a,
  399 + 0x1366a,
  400 + 0x1376a,
  401 + 0x1386a,
  402 + 0x1306b,
  403 + 0x1316b,
  404 + 0x1326b,
  405 + 0x1336b,
  406 + 0x1346b,
  407 + 0x1356b,
  408 + 0x1366b,
  409 + 0x1376b,
  410 + 0x1386b,
  411 + 0x1008c,
  412 + 0x11008c,
  413 + 0x21008c,
  414 + 0x1018c,
  415 + 0x11018c,
  416 + 0x21018c,
  417 + 0x1008d,
  418 + 0x11008d,
  419 + 0x21008d,
  420 + 0x1018d,
  421 + 0x11018d,
  422 + 0x21018d,
  423 + 0x1008e,
  424 + 0x11008e,
  425 + 0x21008e,
  426 + 0x1018e,
  427 + 0x11018e,
  428 + 0x21018e,
  429 + 0x1008f,
  430 + 0x11008f,
  431 + 0x21008f,
  432 + 0x1018f,
  433 + 0x11018f,
  434 + 0x21018f,
  435 + 0x1108c,
  436 + 0x11108c,
  437 + 0x21108c,
  438 + 0x1118c,
  439 + 0x11118c,
  440 + 0x21118c,
  441 + 0x1108d,
  442 + 0x11108d,
  443 + 0x21108d,
  444 + 0x1118d,
  445 + 0x11118d,
  446 + 0x21118d,
  447 + 0x1108e,
  448 + 0x11108e,
  449 + 0x21108e,
  450 + 0x1118e,
  451 + 0x11118e,
  452 + 0x21118e,
  453 + 0x1108f,
  454 + 0x11108f,
  455 + 0x21108f,
  456 + 0x1118f,
  457 + 0x11118f,
  458 + 0x21118f,
  459 + 0x1208c,
  460 + 0x11208c,
  461 + 0x21208c,
  462 + 0x1218c,
  463 + 0x11218c,
  464 + 0x21218c,
  465 + 0x1208d,
  466 + 0x11208d,
  467 + 0x21208d,
  468 + 0x1218d,
  469 + 0x11218d,
  470 + 0x21218d,
  471 + 0x1208e,
  472 + 0x11208e,
  473 + 0x21208e,
  474 + 0x1218e,
  475 + 0x11218e,
  476 + 0x21218e,
  477 + 0x1208f,
  478 + 0x11208f,
  479 + 0x21208f,
  480 + 0x1218f,
  481 + 0x11218f,
  482 + 0x21218f,
  483 + 0x1308c,
  484 + 0x11308c,
  485 + 0x21308c,
  486 + 0x1318c,
  487 + 0x11318c,
  488 + 0x21318c,
  489 + 0x1308d,
  490 + 0x11308d,
  491 + 0x21308d,
  492 + 0x1318d,
  493 + 0x11318d,
  494 + 0x21318d,
  495 + 0x1308e,
  496 + 0x11308e,
  497 + 0x21308e,
  498 + 0x1318e,
  499 + 0x11318e,
  500 + 0x21318e,
  501 + 0x1308f,
  502 + 0x11308f,
  503 + 0x21308f,
  504 + 0x1318f,
  505 + 0x11318f,
  506 + 0x21318f,
  507 + 0x100c0,
  508 + 0x1100c0,
  509 + 0x2100c0,
  510 + 0x101c0,
  511 + 0x1101c0,
  512 + 0x2101c0,
  513 + 0x102c0,
  514 + 0x1102c0,
  515 + 0x2102c0,
  516 + 0x103c0,
  517 + 0x1103c0,
  518 + 0x2103c0,
  519 + 0x104c0,
  520 + 0x1104c0,
  521 + 0x2104c0,
  522 + 0x105c0,
  523 + 0x1105c0,
  524 + 0x2105c0,
  525 + 0x106c0,
  526 + 0x1106c0,
  527 + 0x2106c0,
  528 + 0x107c0,
  529 + 0x1107c0,
  530 + 0x2107c0,
  531 + 0x108c0,
  532 + 0x1108c0,
  533 + 0x2108c0,
  534 + 0x100c1,
  535 + 0x1100c1,
  536 + 0x2100c1,
  537 + 0x101c1,
  538 + 0x1101c1,
  539 + 0x2101c1,
  540 + 0x102c1,
  541 + 0x1102c1,
  542 + 0x2102c1,
  543 + 0x103c1,
  544 + 0x1103c1,
  545 + 0x2103c1,
  546 + 0x104c1,
  547 + 0x1104c1,
  548 + 0x2104c1,
  549 + 0x105c1,
  550 + 0x1105c1,
  551 + 0x2105c1,
  552 + 0x106c1,
  553 + 0x1106c1,
  554 + 0x2106c1,
  555 + 0x107c1,
  556 + 0x1107c1,
  557 + 0x2107c1,
  558 + 0x108c1,
  559 + 0x1108c1,
  560 + 0x2108c1,
  561 + 0x100c2,
  562 + 0x1100c2,
  563 + 0x2100c2,
  564 + 0x101c2,
  565 + 0x1101c2,
  566 + 0x2101c2,
  567 + 0x102c2,
  568 + 0x1102c2,
  569 + 0x2102c2,
  570 + 0x103c2,
  571 + 0x1103c2,
  572 + 0x2103c2,
  573 + 0x104c2,
  574 + 0x1104c2,
  575 + 0x2104c2,
  576 + 0x105c2,
  577 + 0x1105c2,
  578 + 0x2105c2,
  579 + 0x106c2,
  580 + 0x1106c2,
  581 + 0x2106c2,
  582 + 0x107c2,
  583 + 0x1107c2,
  584 + 0x2107c2,
  585 + 0x108c2,
  586 + 0x1108c2,
  587 + 0x2108c2,
  588 + 0x100c3,
  589 + 0x1100c3,
  590 + 0x2100c3,
  591 + 0x101c3,
  592 + 0x1101c3,
  593 + 0x2101c3,
  594 + 0x102c3,
  595 + 0x1102c3,
  596 + 0x2102c3,
  597 + 0x103c3,
  598 + 0x1103c3,
  599 + 0x2103c3,
  600 + 0x104c3,
  601 + 0x1104c3,
  602 + 0x2104c3,
  603 + 0x105c3,
  604 + 0x1105c3,
  605 + 0x2105c3,
  606 + 0x106c3,
  607 + 0x1106c3,
  608 + 0x2106c3,
  609 + 0x107c3,
  610 + 0x1107c3,
  611 + 0x2107c3,
  612 + 0x108c3,
  613 + 0x1108c3,
  614 + 0x2108c3,
  615 + 0x110c0,
  616 + 0x1110c0,
  617 + 0x2110c0,
  618 + 0x111c0,
  619 + 0x1111c0,
  620 + 0x2111c0,
  621 + 0x112c0,
  622 + 0x1112c0,
  623 + 0x2112c0,
  624 + 0x113c0,
  625 + 0x1113c0,
  626 + 0x2113c0,
  627 + 0x114c0,
  628 + 0x1114c0,
  629 + 0x2114c0,
  630 + 0x115c0,
  631 + 0x1115c0,
  632 + 0x2115c0,
  633 + 0x116c0,
  634 + 0x1116c0,
  635 + 0x2116c0,
  636 + 0x117c0,
  637 + 0x1117c0,
  638 + 0x2117c0,
  639 + 0x118c0,
  640 + 0x1118c0,
  641 + 0x2118c0,
  642 + 0x110c1,
  643 + 0x1110c1,
  644 + 0x2110c1,
  645 + 0x111c1,
  646 + 0x1111c1,
  647 + 0x2111c1,
  648 + 0x112c1,
  649 + 0x1112c1,
  650 + 0x2112c1,
  651 + 0x113c1,
  652 + 0x1113c1,
  653 + 0x2113c1,
  654 + 0x114c1,
  655 + 0x1114c1,
  656 + 0x2114c1,
  657 + 0x115c1,
  658 + 0x1115c1,
  659 + 0x2115c1,
  660 + 0x116c1,
  661 + 0x1116c1,
  662 + 0x2116c1,
  663 + 0x117c1,
  664 + 0x1117c1,
  665 + 0x2117c1,
  666 + 0x118c1,
  667 + 0x1118c1,
  668 + 0x2118c1,
  669 + 0x110c2,
  670 + 0x1110c2,
  671 + 0x2110c2,
  672 + 0x111c2,
  673 + 0x1111c2,
  674 + 0x2111c2,
  675 + 0x112c2,
  676 + 0x1112c2,
  677 + 0x2112c2,
  678 + 0x113c2,
  679 + 0x1113c2,
  680 + 0x2113c2,
  681 + 0x114c2,
  682 + 0x1114c2,
  683 + 0x2114c2,
  684 + 0x115c2,
  685 + 0x1115c2,
  686 + 0x2115c2,
  687 + 0x116c2,
  688 + 0x1116c2,
  689 + 0x2116c2,
  690 + 0x117c2,
  691 + 0x1117c2,
  692 + 0x2117c2,
  693 + 0x118c2,
  694 + 0x1118c2,
  695 + 0x2118c2,
  696 + 0x110c3,
  697 + 0x1110c3,
  698 + 0x2110c3,
  699 + 0x111c3,
  700 + 0x1111c3,
  701 + 0x2111c3,
  702 + 0x112c3,
  703 + 0x1112c3,
  704 + 0x2112c3,
  705 + 0x113c3,
  706 + 0x1113c3,
  707 + 0x2113c3,
  708 + 0x114c3,
  709 + 0x1114c3,
  710 + 0x2114c3,
  711 + 0x115c3,
  712 + 0x1115c3,
  713 + 0x2115c3,
  714 + 0x116c3,
  715 + 0x1116c3,
  716 + 0x2116c3,
  717 + 0x117c3,
  718 + 0x1117c3,
  719 + 0x2117c3,
  720 + 0x118c3,
  721 + 0x1118c3,
  722 + 0x2118c3,
  723 + 0x120c0,
  724 + 0x1120c0,
  725 + 0x2120c0,
  726 + 0x121c0,
  727 + 0x1121c0,
  728 + 0x2121c0,
  729 + 0x122c0,
  730 + 0x1122c0,
  731 + 0x2122c0,
  732 + 0x123c0,
  733 + 0x1123c0,
  734 + 0x2123c0,
  735 + 0x124c0,
  736 + 0x1124c0,
  737 + 0x2124c0,
  738 + 0x125c0,
  739 + 0x1125c0,
  740 + 0x2125c0,
  741 + 0x126c0,
  742 + 0x1126c0,
  743 + 0x2126c0,
  744 + 0x127c0,
  745 + 0x1127c0,
  746 + 0x2127c0,
  747 + 0x128c0,
  748 + 0x1128c0,
  749 + 0x2128c0,
  750 + 0x120c1,
  751 + 0x1120c1,
  752 + 0x2120c1,
  753 + 0x121c1,
  754 + 0x1121c1,
  755 + 0x2121c1,
  756 + 0x122c1,
  757 + 0x1122c1,
  758 + 0x2122c1,
  759 + 0x123c1,
  760 + 0x1123c1,
  761 + 0x2123c1,
  762 + 0x124c1,
  763 + 0x1124c1,
  764 + 0x2124c1,
  765 + 0x125c1,
  766 + 0x1125c1,
  767 + 0x2125c1,
  768 + 0x126c1,
  769 + 0x1126c1,
  770 + 0x2126c1,
  771 + 0x127c1,
  772 + 0x1127c1,
  773 + 0x2127c1,
  774 + 0x128c1,
  775 + 0x1128c1,
  776 + 0x2128c1,
  777 + 0x120c2,
  778 + 0x1120c2,
  779 + 0x2120c2,
  780 + 0x121c2,
  781 + 0x1121c2,
  782 + 0x2121c2,
  783 + 0x122c2,
  784 + 0x1122c2,
  785 + 0x2122c2,
  786 + 0x123c2,
  787 + 0x1123c2,
  788 + 0x2123c2,
  789 + 0x124c2,
  790 + 0x1124c2,
  791 + 0x2124c2,
  792 + 0x125c2,
  793 + 0x1125c2,
  794 + 0x2125c2,
  795 + 0x126c2,
  796 + 0x1126c2,
  797 + 0x2126c2,
  798 + 0x127c2,
  799 + 0x1127c2,
  800 + 0x2127c2,
  801 + 0x128c2,
  802 + 0x1128c2,
  803 + 0x2128c2,
  804 + 0x120c3,
  805 + 0x1120c3,
  806 + 0x2120c3,
  807 + 0x121c3,
  808 + 0x1121c3,
  809 + 0x2121c3,
  810 + 0x122c3,
  811 + 0x1122c3,
  812 + 0x2122c3,
  813 + 0x123c3,
  814 + 0x1123c3,
  815 + 0x2123c3,
  816 + 0x124c3,
  817 + 0x1124c3,
  818 + 0x2124c3,
  819 + 0x125c3,
  820 + 0x1125c3,
  821 + 0x2125c3,
  822 + 0x126c3,
  823 + 0x1126c3,
  824 + 0x2126c3,
  825 + 0x127c3,
  826 + 0x1127c3,
  827 + 0x2127c3,
  828 + 0x128c3,
  829 + 0x1128c3,
  830 + 0x2128c3,
  831 + 0x130c0,
  832 + 0x1130c0,
  833 + 0x2130c0,
  834 + 0x131c0,
  835 + 0x1131c0,
  836 + 0x2131c0,
  837 + 0x132c0,
  838 + 0x1132c0,
  839 + 0x2132c0,
  840 + 0x133c0,
  841 + 0x1133c0,
  842 + 0x2133c0,
  843 + 0x134c0,
  844 + 0x1134c0,
  845 + 0x2134c0,
  846 + 0x135c0,
  847 + 0x1135c0,
  848 + 0x2135c0,
  849 + 0x136c0,
  850 + 0x1136c0,
  851 + 0x2136c0,
  852 + 0x137c0,
  853 + 0x1137c0,
  854 + 0x2137c0,
  855 + 0x138c0,
  856 + 0x1138c0,
  857 + 0x2138c0,
  858 + 0x130c1,
  859 + 0x1130c1,
  860 + 0x2130c1,
  861 + 0x131c1,
  862 + 0x1131c1,
  863 + 0x2131c1,
  864 + 0x132c1,
  865 + 0x1132c1,
  866 + 0x2132c1,
  867 + 0x133c1,
  868 + 0x1133c1,
  869 + 0x2133c1,
  870 + 0x134c1,
  871 + 0x1134c1,
  872 + 0x2134c1,
  873 + 0x135c1,
  874 + 0x1135c1,
  875 + 0x2135c1,
  876 + 0x136c1,
  877 + 0x1136c1,
  878 + 0x2136c1,
  879 + 0x137c1,
  880 + 0x1137c1,
  881 + 0x2137c1,
  882 + 0x138c1,
  883 + 0x1138c1,
  884 + 0x2138c1,
  885 + 0x130c2,
  886 + 0x1130c2,
  887 + 0x2130c2,
  888 + 0x131c2,
  889 + 0x1131c2,
  890 + 0x2131c2,
  891 + 0x132c2,
  892 + 0x1132c2,
  893 + 0x2132c2,
  894 + 0x133c2,
  895 + 0x1133c2,
  896 + 0x2133c2,
  897 + 0x134c2,
  898 + 0x1134c2,
  899 + 0x2134c2,
  900 + 0x135c2,
  901 + 0x1135c2,
  902 + 0x2135c2,
  903 + 0x136c2,
  904 + 0x1136c2,
  905 + 0x2136c2,
  906 + 0x137c2,
  907 + 0x1137c2,
  908 + 0x2137c2,
  909 + 0x138c2,
  910 + 0x1138c2,
  911 + 0x2138c2,
  912 + 0x130c3,
  913 + 0x1130c3,
  914 + 0x2130c3,
  915 + 0x131c3,
  916 + 0x1131c3,
  917 + 0x2131c3,
  918 + 0x132c3,
  919 + 0x1132c3,
  920 + 0x2132c3,
  921 + 0x133c3,
  922 + 0x1133c3,
  923 + 0x2133c3,
  924 + 0x134c3,
  925 + 0x1134c3,
  926 + 0x2134c3,
  927 + 0x135c3,
  928 + 0x1135c3,
  929 + 0x2135c3,
  930 + 0x136c3,
  931 + 0x1136c3,
  932 + 0x2136c3,
  933 + 0x137c3,
  934 + 0x1137c3,
  935 + 0x2137c3,
  936 + 0x138c3,
  937 + 0x1138c3,
  938 + 0x2138c3,
  939 + 0x10020,
  940 + 0x110020,
  941 + 0x210020,
  942 + 0x11020,
  943 + 0x111020,
  944 + 0x211020,
  945 + 0x12020,
  946 + 0x112020,
  947 + 0x212020,
  948 + 0x13020,
  949 + 0x113020,
  950 + 0x213020,
  951 + 0x2007d,
  952 + 0x12007d,
  953 + 0x22007d,
  954 + 0x10040,
  955 + 0x10140,
  956 + 0x10240,
  957 + 0x10340,
  958 + 0x10440,
  959 + 0x10540,
  960 + 0x10640,
  961 + 0x10740,
  962 + 0x10840,
  963 + 0x10030,
  964 + 0x10130,
  965 + 0x10230,
  966 + 0x10330,
  967 + 0x10430,
  968 + 0x10530,
  969 + 0x10630,
  970 + 0x10730,
  971 + 0x10830,
  972 + 0x11040,
  973 + 0x11140,
  974 + 0x11240,
  975 + 0x11340,
  976 + 0x11440,
  977 + 0x11540,
  978 + 0x11640,
  979 + 0x11740,
  980 + 0x11840,
  981 + 0x11030,
  982 + 0x11130,
  983 + 0x11230,
  984 + 0x11330,
  985 + 0x11430,
  986 + 0x11530,
  987 + 0x11630,
  988 + 0x11730,
  989 + 0x11830,
  990 + 0x12040,
  991 + 0x12140,
  992 + 0x12240,
  993 + 0x12340,
  994 + 0x12440,
  995 + 0x12540,
  996 + 0x12640,
  997 + 0x12740,
  998 + 0x12840,
  999 + 0x12030,
  1000 + 0x12130,
  1001 + 0x12230,
  1002 + 0x12330,
  1003 + 0x12430,
  1004 + 0x12530,
  1005 + 0x12630,
  1006 + 0x12730,
  1007 + 0x12830,
  1008 + 0x13040,
  1009 + 0x13140,
  1010 + 0x13240,
  1011 + 0x13340,
  1012 + 0x13440,
  1013 + 0x13540,
  1014 + 0x13640,
  1015 + 0x13740,
  1016 + 0x13840,
  1017 + 0x13030,
  1018 + 0x13130,
  1019 + 0x13230,
  1020 + 0x13330,
  1021 + 0x13430,
  1022 + 0x13530,
  1023 + 0x13630,
  1024 + 0x13730,
  1025 + 0x13830,
  1026 +#endif
  1027 + 0
  1028 +};
  1029 +
  1030 +void save_1d2d_trained_csr_ddr4_p012(unsigned int addr)
  1031 +{
  1032 + unsigned int i;
  1033 +
  1034 + dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  1035 + dwc_ddrphy_apb_wr(0xc0080, 0x3); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
  1036 + for (i = 0; save_csr[i] != 0; i++) {
  1037 + reg32_write(addr + (i << 2), dwc_ddrphy_apb_rd(save_csr[i]));
  1038 + }
  1039 + dwc_ddrphy_apb_wr(0xc0080, 0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
  1040 + dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
  1041 +
  1042 + ddr_dbg("save 1d2d training registers done \n");
  1043 +}
  1044 +#endif
board/freescale/imx8mm_evk/ddr/helper.c
Diff comments   View file @ 6a8f558
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <spl.h>
  9 +#include <asm/io.h>
  10 +#include <errno.h>
  11 +#include <asm/io.h>
  12 +#include <asm/arch/ddr.h>
  13 +#include <asm/sections.h>
  14 +
  15 +#include "ddr.h"
  16 +
  17 +DECLARE_GLOBAL_DATA_PTR;
  18 +
  19 +#define IMEM_LEN 32768
  20 +#define DMEM_LEN 16384
  21 +#define IMEM_2D_OFFSET 49152
  22 +
  23 +#define IMEM_OFFSET_ADDR 0x00050000
  24 +#define DMEM_OFFSET_ADDR 0x00054000
  25 +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
  26 +
  27 +/* We need PHY iMEM PHY is 32KB padded */
  28 +void ddr_load_train_code(enum fw_type type)
  29 +{
  30 + u32 tmp32, i;
  31 + u32 error = 0;
  32 + unsigned long pr_to32, pr_from32;
  33 + unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
  34 + unsigned long imem_start = (unsigned long)&_end + fw_offset;
  35 + unsigned long dmem_start = imem_start + IMEM_LEN;
  36 +
  37 + pr_from32 = imem_start;
  38 + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
  39 + for (i = 0x0; i < IMEM_LEN; ) {
  40 + tmp32 = readl(pr_from32);
  41 + writew(tmp32 & 0x0000ffff, pr_to32);
  42 + pr_to32 += 4;
  43 + writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
  44 + pr_to32 += 4;
  45 + pr_from32 += 4;
  46 + i += 4;
  47 + }
  48 +
  49 + pr_from32 = dmem_start;
  50 + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
  51 + for (i = 0x0; i < DMEM_LEN;) {
  52 + tmp32 = readl(pr_from32);
  53 + writew(tmp32 & 0x0000ffff, pr_to32);
  54 + pr_to32 += 4;
  55 + writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
  56 + pr_to32 += 4;
  57 + pr_from32 += 4;
  58 + i += 4;
  59 + }
  60 +
  61 + printf("check ddr4_pmu_train_imem code\n");
  62 + pr_from32 = imem_start;
  63 + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
  64 + for (i = 0x0; i < IMEM_LEN;) {
  65 + tmp32 = (readw(pr_to32) & 0x0000ffff);
  66 + pr_to32 += 4;
  67 + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
  68 +
  69 + if (tmp32 != readl(pr_from32)) {
  70 + printf("%lx %lx\n", pr_from32, pr_to32);
  71 + error++;
  72 + }
  73 + pr_from32 += 4;
  74 + pr_to32 += 4;
  75 + i += 4;
  76 + }
  77 + if (error)
  78 + printf("check ddr4_pmu_train_imem code fail=%d\n", error);
  79 + else
  80 + printf("check ddr4_pmu_train_imem code pass\n");
  81 +
  82 + printf("check ddr4_pmu_train_dmem code\n");
  83 + pr_from32 = dmem_start;
  84 + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
  85 + for (i = 0x0; i < DMEM_LEN;) {
  86 + tmp32 = (readw(pr_to32) & 0x0000ffff);
  87 + pr_to32 += 4;
  88 + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
  89 + if (tmp32 != readl(pr_from32)) {
  90 + printf("%lx %lx\n", pr_from32, pr_to32);
  91 + error++;
  92 + }
  93 + pr_from32 += 4;
  94 + pr_to32 += 4;
  95 + i += 4;
  96 + }
  97 +
  98 + if (error)
  99 + printf("check ddr4_pmu_train_dmem code fail=%d", error);
  100 + else
  101 + printf("check ddr4_pmu_train_dmem code pass\n");
  102 +}
board/freescale/imx8mm_evk/ddr/wait_ddrphy_training_complete.c
Diff comments   View file @ 6a8f558
  1 +/*
  2 + * Copyright 2017 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +#include <common.h>
  7 +#include <errno.h>
  8 +#include <asm/io.h>
  9 +#include <asm/arch/ddr.h>
  10 +#include <asm/arch/clock.h>
  11 +#include "ddr.h"
  12 +
  13 +static inline void poll_pmu_message_ready(void)
  14 +{
  15 + unsigned int reg;
  16 +
  17 + do {
  18 + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
  19 + } while (reg & 0x1);
  20 +}
  21 +
  22 +static inline void ack_pmu_message_recieve(void)
  23 +{
  24 + unsigned int reg;
  25 +
  26 + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031, 0x0);
  27 +
  28 + do {
  29 + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
  30 + } while (!(reg & 0x1));
  31 +
  32 + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031, 0x1);
  33 +}
  34 +
  35 +static inline unsigned int get_mail(void)
  36 +{
  37 + unsigned int reg;
  38 +
  39 + poll_pmu_message_ready();
  40 +
  41 + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
  42 +
  43 + ack_pmu_message_recieve();
  44 +
  45 + return reg;
  46 +}
  47 +
  48 +static inline unsigned int get_stream_message(void)
  49 +{
  50 + unsigned int reg, reg2;
  51 +
  52 + poll_pmu_message_ready();
  53 +
  54 + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
  55 +
  56 + reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034);
  57 +
  58 + reg2 = (reg2 << 16) | reg;
  59 +
  60 + ack_pmu_message_recieve();
  61 +
  62 + return reg2;
  63 +}
  64 +
  65 +static inline void decode_major_message(unsigned int mail)
  66 +{
  67 + ddr_dbg("[PMU Major message = 0x%08x]\n", mail);
  68 +}
  69 +
  70 +static inline void decode_streaming_message(void)
  71 +{
  72 + unsigned int string_index, arg __maybe_unused;
  73 + int i = 0;
  74 +
  75 + string_index = get_stream_message();
  76 + ddr_dbg(" PMU String index = 0x%08x\n", string_index);
  77 + while (i < (string_index & 0xffff)) {
  78 + arg = get_stream_message();
  79 + ddr_dbg(" arg[%d] = 0x%08x\n", i, arg);
  80 + i++;
  81 + }
  82 +
  83 + ddr_dbg("\n");
  84 +}
  85 +
  86 +void wait_ddrphy_training_complete(void)
  87 +{
  88 + unsigned int mail;
  89 + while (1) {
  90 + mail = get_mail();
  91 + decode_major_message(mail);
  92 + if (mail == 0x08) {
  93 + decode_streaming_message();
  94 + } else if (mail == 0x07) {
  95 + printf("Training PASS\n");
  96 + break;
  97 + } else if (mail == 0xff) {
  98 + printf("Training FAILED\n");
  99 + break;
  100 + }
  101 + }
  102 +}
board/freescale/imx8mm_evk/imx8mm_evk.c
Diff comments   View file @ 6a8f558
... ... @@ -123,7 +123,6 @@
123 123 static void setup_gpmi_nand(void)
124 124 {
125 125 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
126   - mxs_dma_init();
127 126 }
128 127 #endif
129 128  
... ... @@ -137,6 +136,10 @@
137 136  
138 137 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
139 138  
  139 +#ifdef CONFIG_NAND_MXS
  140 + setup_gpmi_nand(); /* SPL will call the board_early_init_f */
  141 +#endif
  142 +
140 143 return 0;
141 144 }
142 145  
... ... @@ -405,9 +408,6 @@
405 408 board_qspi_init();
406 409 #endif
407 410  
408   -#ifdef CONFIG_NAND_MXS
409   - setup_gpmi_nand(); /* SPL will call the board_early_init_f */
410   -#endif
411 411 return 0;
412 412 }
413 413  
board/freescale/imx8mm_evk/spl.c
Diff comments   View file @ 6a8f558
... ... @@ -19,14 +19,22 @@
19 19 #include <asm/mach-imx/mxc_i2c.h>
20 20 #include <fsl_esdhc.h>
21 21 #include <mmc.h>
  22 +#ifdef CONFIG_IMX8M_LPDDR4
22 23 #include <asm/arch/imx8m_ddr.h>
  24 +#else
  25 +#include "ddr/ddr.h"
  26 +#endif
23 27  
24 28 DECLARE_GLOBAL_DATA_PTR;
25 29  
26 30 void spl_dram_init(void)
27 31 {
  32 +#ifdef CONFIG_IMX8M_LPDDR4
28 33 /* ddr train */
29 34 ddr_init(&lpddr4_timing);
  35 +#else
  36 + ddr_init();
  37 +#endif
30 38 }
31 39  
32 40 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
... ... @@ -180,6 +188,11 @@
180 188  
181 189 /* increase VDD_DRAM to 0.9v for 3Ghz DDR */
182 190 pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x2);
  191 +
  192 +#ifndef CONFIG_IMX8M_LPDDR4
  193 + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
  194 + pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28);
  195 +#endif
183 196  
184 197 /* lock the PMIC regs */
185 198 pmic_reg_write(p, BD71837_REGLOCK, 0x11);
configs/imx8mm_ddr4_evk_defconfig
Diff comments   View file @ 6a8f558
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_IMX8M=y
  3 +CONFIG_SYS_TEXT_BASE=0x40200000
  4 +CONFIG_SYS_MALLOC_F_LEN=0x2000
  5 +CONFIG_USB_TCPC=y
  6 +CONFIG_TARGET_IMX8MM_DDR4_EVK=y
  7 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000"
  8 +CONFIG_FIT=y
  9 +CONFIG_SPL_LOAD_FIT=y
  10 +CONFIG_ARCH_MISC_INIT=y
  11 +CONFIG_SPL=y
  12 +CONFIG_SPL_BOARD_INIT=y
  13 +CONFIG_SPL_MMC_SUPPORT=y
  14 +CONFIG_HUSH_PARSER=y
  15 +CONFIG_OF_LIBFDT=y
  16 +CONFIG_FS_FAT=y
  17 +CONFIG_CMD_EXT2=y
  18 +CONFIG_CMD_EXT4=y
  19 +CONFIG_CMD_EXT4_WRITE=y
  20 +CONFIG_CMD_FAT=y
  21 +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-ddr4-evk"
  22 +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-ddr4-evk.dtb"
  23 +CONFIG_ENV_IS_IN_MMC=y
  24 +CONFIG_CMD_I2C=y
  25 +CONFIG_CMD_GPIO=y
  26 +CONFIG_CMD_CACHE=y
  27 +CONFIG_CMD_REGULATOR=y
  28 +CONFIG_CMD_MEMTEST=y
  29 +CONFIG_OF_CONTROL=y
  30 +CONFIG_FASTBOOT=y
  31 +CONFIG_USB_FUNCTION_FASTBOOT=y
  32 +CONFIG_CMD_FASTBOOT=y
  33 +CONFIG_ANDROID_BOOT_IMAGE=y
  34 +CONFIG_FSL_FASTBOOT=y
  35 +CONFIG_FASTBOOT_BUF_ADDR=0x42800000
  36 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000
  37 +CONFIG_FASTBOOT_FLASH=y
  38 +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
  39 +
  40 +CONFIG_DM_GPIO=y
  41 +CONFIG_DM_I2C=y
  42 +CONFIG_SYS_I2C_MXC=y
  43 +CONFIG_DM_MMC=y
  44 +# CONFIG_DM_PMIC=y
  45 +CONFIG_EFI_PARTITION=y
  46 +CONFIG_DM_ETH=y
  47 +CONFIG_PINCTRL=y
  48 +CONFIG_PINCTRL_IMX8M=y
  49 +CONFIG_DM_REGULATOR=y
  50 +CONFIG_DM_REGULATOR_FIXED=y
  51 +CONFIG_DM_REGULATOR_GPIO=y
  52 +CONFIG_NXP_TMU=y
  53 +CONFIG_DM_THERMAL=y
  54 +CONFIG_USB=y
  55 +CONFIG_USB_GADGET=y
  56 +CONFIG_DM_USB=y
  57 +CONFIG_USB_EHCI_HCD=y
  58 +
  59 +CONFIG_SPL_USB_HOST_SUPPORT=y
  60 +CONFIG_SPL_USB_GADGET_SUPPORT=y
  61 +CONFIG_SPL_USB_SDP_SUPPORT=y
  62 +CONFIG_SDP_LOADADDR=0x40400000
  63 +CONFIG_USB_GADGET_MANUFACTURER="FSL"
  64 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
  65 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
  66 +
  67 +CONFIG_VIDEO=y
  68 +CONFIG_IMX_SEC_MIPI_DSI=y
  69 +
  70 +CONFIG_CMD_NAND=y
  71 +CONFIG_CMD_UBI=y
configs/imx8mm_evk_defconfig
Diff comments   View file @ 6a8f558
... ... @@ -19,6 +19,7 @@
19 19 CONFIG_CMD_EXT4_WRITE=y
20 20 CONFIG_CMD_FAT=y
21 21 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk"
  22 +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb"
22 23 CONFIG_ENV_IS_IN_MMC=y
23 24 CONFIG_CMD_SF=y
24 25 CONFIG_CMD_I2C=y
include/configs/imx8mm_evk.h
Diff comments   View file @ 6a8f558
... ... @@ -127,7 +127,7 @@
127 127 "fdt_addr=0x43000000\0" \
128 128 "fdt_high=0xffffffffffffffff\0" \
129 129 "boot_fdt=try\0" \
130   - "fdt_file=fsl-imx8mm-evk.dtb\0" \" \
  130 + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \" \
131 131 "initrd_addr=0x43800000\0" \
132 132 "initrd_high=0xffffffffffffffff\0" \
133 133 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
134 134  
... ... @@ -244,7 +244,11 @@
244 244 #define CONFIG_FSL_ESDHC
245 245 #define CONFIG_FSL_USDHC
246 246  
  247 +#ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK
  248 +#define CONFIG_SYS_FSL_USDHC_NUM 1
  249 +#else
247 250 #define CONFIG_SYS_FSL_USDHC_NUM 2
  251 +#endif
248 252 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
249 253  
250 254 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
... ... @@ -279,7 +283,8 @@
279 283 #endif
280 284 #endif
281 285  
282   -#ifdef CONFIG_NAND_MXS
  286 +#ifdef CONFIG_CMD_NAND
  287 +#define CONFIG_NAND_MXS
283 288 #define CONFIG_CMD_NAND_TRIMFFS
284 289  
285 290 /* NAND stuff */
286 291  
... ... @@ -292,7 +297,13 @@
292 297 #define CONFIG_APBH_DMA
293 298 #define CONFIG_APBH_DMA_BURST
294 299 #define CONFIG_APBH_DMA_BURST8
  300 +
  301 +#ifdef CONFIG_CMD_UBI
  302 +#define CONFIG_MTD_PARTITIONS
  303 +#define CONFIG_MTD_DEVICE
295 304 #endif
  305 +#endif /* CONFIG_CMD_NAND */
  306 +
296 307  
297 308 #define CONFIG_MXC_GPIO
298 309