drivers: mmc: omap_hsmmc: Fix IO Buffer on OMAP36xx

On the OMAP36xx/37xx the CONTROL_WKUP_CTRL register has a field (bit 6) named GPIO_IO_PWRDNZ. If 0, the IO buffers which are related to GPIO_126, 127 and 129 are disabled. Some boards may need this for MMC. After the PBIAS is configured, this bit should be set high to enable these GPIO pins. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>

drivers: mmc: omap_hsmmc: Fix IO Buffer on OMAP36xx
On the OMAP36xx/37xx the CONTROL_WKUP_CTRL register has a field (bit 6) named GPIO_IO_PWRDNZ. If 0, the IO buffers which are related to GPIO_126, 127 and 129 are disabled. Some boards may need this for MMC. After the PBIAS is configured, this bit should be set high to enable these GPIO pins. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Adam Ford · Jaehoon Chung · Eric Lee · Eric Lee · Eric Lee · Eric Lee
1 parent d14f1d511a
Showing 3 changed files with 31 additions and 0 deletions Side-by-side Diff
configs/omap3_logic_defconfig
drivers/mmc/Kconfig
drivers/mmc/omap_hsmmc.c
@@ -33,6 +33,7 @@
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_OMAP36XX_PINS=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
@@ -131,6 +131,18 @@
  
 	  If unsure, say N.
  
+config MMC_OMAP36XX_PINS
+	bool "Enable MMC1 on OMAP36xx/37xx"
+	depends on OMAP34XX && MMC_OMAP_HS
+	help
+	  This enables extended-drain in the MMC/SD/SDIO1I/O and
+	  GPIO-associated I/O cells (gpio_126, gpio_127, and gpio_129)
+	  specific to the OMAP36xx/37xx using MMC1
+
+	  If you have a controller with this interface, say Y here.
+
+	  If unsure, say N.
+
 config SH_SDHI
 	bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
 	depends on RMOBILE
@@ -38,6 +38,7 @@
 #include <asm/arch/sys_proto.h>
 #endif
 #include <dm.h>
+#include <asm/arch-omap3/mux.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
@@ -102,6 +103,9 @@
 	t2_t *t2_base = (t2_t *)T2_BASE;
 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 	u32 pbias_lite;
+#ifdef CONFIG_MMC_OMAP36XX_PINS
+	u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
+#endif
  
 	pbias_lite = readl(&t2_base->pbias_lite);
 	pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
  
@@ -109,12 +113,26 @@
 	/* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 	pbias_lite &= ~PBIASLITEVMODE0;
 #endif
+#ifdef CONFIG_MMC_OMAP36XX_PINS
+	if (get_cpu_family() == CPU_OMAP36XX) {
+		/* Disable extended drain IO before changing PBIAS */
+		wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
+		writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
+	}
+#endif
 	writel(pbias_lite, &t2_base->pbias_lite);
  
 	writel(pbias_lite | PBIASLITEPWRDNZ1 |
 		PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 		&t2_base->pbias_lite);
  
+#ifdef CONFIG_MMC_OMAP36XX_PINS
+	if (get_cpu_family() == CPU_OMAP36XX)
+		/* Enable extended drain IO after changing PBIAS */
+		writel(wkup_ctrl |
+				OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
+				OMAP34XX_CTRL_WKUP_CTRL);
+#endif
 	writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 		&t2_base->devconf0);
...	...	@@ -33,6 +33,7 @@
33	33	CONFIG_ISO_PARTITION=y
34	34	CONFIG_EFI_PARTITION=y
35	35	CONFIG_MMC_OMAP_HS=y
	36	+CONFIG_MMC_OMAP36XX_PINS=y
36	37	CONFIG_SYS_NS16550=y
37	38	CONFIG_USB=y
38	39	CONFIG_USB_MUSB_GADGET=y
...	...	@@ -131,6 +131,18 @@
131	131
132	132	If unsure, say N.
133	133
	134	+config MMC_OMAP36XX_PINS
	135	+ bool "Enable MMC1 on OMAP36xx/37xx"
	136	+ depends on OMAP34XX && MMC_OMAP_HS
	137	+ help
	138	+ This enables extended-drain in the MMC/SD/SDIO1I/O and
	139	+ GPIO-associated I/O cells (gpio_126, gpio_127, and gpio_129)
	140	+ specific to the OMAP36xx/37xx using MMC1
	141	+
	142	+ If you have a controller with this interface, say Y here.
	143	+
	144	+ If unsure, say N.
	145	+
134	146	config SH_SDHI
135	147	bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
136	148	depends on RMOBILE
...	...	@@ -38,6 +38,7 @@
38	38	#include <asm/arch/sys_proto.h>
39	39	#endif
40	40	#include <dm.h>
	41	+#include <asm/arch-omap3/mux.h>
41	42
42	43	DECLARE_GLOBAL_DATA_PTR;
43	44
...	...	@@ -102,6 +103,9 @@
102	103	t2_t t2_base = (t2_t )T2_BASE;
103	104	struct prcm prcm_base = (struct prcm )PRCM_BASE;
104	105	u32 pbias_lite;
	106	+#ifdef CONFIG_MMC_OMAP36XX_PINS
	107	+ u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
	108	+#endif
105	109
106	110	pbias_lite = readl(&t2_base->pbias_lite);
107	111	pbias_lite &= ~(PBIASLITEPWRDNZ1 \| PBIASLITEPWRDNZ0);
108	112
...	...	@@ -109,12 +113,26 @@
109	113	/* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
110	114	pbias_lite &= ~PBIASLITEVMODE0;
111	115	#endif
	116	+#ifdef CONFIG_MMC_OMAP36XX_PINS
	117	+ if (get_cpu_family() == CPU_OMAP36XX) {
	118	+ /* Disable extended drain IO before changing PBIAS */
	119	+ wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
	120	+ writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
	121	+ }
	122	+#endif
112	123	writel(pbias_lite, &t2_base->pbias_lite);
113	124
114	125	writel(pbias_lite \| PBIASLITEPWRDNZ1 \|
115	126	PBIASSPEEDCTRL0 \| PBIASLITEPWRDNZ0,
116	127	&t2_base->pbias_lite);
117	128
	129	+#ifdef CONFIG_MMC_OMAP36XX_PINS
	130	+ if (get_cpu_family() == CPU_OMAP36XX)
	131	+ /* Enable extended drain IO after changing PBIAS */
	132	+ writel(wkup_ctrl \|
	133	+ OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
	134	+ OMAP34XX_CTRL_WKUP_CTRL);
	135	+#endif
118	136	writel(readl(&t2_base->devconf0) \| MMCSDIO1ADPCLKISEL,
119	137	&t2_base->devconf0);
120	138