mmc/dw_mmc: Fix clock divider calculation error for bypass mode

To fix the clock divider calculation error when the controller clock same as the operating frequency. This is known as bypass mode. In this mode, the divider should be 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Mischa Jonker <mjonker@synopsys.com>

mmc/dw_mmc: Fix clock divider calculation error for bypass mode
To fix the clock divider calculation error when the controller clock same as the operating frequency. This is known as bypass mode. In this mode, the divider should be 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Mischa Jonker <mjonker@synopsys.com>
Chin Liang See · Pantelis Antoniou
1 parent dae0f5c644
Showing 1 changed file with 4 additions and 1 deletions Side-by-side Diff
drivers/mmc/dw_mmc.c
@@ -245,7 +245,10 @@
 		return -EINVAL;
 	}
  
-	div = DIV_ROUND_UP(sclk, 2 * freq);
+	if (sclk == freq)
+		div = 0;	/* bypass mode */
+	else
+		div = DIV_ROUND_UP(sclk, 2 * freq);
  
 	dwmci_writel(host, DWMCI_CLKENA, 0);
 	dwmci_writel(host, DWMCI_CLKSRC, 0);
...	...	@@ -245,7 +245,10 @@
245	245	return -EINVAL;
246	246	}
247	247
248		- div = DIV_ROUND_UP(sclk, 2 * freq);
	248	+ if (sclk == freq)
	249	+ div = 0; /* bypass mode */
	250	+ else
	251	+ div = DIV_ROUND_UP(sclk, 2 * freq);
249	252
250	253	dwmci_writel(host, DWMCI_CLKENA, 0);
251	254	dwmci_writel(host, DWMCI_CLKSRC, 0);